SFARDS SF3301-FC481 STMicroelectronics 28 nm FD-SOI Logic Transistor Characterization
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3 Table of Contents Introduction Device Identification Device Identification Package Photographs Package X-Ray Die Photograph and Die Markings Die at the Gate Level Transistor Universal Curves NMOS and PMOS Universal Curves Normalized per Gate Width NMOS and PMOS Universal Curves Unnormalized Process Analysis Summary Logic Layout Overview at the Gate Level Logic Layout Overview at the Gate Level Detail Logic Back-Gate Well Contacts at the Gate Level Detail Logic NMOS and PMOS Contacted Gate Pitch Logic Process Summary Transistor Characterization Setup Logic Electrical Measurements Performed Transfer Characteristic Measurement Ranges Measurement Sample Typical NMOS Characterization Results AFP Image of the Measurement Area for NMOS Logic Transistor 2 Transfer Characteristics for NMOS Logic Transistor 2 (V DS = 1.0 V and 0.05 V) Extrapolated Linear V T for NMOS Logic Transistor 2 (V DS = 0.05 V) Transconductance (g m ) for NMOS Logic Transistor 2 (V DS = 1.0 V) Subthreshold Swing (S) for NMOS Logic Transistor 2 (V DS = 1.0 V) Transfer Characteristics Versus V DS for NMOS Logic Transistor 2 DIBL (ΔV GS /ΔV DS ) for NMOS Logic Transistor 2 Back-Gate Bias Transfer Characteristics for NMOS Logic Transistor 2 (V DS = 0.05 V) Back-Gate Bias Extrapolated Linear V T for NMOS Logic Transistor 2 (V DS = 0.05 V) NMOS Logic Transistor Characteristics Summary Table (V WELL = 0 V, V DS = 1.0 V)
4 Table of Contents Typical PMOS Characterization Results AFP Image of Measurement Area for PMOS Logic Transistor 1 Transfer Characteristics for PMOS Logic Transistor 1 (V DS = 1.0 V and 0.05 V) Extrapolated Linear V T for PMOS Logic Transistor 1 (V DS = 0.05 V) Transconductance (gm) for PMOS Logic Transistor 1 (V DS = 1.0 V) Subthreshold Swing (S) for PMOS Logic Transistor 1 (V DS = 1.0 V) Transfer Characteristics Versus V DS for Logic PMOS Transistor 1 DIBL (ΔV GS /ΔV DS ) for Logic PMOS Transistor 1 Back-Gate Bias Transfer Characteristics for PMOS Logic Transistor 1 (V DS = 0.05 V) Back-Gate Bias Extrapolated Linear V T for PMOS Logic Transistor 1 (V DS = 0.05 V) PMOS Transistor Characteristics Summary Table (V WELL = 0 V, V DS = 1.0 V) Average Logic V t,lin Values Versus Back-Gate Bias (V well ) Statement of Measurement Uncertainty and Scope Variation About Chipworks
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