September 21, 2005 Peregrine Semiconductor PE4268 Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Inroduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Transistor and Poly 3.7 Switch Gates 3.8 Capacitors and Resistors 3.9 Isolation 3.10 Silicon-on-Sapphire (SOS) 4 Materials Analysis 4.1 TEM-EDS Analysis of the Dielectrics 4.2 TEM-EDS Analysis of the Metal 1 4.3 TEM-EDS Transistor and Substrate 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions Report Evaluation
Overview 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Top-View Package Pin-Out 2.1.4 Plan-View Package X-Ray 2.1.5 Die Photograph 2.1.6 Die Marking 1 2.1.7 Die Marking 2 2.1.8 Die Marking 3 2.1.9 Annotated Die Photograph at Polycide 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Die Corner 3 2.2.4 Die Corner 4 2.2.5 Minimum Pitch Bond Pads 2.2.6 Diffusion Resistors 2.2.7 MIS Capacitors 3 Process Analysis 3.1.1 General-View of PE4268 3.1.2 Die Edge 3.1.3 Die Seal 3.2.1 Bond Pad 3.2.2 Left End Bond Pad 3.3.1 Passivation 3.3.2 Intermetal Dielectric 3.3.3 Oxide Seed Layer 3.3.4 PMD 3.3.5 TEM PMD Layers 3.4.1 Minimum Pitch Metal 2 3.4.2 TEM Metal 2 3.4.3 TEM Metal 2 TiN Cap Layer 3.4.4 TEM Metal 2 Ti Adhesion Layer 3.4.5 Minimum Pitch Metal 1 3.4.6 TEM Metal 1 TiN Cap Layer 1-1
Overview 3.4.7 TEM Metal 1 TiN Barrier and Ti Adhesion Layers 3.5.1 Minimum Pitch Vias 3.5.2 Minimum Pitch Contacts to Diffusion 3.5.3 TEM Contact Bottom 3.5.4 Minimum Pitch Contacts to Polycide 3.6.1 Minimum Gate Length NMOS Transistor 3.6.2 Minimum Gate Length PMOS Transistor 3.6.3 TEM Peripheral NMOS Transistor 3.6.4 TEM Gate Polycide and Si Channel 3.6.5 TEM Peripheral Gate Oxide 3.6.6 Minimum Pitch Polycide 3.7.1 NMOS Switch Transistor 3.7.2 TEM Switch Transistor 3.7.3 TEM Gate Edge 3.7.4 TEM Switch Transistor Gate Oxide 3.8.1 Silicon Resistors and LOCOS 3.8.2 Silicon Resistor 3.8.3 Upper Capacitor Plate and Contact 3.8.4 Lower Capacitor Plate and Contact 3.9.1 Minimum Width Isolation 3.9.2 Poly Over Isolation 3.10.1 Silicon-on-Sapphire 3.10.2 Silicon-Sapphire Interface 3.10.3 Epitaxial Silicon Diffraction Pattern 3.10.4 Sapphire Substrate Diffraction Pattern 4 Materials Analysis 4.1.1 TEM-EDS Spectra of Silicon Nitride and PSG Passivation 4.1.2 TEM-EDS Spectra of IMD Layers 4.1.3 TEM-EDS Spectra of PMD Layers 4.2.1 TEM-EDS Metal 1 Layer 4.3.1 TEM-EDS Gates 4.3.2 TEM-EDS Sapphire Substrate 1-2
Overview 1.2 List of Tables 1.5.1 Device Summary 1.6.1 Process Summary 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Transistor and Polycide Dimensions 3.7.1 Switch Transistor Dimensions 1-3
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