HD6672 (LCD-II/E2) (Dot Matrix Liquid Crystal Display Controller/Driver) Description The HD6672 LCD-II/E2 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. A single LCD-II/E2 can display up to two 2- character lines. However, with the addition of HD44 drivers, a maximum of up to two 4- character lines can be displayed. The low 3-V power supply of the LCD-II/E2 under development is suitable for any portable batterydriven product requiring low power dissipation. Features 5 7 and 5 dot matrix possible 8 8-bit display RAM (8 characters max.) 7,2-bit character generator ROM 6 character fonts (5 7 dot) 32 character fonts (5 dot) 64 8-bit character generator RAM 8 character fonts (5 7 dot) 4 character fonts (5 dot) 6-common -segment liquid crystal display driver Programmable duty cycles /8 for one line of 5 7 dots with cursor / for one line of 5 dots with cursor /6 for two lines of 5 7 dots with cursor Maximum display characters One line /8 duty cycle, 2-char. -line (no extension), 28-char. -line (extended with one HD44R), 8-char. -line (max. extension with eight HD44s). / duty cycle, 2-char. -line (no extension), 28-char. -line (extended with one HD44R), 8- char. -line (max. extension with eight HD44Rs) Two lines /6 duty cycle, 2-char. 2-line (no extension), 28-char. 2-line (extended with one HD44R), 4-char. 2-line (max. extension with eight HD44Rs) Wide range of instruction functions Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift Choice of power supply (V CC ): 4.5 to 5.5 V (standard), 2.7 to 5.5 V (low voltage) Automatic reset circuit that initializes the controller/driver after power on (standard version only) Independent LCD drive voltage driven off of the logic power supply (V CC ): 3. to 8.3 V
HD6672 Ordering Information Type No. Package Operating Voltage ROM Font HCD6672RAL Chip 2.7 to 5.5 V Standard Japanese HD6672RAF 44-pin plastic QFP (FP-44A) 4.5 to 5.5 V font HD6672RAFL 44-pin plastic QFP (FP-44A) 2.7 to 5.5 V HD6672RAF 44-pin plastic QFP (FP-44A) 4.5 to 5.5 V Japanese font for comunication system HD6672RA2F 44-pin plastic QFP (FP-44A) 4.5 to 5.5 V European font HCD6672RBxxL Chip 2.7 to 5.5 V Custom font HD6672RBxxF 44-pin plastic QFP (FP-44A) 4.5 to 5.5 V HD6672RBxxFL 44-pin plastic QFP (FP-44A) 2.7 to 5.5 V Note: xx: ROM code No. 269
HD6672 LCD-II Family Comparison Item LCD-II (HD4478U) LCD-II/E2 (HD6672) Power supply voltage 2.7 to 5.5 V 5 V ±% (standard) 2.7 to 5.5 V (low voltage) Liquid crystal drive /4 bias 3. to V 3. to 8.3 V voltage V LCD /5 bias 3. to V 3. to 8.3 V Maximum display 6 digits 4 digits digits per chip (8 digits 2 lines) (2 digits 2 lines) Display duty cycle /8, /, and /6 /8, /, and /6 CGROM 9,6 bits 7,2 bits (28 character fonts (6 character fonts for for 5 8 dot and 5 7 dot and 32 character fonts 32 character fonts for for 5 dot) 5 dot) CGRAM 64 bytes 64 bytes DDRAM 8 bytes 8 bytes Segment signals 4 Common signals 6 6 Liquid crystal drive waveform A B Ladder resistor for LCD External External power supply Clock source External resistor External resistor or external or external clock clock R f oscillation frequency 27 khz ±3% 32 khz ±3% (frame frequency) (59 to Hz for /8 and (69 to 28 Hz for /8 and /6 duty cycles; 43 to 8 Hz /6 duty cycles; 5 to 93 Hz for / duty cycle) for / duty cycle) R f resistance 9 kω ±2% (5 V) 68 kω ±2% (5 V) 75 kω ±2% (3 V) 56 kω ±2% (3 V) Instructions Fully compatible within the LCD-II family CPU bus timing MHz MHz Package FP-8B, TFP-8, and 8-pin 44-pin bare chip (no package) bare chip (no package) and FP-44A 27
HD6672 LCD-II/E2 Block Diagram Reset circuit ACL OSC OSC 2 CPG EXT Timing generator CL CL 2 M 8 Instruction register (IR) 7 D RS R/W E MPU inter- face Instruction decoder Display data RAM (DD RAM) 8 8 bits 6-bit shift register Common signal driver COM to COM 6 6 DB to DB 4 7 DB to DB 3 Input/ output buffer 8 7 Data register (DR) Busy flag Address counter 7 8 7 8 8 8 -bit shift register -bit latch circuit Segment signal driver LCD drive voltage selector to TEST GND Character generator RAM (CG RAM) 64 bytes Character generator ROM (CG ROM) 7,2 bits Cursor and blink controller 5 5 Parallel/serial converter and attribute circuit V CC V V 2 V 3 V 4 V 5 27
HD6672 LCD-II/E2 Pad Arrangement 34 33 32 3 3 29 28 27 26 25 24 23 22 2 2 9 8 7 6 5 4 3 2 9 8 7 6 5 4 3 2 GND OSC 2 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 26 27 28 29 3 3 32 33 34 35 36 44 43 42 4 4 39 38 37 36 35 34 33 32 3 3 29 28 27 26 25 24 23 22 2 2 9 8 7 6 5 4 3 2 9 8 7 6 5 4 3 2 99 98 97 96 95 94 93 92 9 9 89 88 87 86 85 84 83 82 8 8 79 78 77 76 75 74 73 37 38 39 4 4 42 43 44 45 46 47 48 49 5 5 52 53 54 55 56 57 58 59 6 6 62 63 64 65 66 67 68 69 7 7 72 7 72 73 74 75 76 77 78 79 8 8 82 83 84 85 86 87 88 89 9 9 92 93 94 95 96 97 98 99 COM 6 COM 5 COM 4 COM 3 COM2 COM OSC V CC V CC V V 2 V 3 V 4 V 5 CL CL 2 M D EXT TEST GND RS R/W E DB DB DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 COM COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM 35 36 37 38 39 4 4 42 43 44 45 46 47 48 49 5 5 52 53 54 55 56 57 58 59 6 6 62 63 64 65 66 67 68 69 7 HD6672 Type code (Top view) Note: : Test pins to be grounded : Power supply pins : Power supply pins (ground) : Input pins : Output pins : Input/Output pins Minimum pad pitch = 3 µm 272
HD6672 HCD6672 Pad Location Coordinates Pad Pad No. Name X (µm) Y (µm) 34 2475 235 2 33 2475 225 3 32 2475 265 4 3 2475 925 5 3 2475 79 6 29 2475 655 7 28 2475 525 8 27 2475 395 9 26 2475 265 25 2475 35 24 2475 5 2 23 2475 875 3 22 2475 745 4 2 2475 65 5 2 2475 485 6 9 2475 355 7 8 2475 225 8 7 2475 95 9 6 2475 35 2 5 2475 65 2 4 2475 295 22 3 2475 425 23 2 2475 555 24 2475 685 25 2475 85 26 9 2475 945 27 8 2475 75 28 7 2475 25 29 6 2475 335 3 5 2475 465 Pad Pad No. Name X (µm) Y (µm) 3 4 2475 6 32 3 2475 735 33 2 2475 87 34 2475 2 35 GND 2475 28 36 OSC 2 2475 2325 37 OSC 2445 2475 38 V CC 235 2475 39 V CC 265 2475 4 V 225 2475 4 V 2 875 2475 42 V 3 745 2475 43 V 4 595 2475 44 V 5 465 2475 45 CL 335 2475 46 CL 2 85 2475 47 M 55 2475 48 D 95 2475 49 EXT 775 2475 5 TEST 625 2475 5 GND 495 2475 52 RS 345 2475 53 R/W 95 2475 54 E 45 2475 55 DB 85 2475 56 DB 235 2475 57 DB 2 365 2475 58 DB 3 55 2475 59 DB 4 645 2475 6 DB 5 795 2475 273
HD6672 Pad Pad No. Name X (µm) Y (µm) 6 DB 6 925 2475 62 DB 7 75 2475 63 COM 25 2475 64 COM 2 335 2475 65 COM 3 465 2475 66 COM 4 595 2475 67 COM 5 725 2475 68 COM 6 855 2475 69 COM 7 99 2475 7 COM 8 225 2475 7 COM 9 2265 2475 72 COM 24 2475 73 COM 2475 229 74 COM 2 2475 245 75 COM 3 2475 25 76 COM 4 2475 865 77 COM 5 2475 73 78 COM 6 2475 595 79 2475 465 8 99 2475 335 8 98 2475 25 82 97 2475 75 83 96 2475 945 84 95 2475 85 85 94 2475 685 86 93 2475 555 87 92 2475 425 88 9 2475 295 89 9 2475 65 9 89 2475 35 Pad Pad No. Name X (µm) Y (µm) 9 88 2475 95 92 87 2475 225 93 86 2475 355 94 85 2475 485 95 84 2475 65 96 83 2475 745 97 82 2475 875 98 8 2475 5 99 8 2475 35 79 2475 265 78 2475 395 2 77 2475 525 3 76 2475 655 4 75 2475 79 5 74 2475 925 6 73 2475 265 7 72 2475 225 8 7 2475 235 9 7 232 2475 69 275 2475 68 235 2475 2 67 895 2475 3 66 76 2475 4 65 625 2475 5 64 495 2475 6 63 365 2475 7 62 235 2475 8 6 5 2475 9 6 975 2475 2 59 845 2475 274
Pad Pad No. Name X (µm) Y (µm) 2 58 75 2475 22 57 585 2475 23 56 455 2475 24 55 325 2475 25 54 95 2475 26 53 65 2475 27 52 65 2475 28 5 95 2475 29 5 325 2475 3 49 455 2475 3 48 585 2475 32 47 75 2475 HD6672 Pad Pad No. Name X (µm) Y (µm) 33 46 845 2475 34 45 975 2475 35 44 5 2475 36 43 235 2475 37 42 365 2475 38 4 495 2475 39 4 625 2475 4 39 76 2475 4 38 895 2475 42 37 235 2475 43 36 275 2475 44 35 232 2475 Notes:. Coordinates originate from the chip center. 2. The above are preliminary specifications, and may be subject to change. 275
HD6672 HD6672 Pin Arrangement 34 33 32 3 3 29 28 27 26 25 24 23 22 2 2 9 8 7 6 5 4 3 2 9 8 7 6 5 4 3 2 GND OSC 2 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 26 27 28 29 3 3 32 33 34 35 36 44 43 42 4 4 39 38 37 36 35 34 33 32 3 3 29 28 27 26 25 24 23 22 2 2 9 8 7 6 5 4 3 2 9 8 7 6 5 4 3 2 99 98 97 96 95 94 93 92 9 9 89 88 87 86 85 84 83 82 8 8 79 78 77 76 75 74 73 37 38 39 4 4 42 43 44 45 46 47 48 49 5 5 52 53 54 55 56 57 58 59 6 6 62 63 64 65 66 67 68 69 7 7 72 7 72 73 74 75 76 77 78 79 8 8 82 83 84 85 86 87 88 89 9 9 92 93 94 95 96 97 98 99 COM 6 COM 5 COM 4 COM 3 COM2 COM OSC V CC V CC V V 2 V 3 V 4 V 5 CL CL 2 M D EXT TEST GND RS R/W E DB DB DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 COM COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM 35 36 37 38 39 4 4 42 43 44 45 46 47 48 49 5 5 52 53 54 55 56 57 58 59 6 6 62 63 64 65 66 67 68 69 7 FP-44A (Top view) Note: : Test pins to be grounded : Power supply pins : Power supply pins (ground) : Input pins : Output pins : Input/Output pins 276
HD6672 Pin Functions Table Pin Functional Description Device Signal I/O Interfaced with Function RS I MPU Selects registers : Instruction register (for write) Busy flag: address counter (for read) : Data register (for write and read) R/W I MPU Selects read or write : Write : Read E I MPU Starts data read/write DB 4 to DB 7 I/O MPU Four high order bidirectional tristate data bus pins. Used for data transfer between the MPU and the LCD-II/E2. DB 7 can be used as a busy flag. DB to DB 3 I/O MPU Four low order bidirectional tristate data bus pins. Used for data transfer between the MPU and the LCD-II/E2. These pins are not used during 4-bit operation. CL O HD44 Clock to latch serial data D sent to the HD44H driver CL 2 O HD44 Clock to shift serial data D M O HD44 Switch signal for converting the liquid crystal drive waveform to AC D O HD44 Character pattern data corresponding to each segment signal COM to COM 6 O LCD Common signals that are not used are changed to nonselection waveforms. COM 9 to COM 6 are nonselection waveforms at /8 duty factor and COM 2 to COM 6 are non-selection waveforms at / duty factor. to O LCD Segment signals V to V 5 Power supply Power supply for LCD drive V CC, GND Power supply V CC : +5 V or +3 V, GND: V TEST I Test pin, which must be grounded EXT I : Enables extension driver control signals CL, CL 2, M, and D to be output from its corresponding pins. : Drives CL, CL 2, M, and D as tristate, lowering power dissipation. OSC, OSC 2 Pins for connecting the registers of the internal clock oscillation. When the pin input is an external clock, it must be input to OSC. 277
HD6672 Function Description Registers The HD6672 has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DD RAM) and character generator RAM (CG RAM). The IR can only be written from the MPU. The DR temporarily stores data to be written into DD RAM or CG RAM. Data written into the DR from the MPU is automatically written into DD RAM or CG RAM by an internal operation. The DR is also used for data storage when reading data from DD RAM or CG RAM. When address information is written into the IR, data is read and then stored into the DR from DD RAM or CG RAM by an internal operation. Data transfer between the MPU is then completed when the MPU reads the DR. After the read, data in DD RAM or CG RAM at the next address is sent to the DR for the next read from the MPU. By the register selector (RS) signal, these two registers can be selected (table 2). Busy Flag (BF) When the busy flag is, the HD6672 is in the internal operation mode, and the next instruction will not be accepted. When RS = and R/W = (table 2), the busy flag is output to DB 7. The next instruction must be written after ensuring that the busy flag is. Address Counter (AC) The address counter (AC) assigns addresses to both DD RAM and CG RAM. When an address of an instruction is written into the IR, the address information is sent from the IR to the AC. Selection of either DD RAM or CG RAM is also determined concurrently by the instruction. After writing into (reading from) DD RAM or CG RAM, the AC is automatically incremented by (decremented by ). The AC contents are then output to DB to DB 6 when RS = and R/W = (table 2). Table 2 Register Selection RS R/W Operation IR write as an internal operation (display clear, etc.) Read busy flag (DB 7 ) and address counter (DB to DB 6 ) DR write as an internal operation (DR to DD RAM or CG RAM) DR read as an internal operation (DD RAM or CG RAM to DR) 278
HD6672 Display Data RAM (DD RAM) Display data RAM (DD RAM) stores display data represented in 8-bit character codes. Its extended capacity is 8 8 bits, or 8 characters. The area in display data RAM (DD RAM) that is not used for display can be used as general data RAM. See figure for the relationships between DD RAM addresses and positions on the liquid crystal display. The DD RAM address (A DD ) is set in the address counter (AC) as hexadecimal. -line display (N = ) (figure 2) Case : When there are fewer than 8 display characters, the display begins at the head position. For example, if using only the HD6672, 2 characters are displayed. See figure 3. Case 2: For a 28-character display, the HD6672 can be extended using one HD44 and displayed. See figure 4. When the display shift operation is performed, the DD RAM address shifts. See figure 4. Case 3: The relationship between the display position and DD RAM address when the number of display digits is increased through the use of two or more HD44s can be considered as an extension of case #2. Since the increase can be eight digits per additional HD44, up to 8 digits can be displayed by externally connecting eight HD44s. See figure 5. When the display shift operation is performed, the DD RAM address shifts. See figure 3. AC (hexadecimal) High order bits Low order bits Example: DD RAM address 4E AC6 AC5 AC4 AC3 AC2 AC AC Figure DD RAM Address Display position (digit) 2 3 4 5 79 8 DD RAM address (hexadecimal) 2 3 4.................. 4E 4F Figure 2 -Line Display 279
HD6672 Display position 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 DD RAM address 2 3 4 5 6 7 8 9 A B C D E F 2 3 For shift left 2 3 4 5 6 7 8 9 A B C D E F 2 3 4 For shift right 4F 2 3 4 5 6 7 8 9 A B C D E F 2 Figure 3 -Line by 2-Character Display Example Display position 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 26 27 28 DD RAM address 2 3 4 5 6 7 8 9 A BC D E F 2 3 4 5 6 7 8 9 A B LCD-II/E2 display HD44 display For shift left 2 3 4 5 6 7 8 9 A BC D E F 2 3 4 5 6 7 8 9 A B C For shift right 4F 2 3 4 5 6 7 8 9 A BC D E F 2 3 4 5 6 7 8 9 A Figure 4 -Line by 28-Character Display Example Display position 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 26 27 28 DD RAM address 2 3 4 5 6 7 8 9 A BC D E F 2 3 4 5 6 7 8 9 A B 77 78 79 8... 4C 4D 4E 4F LCD-II/E2 display st HD44 display 8th HD44 display Figure 5 -Line by 8-Character Display Example 28
HD6672 2-line display (N = ) (figure 6) Case : When the number of display characters is less than 4 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the HD6672 is used, 2 characters 2 lines are displayed. See figure 7. When display shift operation is performed, the DD RAM address shifts. See figure 7. Display position 2 3 4 5 39 4 DD RAM address (hexadecimal) 2 3 4.................. 26 27 4 4 42 43 44.................. 66 67 Figure 6 2-Line Display Display position 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 DD RAM address 2 3 4 5 6 7 8 9 A B C D E F 2 3 4 4 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 5 5 52 53 For shift left 2 3 4 5 6 7 8 9 A B C D E F 2 3 4 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 5 5 52 53 4 54 For shift right 27 2 3 4 5 6 7 8 9 A B C D E F 2 67 4 4 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 5 5 52 Figure 7 2-Line by 2-Character Display Example 28
HD6672 Case 2: For a 28-character 2-line display, the HD6672 can be extended using one HD44. See figure 8. When display shift operation is performed, the DD RAM address shifts. See figure 8. Case 3: The relationship between the display position and DD RAM address when the number of display digits is increased by using two or more HD44s, can be considered as an extension of case #2. See figure 9. Since the increase can be 8 digits 2 lines for each additional HD44, up to 4 digits 2 lines can be displayed by externally connecting three HD44s. Display position 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 26 27 28 DD RAM address 2 3 4 5 6 7 8 9 A BC D E F 2 3 4 5 6 7 8 9 A B 4 4 42 43 44 45 46 47 48 49 4A 4B4C 4D 4E 4F 5 5 52 53 54 55 56 57 58 59 5A 5B LCD-II/E2 display HD44 display For shift left 2 3 4 5 6 7 8 9 A BC D E F 2 3 4 5 6 7 8 9 A B C 4 42 43 44 45 46 47 48 49 4A 4B4C 4D 4E 4F 5 5 52 53 54 55 56 57 58 59 5A 5B 5C For shift right 27 2 3 4 5 6 7 8 9 A BC D E F 2 3 4 5 6 7 8 9 A 67 4 4 42 43 44 45 46 47 48 49 4A 4B4C 4D 4E 4F 5 5 52 53 54 55 56 57 58 59 5A Figure 8 2-Line by 28-Character Display Example Display position DD RAM address 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 26 27 28 37 38 39 4 2 3 4 5 6 7 8 9 A BC D E F 2 3 4 5 6 7 8 9 A B... 24 25 26 27 4 4 42 43 44 45 46 47 48 49 4A 4B4C 4D 4E 4F 5 5 52 53 54 55 56 57 58 59 5A 5B... 64 65 66 67 LCD-II/E2 display st HD44 display 3rd HD44 display Figure 9 2-Line by 4-Character Display Example 282
HD6672 Character Generator ROM (CG ROM) The character generator ROM generates 5 7 dot or 5 dot character patterns from 8-bit character codes (table 5). It can generate 6 5 7 dot character patterns and 32 5 dot character patterns. User-defined character patterns are also available by mask-programmed ROM. Character Generator RAM (CG RAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 7 dots, eight character patterns can be written, and for 5 dots, four character patterns can be written. Write the character codes at the addresses shown as the left column of table 5 to show the character patterns stored in CG RAM. See table 6 for the relationship between CG RAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. Modifying Character Patterns Character pattern development procedure The following operations correspond to the numbers listed in figure :. Determine the correspondence between character codes and character patterns. 2. Create a listing indicating the correspondence between EPROM addresses and data. 3. Program the character patterns into the EPROM. 4. Send the EPROM to Hitachi. 5. Computer processing on the EPROM is performed at Hitachi to create a character pattern listing, which is sent to the user. 6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples are sent to the user for evaluation. When it is confirmed by the user that the character patterns are correctly written, mass production of the LSI proceeds at Hitachi. 283
HD6672 Hitachi User Start Computer processing Determine character patterns Create character pattern listing 5 Create EPROM address data listing 2 Evaluate character patterns Write EPROM 3 No OK? EPROM Hitachi 4 Yes Art work M/T Masking Trial Sample Sample evaluation 6 OK? No Yes Mass production Note: For a description of the numbers used in this figure, refer to the preceding page. Figure Character Pattern Development Procedure 284
HD6672 Programming character patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM. The LCD-II/E2 character generator ROM can generate 6 5 7 dot character patterns and 32 5 dot character patterns for a total of 92 different character patterns. 5 7 dot character pattern EPROM address data and character pattern data correspond with each other to form a 5 7 dot character pattern (table 3). Table 3 Example of Correspondence between EPROM Address Data and Character Pattern (5 7 dots) EPROM Address A A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A A Data LSB O 4 O 3 O 2 O O Character code Line position Fill line 8 (cursor position) with s Notes:. EPROM addresses A to A 3 correspond to a character code. 2. EPROM addresses A 2 to A specify a line position of the character pattern. 3. EPROM data O 4 to O correspond to character pattern data. 4. A lit display position (black) corresponds to a. 5. Line 8 (cursor position) of the character pattern must be blanked with s. 6. EPROM data O 5 to O 7 are not used. 285
HD6672 5 dot character pattern EPROM address data and character pattern data correspond with each other to form a 5 dot character pattern (table 4). Handling unused character patterns. EPROM data outside the character pattern area: Ignored by the character generator ROM for display operation so or is arbitrary. 2. EPROM data in CG RAM area: Ignored by the character generator ROM for display operation so or is arbitrary. 3. EPROM data used when the user does not use any HD6672 character pattern: According to the user application, handled in one of the two ways listed as follows. a. When unused character patterns are not programmed: If an unused character code is written into DD RAM, all its dots are lit. By not programing a character pattern, all of its bits become lit. (This is due to the EPROM being filled with s after it is erased.) b. When unused character patterns are programmed as s: Nothing is displayed even if unused character codes are written into DD RAM. (This is equivalent to a space.) Table 4 Example of Correspondence between EPROM Address Data and Character Pattern (5 dots) EPROM Address A A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A A Data LSB O 4 O 3 O 2 O O Character code Line position Fill line (cursor position) with s Notes:. EPROM addresses A to A 3 correspond to a character code. Set A 8 and A 9 of character pattern lines 9,, and to s. 2. EPROM addresses A 2 to A specify a line position of the character pattern. 3. EPROM data O 4 to O correspond to character pattern data. 4. A lit display position (black) corresponds to a. 5. Blank out line (cursor position) of the character pattern with s. 6. EPROM data O 5 to O 7 are not used. 286
Table 5 Correspondence between Character Codes and Character Patterns (ROM code: A) Lower 4 Bits Upper 4 Bits xxxx CG RAM () HD6672 xxxx (2) xxxx (3) xxxx (4) xxxx (5) xxxx (6) xxxx (7) xxxx (8) xxxx () xxxx (2) xxxx (3) xxxx (4) xxxx (5) xxxx (6) xxxx (7) xxxx (8) Note: The user can specify any pattern for character-generator RAM. 287
HD6672 Table 5 Correspondence between Character Codes and Character Patterns (ROM code: A) Lower 4 Bits Upper 4 Bits xxxx CG RAM () xxxx (2) xxxx (3) xxxx (4) xxxx (5) xxxx (6) xxxx (7) xxxx (8) xxxx () xxxx (2) xxxx (3) xxxx (4) xxxx (5) xxxx (6) xxxx (7) xxxx (8) 288
HD6672 Table 5 Correspondence between Character Codes and Character Patterns (ROM code: A2) Lower 4 Bits Upper 4 Bits xxxx CG RAM () xxxx (2) xxxx (3) xxxx (4) xxxx (5) xxxx (6) xxxx (7) xxxx (8) xxxx () xxxx (2) xxxx (3) xxxx (4) xxxx (5) xxxx (6) xxxx (7) xxxx (8) 289
HD6672 Table 6 Relationship between CG RAM Addresses, Character Codes (DD RAM) and Character Patterns (CG RAM Data) For 5 7 dot character patterns Character Codes (DD RAM data) 7 6 5 4 3 2 High Low CG RAM Address 5 4 3 2 High Low Character Patterns (CG RAM data) 7 6 5 4 3 2 High Low Character pattern Cursor position Notes:. Character code bits to 2 correspond to CG RAM address bits 3 to 5 (3 bits: 8 types). 2. CG RAM address bits to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at as the cursor display. If the 8th line data is, bits will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CG RAM data bits to 4 (bit 4 being at the left ). Since CG RAM data bits 5 to 7 are not used for display, they can be used for general data RAM. 4. As shown tables 5 and 6, CG RAM character patterns are selected when character code bits 4 to 7 are all. However, since character code bit 3 has no effect, the R display example above can be selected by either character code H or 8H. 5. for CG RAM data corresponds to display selection and to non-selection. Indicates no effect. 29
HD6672 Table 6 Relationship between CG RAM Addresses, Character Codes (DD RAM) and Character Patterns (CG RAM Data) (cont) For 5 dot character patterns Character Codes (DD RAM data) 7 6 5 4 3 2 CG RAM Address 5 4 3 2 Character Patterns (CG RAM data) 7 6 5 4 3 2 High Low High Low High Low Character pattern Cursor position Notes:. Character code bits and 2 correspond to CG RAM address bits 4 and 5 (2 bits: 4 types). 2. CG RAM address bits to 3 designate the character pattern line position. The th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the th line data corresponding to the cursor display positon at as the cursor display. If the th line data is, bits will light up the th line regardless of the cursor presence. Since lines 2 to 6 are not used for display, they can be used for general data RAM. 3. Character pattern row positions are the same as 5 7 dot character pattern positions. 4. CG RAM character patterns are selected when character code bits 4 to 7 are all. However, since character code bits and 3 have no effect, the P display example above can be selected by character codes H, H, 8H, and 9H. 5. for CG RAM data corresponds to display selection and to non-selection. Indicates no effect. 29
HD6672 Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DD RAM, CG ROM and CG RAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DD RAM, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area. This circuit also generates timing signals for the operation of the externally connected HD44 driver. Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 6 common signal drivers and segment signal drivers. When the character font and number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output non-selection waveforms. The segment signal driver has essentially the same configuration as the HD44 driver. Character pattern data is sent serially through a -bit shift register and latched when all needed data has arrived. The latched data then enables the driver to generate drive waveform outputs. The serial data can be sent to externally cascaded HD44s used for displaying extended digit numbers. Sending serial data always starts at the display data character pattern corresponding to the last address of the display data RAM (DD RAM). Since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, the HD6672 drives from the head display. The rest of the display, corresponding to latter addresses, are added with each additional HD44. Cursor/Blink Control Circuit The cursor/blink control circuit generates the cursor or character blinking. The cursor or the blinking will appear with the digit located at the display data RAM (DD RAM) address set in the address counter (AC). For example (figure ), when the address counter is 8H, the cursor position is displayed at DD RAM address 8H. AC6 AC5 AC4 AC3 AC2 AC AC AC For a -line display Display position DD RAM address (hexadecimal) 2 3 2 4 3 5 4 6 5 7 6 8 7 9 8 9 A For a 2-line display cursor position Display position 2 3 4 5 6 7 8 9 DD RAM address (hexadecimal) 4 4 2 42 3 43 4 44 5 45 6 46 7 47 8 48 9 49 A 4A cursor position Note: The cursor or blinking appears when the address counter (AC) selects the character generator RAM (CG RAM). However, the cursor and blinking become meaningless. The cursor or blinking is displayed in the meaningless position when the AC is a CG RAM address. 292 Figure Cursor/Blink Display Example
HD6672 Interfacing to the MPU The HD6672 can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit MPUs. For 4-bit interface data, only four bus lines (DB 4 to DB 7 ) are used for transfer. Bus lines DB to DB 3 are disabled. The data transfer between the HD6672 and the MPU is completed after the 4- bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB 4 to DB 7 ) are transferred before the four low order bits (for 8-bit operation, DB to DB 3 ). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data. For 8-bit interface data, all eight bus lines (DB to DB 7 ) are used. RS R/W E DB 7 IR7 IR3 BF AC3 DR7 DR3 DB 6 IR6 IR2 AC 6 AC2 DR6 DR2 DB 5 IR5 IR AC 5 AC DR5 DR DB4 IR4 IR AC 4 AC DR4 DR Instruction register (IR) write Busy flag (BF) and address counter (AC) read Data register (DR) read Figure 2 4-Bit Transfer Example 293
HD6672 Reset Function Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the HD6672 when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = ). The busy state lasts for ms after V CC rises to 4.5 V.. Display clear 2. Function set: DL = ; 8-bit interface data N = ; -line display F = ; 5 7 dot character font 3. Display on/off control: D = ; Display off C = ; Cursor off B = ; Blinking off 4. Entry mode set: I/D = ; Increment by S = ; No shift Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the HD6672. For such a case, initialization must be performed by the MPU as explained in the section, Initializing by Instruction. Instructions Outline Only the instruction register (IR) and the data register (DR) of the HD6672 can be controlled by the MPU. Before starting the internal operation of the HD6672, control information is temporarily stored into these registers to allow interfacing with various MPUs, which operate at different speeds, or various peripheral control devices. The internal operation of the HD6672 is determined by signals sent from the MPU. These signals, which include register selection (RS), read/write (R/W), and the data bus (DB to DB 7 ), make up the HD6672 instructions (table 7). There are four categories of instructions that: Designate HD6672 functions, such as display format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Perform miscellaneous functions Normally, instructions that perform data transfer with internal RAM are used the most. However, auto-incrementation by (or auto-decrementation by ) of internal HD6672 RAM addresses after each data write can lighten the program load of the MPU. Since the display shift instruction (table 2) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency. When an instruction is being executed for internal operation, no instruction other than the busy flag/address read instruction can be executed. Because the busy flag is set to while an instruction is being executed, check it to make sure it is before sending another instruction from the MPU. Note: Be sure the HD6672 is not in the busy state (BF = ) before sending an instruction from the MPU to the HD6672. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to table 7 for the list of each instruc-tion execution time. 294
HD6672 Table 7 Instructions Code Execution Time (max) (when f cp or Instruction RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Description f OSC is 32 khz) Clear Clears entire display and.28 ms display sets DD RAM address in address counter. Return Sets DD RAM address in.28 ms home address counter. Also returns display from being shifted to original position. DD RAM contents remain unchanged. Entry I/D S Sets cursor move direction 3 µs mode set and specifies display shift. These operations are performed during data write and read. Display D C B Sets entire display (D) 3 µs on/off on/off, cursor on/off (C), control and blinking of cursor position character (B). Cursor or S/C R/L Moves cursor and shifts 3 µs display display without changing shift DD RAM contents. Function DL N F Sets interface data length 3 µs set (DL), number of display lines (L), and character font (F). Set CG A CG A CG A CG A CG A CG A CG Sets CG RAM address. 3 µs RAM CG RAM data is sent and address received after this setting. Set DD A DD A DD A DD A DD A DD A DD A DD Sets DD RAM address. 3 µs RAM DD RAM data is sent and address received after this setting. Read busy BF AC AC AC AC AC AC AC Reads busy flag (BF) µs flag & indicating internal operation address is being performed and reads address counter contents. 295
HD6672 Table 7 Instructions (cont) Code Execution Time (max) (when f cp or Instruction RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Description f OSC is 32 khz) Write data Write data Writes data into DD RAM 3 µs to CG or or CG RAM. t ADD = 4.7 µs DD RAM Read data Read data Reads data from DD RAM 3 µs from CG or or CG RAM. t ADD = 4.7 µs DD RAM I/D = : Increment DD RAM: Display data Execution time I/D = : Decrement RAM changes when S = : Accompanies display shift CG RAM: Character frequency changes S/C = : Display shift generator RAM Example: S/C = : Cursor move A CG : CG RAM address When f cp or f OSC R/L = : Shift to the right A DD : DD RAM address is 27 khz, R/L = : Shift to the left (corresponds to DL = : 8 bits, DL = : 4 bits cursor address) 3 µs 32 = 37 µs N = : 2 lines, N = : line AC: Address counter 27 F = : 5 dots, F = : 5 7 dots used for both DD and BF = : Internally operating CG RAM addresses BF = : Instructions acceptable Note: indicates no effect. After execution of the CG RAM/DD RAM data write or read instruction, the RAM address counter is incremented or decremented by. The RAM address counter is updated after the busy flag turns off. In figure 3, t ADD is the time elapsed after the busy flag turns off until the address counter is updated. Busy signal (DB 7 pin) Busy state Address counter (DB to DB 6 pins) A A + t ADD Note: t ADD depends on the operation frequency t ADD =.5/(f cp or f OSC ) seconds Figure 3 Address Counter Update 296
HD6672 Instruction Description Clear Display Clear display writes space code 2H (character pattern for character code 2H must be a blank pattern) into all DD RAM addresses. It then sets DD RAM address into the address counter, and returns the display to its original status if it was shifted. In other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). It also sets I/D to (increment mode) in entry mode. S of entry mode does not change. Return Home Return home sets DD RAM address into the address counter, and returns the display to its original status if it was shifted. The DD RAM contents do not change. The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). Entry Mode Set I/D: Increments (I/D = ) or decrements (I/D = ) the DD RAM address by when a character code is written into or read from DD RAM. The cursor or blinking moves to the right when incremented by and to the left when decremented by. The same applies to writing and reading of CG RAM. S: Shifts the entire display either to the right (I/D = ) or to the left (I/D = ) when S is. The display does not shift if S is. If S is, it will seem as if the cursor does not move but the display does. The display does not shift when reading from DD RAM. Also, writing into or reading out from CG RAM does not shift the display. Display On/Off Control D: The display is on when D is and off when D is. When off, the display data remains in DD RAM, but can be displayed instantly by setting D to. C: The cursor is displayed when C is and not displayed when C is. Even if the cursor disappears, the function of I/D or other specifications will not change during display data write. The cursor is displayed using 5 dots in the 8th line for 5 7 dot character font selection and in the th line for the 5 dot character font selection (figure 6). B: The character indicated by the cursor blinks when B is (figure 6). The blinking is displayed as switching between all blank dots and displayed characters at a speed of 32-ms intervals when f cp or f OSC is 32 khz. The cursor and blinking can be set to display simultaneously. (The blinking frequency changes according to f OSC or the reciprocal of f cp. For example, when f cp is 27 khz, 32 32/27 = 379.2 ms.) Cursor or Display Shift Cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (table 8). This function is used to correct or search the display. In a 2-line display, the cursor moves to the second line when it passes the 4th digit of the first line. Note that the first and second line displays will shift at the same time. When the displayed data is shifted repeatedly each line moves only horizontally. The second line display does not shift into the first line position. The address counter (AC) contents will not change if the only action performed is a display shift. Function Set DL: Sets the interface data length. Data is sent or received in 8-bit lengths (DB 7 to DB ) when DL is, and in 4-bit lengths (DB 7 to DB 4 ) when DL is. When 4-bit length is selected, data must be sent or received twice. 297
HD6672 N: Sets the number of display lines. F: Sets the character font. Note: Perform the function at the head of the program before executing any instructions (except for the read busy flag and address instruction). From this point, the function set instruction cannot be executed unless the interface data length is changed. Set CG RAM Address Set CG RAM address sets the CG RAM address binary AAAAAA into the address counter. Data is then written to or read from the MPU for CG RAM. RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Clear display Code RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Return home Code Note: Don t care. RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Entry mode set Code I/D S RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Display on/off control Code D C B Figure 4 RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Cursor or display shift Code S/C R/L Note: Don t care. RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Function set Code DL N F Note: Don t care. RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Set CG RAM address Code A A A A A A Highest order bit Lowest order bit Figure 5 298
HD6672 Set DD RAM Address Set DD RAM address sets the DD RAM address binary AAAAAAA into the address counter. Data is then written to or read from the MPU for DD RAM. However, when N is (-line display), AAAAAAA can be H to 4FH. When N is (2-line display), AAAAAAA can be H to 27H for the first line, and 4H to 67H for the second line. Read Busy Flag and Address Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction. If BF is, the internal operation is in progress. The next instruction will not be accepted until BF is reset to. Check the BF status before the next write operation. At the same time, the value of the address counter in binary AAAAAAA is read out. This address counter is used by both CG and DD RAM addresses, and its value is determined by the previous instruction. The address contents are the same as for instructions set CG RAM address and set DD RAM address. Table 8 Shift Function S/C R/L Shifts the cursor position to the left. (AC is decremented by one.) Shifts the cursor position to the right. (AC is incremented by one.) Shifts the entire display to the left. The cursor follows the display shift. Shifts the entire display to the right. The cursor follows the display shift. Table 9 Function Set No. of Display Character Duty N F Lines Font Factor Remarks 5 7 dots /8 5 dots / 2 5 7 dots /6 Cannot display two lines for 5 dot character font. Note: Indicates don t care. 299
HD6672 Cursor 5 7 dot 5 dot Alternating display character font character font Cursor display example Blink display example Figure 6 Cursor and Blinking RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Set DD RAM address Code A A A A A A A Highest order bit Lowest order bit RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Read busy flag and address Code BF A A A A A A A Highest order bit Lowest order bit Figure 7 3
HD6672 Write Data to CG or DD RAM Write data to CG or DD RAM writes 8-bit binary data DDDDDDDD to CG or DD RAM. To write into CG or DD RAM is determined by the previous specification of the CG RAM or DD RAM address setting. After a write, the address is automatically incremented or decremented by according to the entry mode. The entry mode also determines the display shift. Read Data from CG or DD RAM Read data from CG or DD RAM reads 8-bit binary data DDDDDDDD from CG or DD RAM. The previous designation determines whether CG or DD RAM is to be read. Before entering this read instruction, either CG RAM or DD RAM address set instruction must be executed. If not executed, the first read data will be invalid. When serially executing read instructions, the next address data is normally read from the second read. The address set instructions need not be executed just before this read instruction when shifting the cursor by the cursor shift instruction (when reading out DD RAM). The operation of the cursor shift instruction is the same as the set DD RAM address instruction. After a read, the entry mode automatically increases or decreases the address by. However, display shift is not executed regardless of the entry mode. Note: The address counter (AC) is automatically incremented or decremented by after the write instructions to CG RAM or DD RAM are executed. The RAM data selected by the AC cannot be read out at this time even if read instructions are executed. Therefore, to correctly read data, execute either the address set instruction or cursor shift instruction (only with DD RAM), then just before reading the desired data, execute the read instruction from the second time the read instruction is sent. RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Write data to CG or DD RAM Code D D D D D D D D Higher order bits Lower order bits RS R/W DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB DB Read data from CG or DD RAM Code D D D D D D D D Higher order bits Lower order bits Figure 8 3
HD6672 HD68 HD6672 VMA ø2 A 5 A E RS COM to COM 6 6 LCD R/W D to D 7 8 R/W DB to DB 7 to Figure 9 8-Bit MPU Interface HD685 HD6672 8 COM to A to A 7 DB to DB7 COM 6 6 C C C 2 E RS R/W to LCD Figure 2 HD685 Interface HD63 HD6672 P 34 P 35 P 36 RS R/W E COM to COM 6 6 P to P 7 8 DB to DB 7 to LCD Figure 2 HD63 Interface 32
HD6672 Interfacing the HD6672 Interface to MPUs Interfacing to an 8-bit MPU through a PIA See figure 23 for an example of using a PIA or I/O port (for a single-chip microcomputer) as an interface device. The input and output of the device is TTL compatible. In this example, PB to PB 7 are connected to the data bus DB to DB 7, and PA to PA 2 are connected to E, R/W, and RS, respectively. Pay careful attention to the timing relationship between E and the other signals when reading or writing data using a PIA for the interface. RS R/W E Internal operation DB 7 Functioning Data Busy Busy Not busy Data Instruction write Busy flag check Busy flag check Busy flag check Instruction write Figure 22 Example of Busy Flag Check Timing Sequence HD68B (8-bit CPU) HD68B2 (PIA) HD6672 A 5 A 4 A 3 A A R/W VMA ø2 DB to DB 7 8 CS2 CS PA 2 CS PA RS RS PA R/W E PB to PB 7 D to D 7 8 RS R/W E DB to DB 7 COM to COM 6 to 6 LCD Figure 23 Example of Interface to HD68B Using PIA (HD68B2) 33
HD6672 Interfacing to a 4-bit MPU The HD6672 can be connected to the I/O port of a 4-bit MPU. If the I/O port has enough bits, 8-bit data can be transferred. Otherwise, one data transfer must be made in two operations for 4-bit data. In this case, the timing sequence becomes somewhat complex. (See figure 24.) See figure 25 for an interface example to the HMCS43C. Note that two cycles are needed for the busy flag check as well as for the data transfer. The 4-bit operation is selected by the program. RS R/W E Internal operation Not DB 7 IR IR 3 Functioning7 Busy AC 3 busy AC 3 D 7 D 3 Instruction Busy flag Busy flag Instruction write check check write Note: IR 7, IR 3 are the 7th and 3rd bits of the instruction. AC 3 is the 3rd bit of the address counter. Figure 24 Example of 4-Bit Data Transfer Timing Sequence HMCS43C (Hitachi 4-bit single-chip microcontroller) HD6672 D 5 RS COM to 6 D 4 R/W COM 6 D 3 E LCD 4 to R to R 3 DB 4to DB7 HMCS43C Figure 25 Example of Interface to 34
HD6672 Interface to Liquid Crystal Display Character Font and Number of Lines: The HD6672 can perform two types of displays, 5 7 dot and 5 dot character fonts, each with a cursor. Up to two lines are displayed for 5 7 dots and one line for 5 dots. Therefore, a total of three types of common signals are available (table ). The number of lines and font types can be selected by the program. (See table 7, Instructions.) Connection to HD6672 and Liquid Crystal Display: See figure 26 for the connection examples. Table Common Signals Number of Lines Character Font Number of Common Signals Duty Factor 5 7 dots + cursor 8 /8 5 dots + cursor / 2 5 7 dots + cursor 6 /6 HD6672 COM COM 8 Example of a 5 7 dot, 2-character -line display (/4 bias, /8 duty cycle) HD6672 COM COM Example of a 5 dot, 2-character -line display (/4 bias, /8 duty cycle) Figure 26 Liquid Crystal Display and HD6672 Connections 35
HD6672 Since five segment signal lines can display one digit, one HD6672 can display up to 2 digits for a -line display and 4 digits for a 2-line display. The examples in figure 26 have unused common signal pins, which always output non-selection waveforms. When the liquid crystal display panel has unused extra scanning lines, connect the extra scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the floating state (figure 28). HD6672 COM COM 8 COM 9 COM 6 Example of a 5 7 dot, 2-character 2-line display (/5 bias, /6 duty cycle) Figure 27 Liquid Crystal Display and HD6672 Connections (cont) HD6672 COM COM 8 COM 9 5 7 dot, 2-character -line display (/4 bias, /8 duty cycle) Figure 28 Using COM 9 to Avoid Crosstalk on Unneeded Scanning Line 36
HD6672 Connection of Changed Matrix Layout: In the preceding examples, the number of lines correspond to the scanning lines. However, the following display examples (figure 29) are made possible by altering the matrix layout of the liquid crystal display panel. In either case, the only change is the layout. The display characteristics and the number of liquid crystal display characters depend on the number of common signals or on duty factor. Note that the display data RAM (DD RAM) addresses for characters 2 lines and for 4 characters line are the same as in figure 27. HD6672 COM COM 8 COM 9 COM 6 5 7 dot, 4-character -line display (/5 bias, /6 duty cycle) 5 COM COM 8 5 5 7 dot, -character 2-line display (/4 bias, /8 duty cycle) Figure 29 Changed Matrix Layout Displays 37
HD6672 Power Supply for Liquid Crystal Display Drive Various voltage levels must be applied to pins V to V 5 of the HD6672 to obtain the liquid crystal display drive waveforms. The voltages must be changed according to the duty factor (table ). V LCD is the peak value for the liquid crystal display drive waveforms, and resistance dividing provides voltages V to V 5 (figure 3). Table Duty Factor and Power Supply for Liquid Crystal Display Drive Duty Factor /8, / /6 Bias Power Supply /4 /5 V V CC /4 V LCD V CC /5 V LCD V 2 V CC /2 V LCD V CC 2/5 V LCD V 3 V CC /2 V LCD V CC 3/5 V LCD V 4 V CC 3/4 V LCD V CC 4/5 V LCD V 5 V CC V LCD V CC V LCD V (+5 V) CC V (+5 V) CC V CC V V 2 V 3 V 4 V 5 R R R R V LCD V CC V V 2 V 3 V 4 V 5 R R R R R V LCD VR VR /4 bias (/8, / duty cycle) 5 V /5 bias (/6, duty cycle) 5 V Figure 3 Drive Voltage Supply Example 38
HD6672 Relationship between Oscillation Frequency and Liquid Crystal Display Frame Frequency The liquid crystal display frame frequencies of figure 3 apply only when the oscillation frequency is 32 khz (one clock pulse of 3.25 µs). /8 duty cycle COM V CC V V 2 (V 3) V 4 V5 4 clocks 2 3 4 8 2 frame frame = 3.25 µs 4 8 = µs = ms Frame frequency = = Hz ms / duty cycle COM V CC V V 2 (V 3) V 4 V5 4 clocks 2 3 4 2 frame frame = 3.25 µs 4 = 375 µs = 3.75 ms Frame frequency = = 72.7 Hz 3.75 ms /6 duty cycle COM V CC V V 2 V 3 V 4 V5 2 clocks 2 3 4 6 2 frame frame = 3.25 µs 2 6 = µs = ms Frame frequency = = Hz ms Figure 3 Frame Frequency 39
HD6672 Connection with HD44 Driver By externally connecting an HD44 liquid crystal display driver to the HD6672, the number of display digits can be increased. The HD44 is used as a segment signal driver when connected to the HD6672. The HD44 can be directly connected to the HD6672 since it supplies CL, CL 2, M, and D signals and power for the liquid crystal display drive (figure 32). Up to eight HD44 units can be connected for a -line display (duty factor /8 or /) and up to three units for a 2-line display (duty factor /6). The RAM size limits the HD6672 to a maximum of 8 character display digits. The connection method for both -line and 2-line displays or for 5 7 and 5 dot character fonts can remain the same (figure 32). Caution: The connection of voltage supply pins V through V 6 for the liquid crystal display drive is somewhat complicated. The EXT pin must be fixed low if the HD44 is to be connected to the HD6672. HD6672 COM COM 6 (COM COM 8) 6 (8) Dot-matrix liquid crystal display panel 4 4 4 D EXT Y DL Y 4 Y DR 2 DL Y 4 Y Y DR 2 DL 4 FCS SHL SHL 2 DL 2 FCS DL 2 FCS HD44 SHL HD44 SHL HD44 DR SHL 2 DR SHL 2 DR 2 DL 2 DR V 6 V V V V V V V CL CL 5 4 3 2 EE GND CC M 2 V 6 V V V V V V V CL CL 5 4 3 2 EE GND CC M 2 V 6 V V V V V V V CL CL 5 4 3 2 EE GND CC M 2 CL CL 2 M V CC GND V 2 V 3 V 5 Figure 32 Example of Connecting HD44Hs to HD6672 3