Push Button On/Off Controller FEATRES Adjustable Push Button On/Off Timers Low Supply Current: 6µA Wide Operating Voltage Range: 2.7V to 26V Output (LTC295-1) Allows DC/DC Converter Control E N Output (LTC295-2) Allows Circuit Breaker Control Simple Interface Allows Graceful µp Shut Down High Input Voltage P B Pin with Internal Pull p Resistor ±1kV ESD HBM on P B Input Accurate.6V Threshold on K I L L Comparator Input 8-Pin 3mm 2mm DFN and ThinSOT TM Packages APPLICATIO S Portable Instrumentation Meters Blade Servers Portable Customer Service PDA Desktop and Notebook Computers DESCRIPTIO The LTC 295 is a micropower, wide input voltage range, push button ON/OFF controller. The part contains a push button input with independently programmable ON and OFF debounce times that control the toggling of an open drain enable output. The part also contains a simple microprocessor interface to allow for proper system housekeeping prior to power down. nder system fault conditions, an internal K I L L timer ensures proper power down. The LTC295 operates over a wide 2.7V to 26V input voltage range to accommodate a wide variety of input power supplies. Very low quiescent current (6µA typical) makes the LTC295 ideally suited for battery powered applications. Two versions of the part are available to accommodate either positive or negative enable polarities. The parts are available in either 8-lead 3mm 2mm DFN or ThinSOT packages., LT, LTC and LTM are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIO 3V 26V V OT Turn On Debounce DC/DC BCK SHDN R1 1k 2V/DIV GND LTC295-1 ONT OFFT µp/µc C ONT *.33µF C OFFT *.33µF *OPTIONAL 295 TA1 1ms/DIV 295 TA1b 1
ABSOLTE AXI RATI GS W W W (Note 1) Supply Voltage ( )....3V to 33V Input Voltages P B... 6V to 33V ONT....3V to 2.7V OFFT....3V to 2.7V K I L L....3V to 7V Output Voltages I N T....3V to 1V / E N....3V to 1V Operating Temperature Range LTC295-C1... C to 7 C LTC295-C2... C to 7 C LTC295-I1... 4 C to 85 C LTC295-I2... 4 C to 85 C Storage Temperature Range DFN Package... 65 C to 125 C TSOT-23... 65 C to 15 C Lead Temperature (Soldering, 1 sec)... 3 C PACKAGE/ORDER I FOR ATIO W ORDER PART NMBER GND ONT LTC295CDDB-1 LTC295CDDB-2 LTC295IDDB-1 LTC295IDDB-2 TOP VIEW DDB8 PACKAGE 8-LEAD (3mm 2mm) PLASTIC DFN T JMAX = 125 C, θ JA = 165 C/W EXPOSED PAD (PIN 9) NCONNECTED DDB PART* MARKING LBKP LBNG LBKP LBNG Consult factory for parts specified with wider operating temperature ranges. * The temperature grade is identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS 1 2 3 4 9 8 7 6 5 / OFFT 1 2 ONT 3 GND 4 ORDER PART NMBER LTC295CTS8-1 LTC295CTS8-2 LTC295ITS8-1 LTC295ITS8-2 Order Options Tape and Reel: Add #TR Lead Free: Add #F Lead Free Tape and Reel: Add #TRF Lead Free Part Marking: http://www.linear.com/leadfree/ TOP VIEW 8 7 OFFT 6 / 5 TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 T JMAX = 125 C, θ JA = 14 C/W S8 PART* MARKING LTBKN LTBNF LTBKN LTBNF The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25C. = 2.7V to 26.4V, unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Supply Voltage Range Steady State Operation 2.7 26.4 V I IN Supply Current System Power On, = 2.7V to 24V 6 12 µa V VL ndervoltage Lockout Falling 2.2 2.3 2.4 V V VL(HYST) ndervoltage Lockout Hysteresis 5 3 6 mv 2
ELECTRICAL CHARACTERISTICS LTC295-1/LTC295-2 The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25C. = 2.7V to 26.4V, unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Push Button Pin ( P B) V P B(MIN, MAX) P B Voltage Range Single-Ended 1 26.4 V I P B P B Input Current 2.5V < V P B < 26.4V V P B = 1V V P B =.6V V P B(VTH) P B Input Threshold P B Falling.6.8 1 V V P B(VOC) P B Open Circuit Voltage I P B = 1µA 1 1.6 2 V Debounce Timing Pins (ONT, OFFT) I ONT, OFFT(P) ONT/OFFT Pull p Current V ONT, OFFT = V 2.4 3 3.6 µa I ONT, OFFT(PD) ONT/OFFT Pull Down Current V ONT, OFFT = 1.3V 2.4 3 3.6 µa t DB, On Internal Turn On Debounce Time ONT Pin Float, P B Falling Enable Asserted 26 32 41 ms t ONT Additional Adjustable Turn On Time C ONT = 15pF 9 11.5 13.5 ms t DB, Off Internal Turn Off Debounce Time OFFT Pin Float, P B Falling I N T Falling 26 32 41 ms t OFFT Additional Adjustable Turn Off Time C OFFT = 15pF 9 11.5 13.5 ms µp Handshake Pins ( I N T, K I L L) I I N T(LKG) I N T Leakage Current V I N T = 3V ±1 µa V I N T(VOL) I N T Output Voltage Low I I N T = 3mA.11.4 V V K I L L(TH) K I L L Input Threshold Voltage K I L L Falling.57.6.63 V V K I L L(HYST) K I L L Input Threshold Hysteresis 1 3 5 mv I K I L L(LKG) K I L L Leakage Current V K I L L =.6V ±.1 µa t K I L L(PW) K I L L Minimum Pulse Width 3 µs t K I L L(PD) K I L L Propagation Delay K I L L Falling Enable Released 3 µs t K I L L, On Blank K I L L Turn On Blanking (Note 3) K I L L = Low, Enable Asserted Enable Released 4 512 65 ms t K I L L, Off Delay K I L L Turn Off Delay (Note 4) K I L L = High, I N T Asserted Enable Released 8 124 13 ms t / E N, Lock Out / E N Lock Out Time (Note 5) Enable Released Enable Asserted 2 256 325 ms I / E N(LKG) / E N Leakage Current V / E N = 1V, Sink Current Off ±.1 µa V / E N(VOL) / E N Voltage Output Low I / E N = 3mA.11.4 V 1 3 6 9 ±1 12 15 µa µa µa Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. Note 3: The K I L L turn on blanking timer period is the waiting period immediately after the enable output is asserted. This blanking time allows sufficient time for the DC/DC converter and the µp to perform power up tasks. The K I L L and P B inputs are ignored during this period. If K I L L remains low at the end of this time period, the enable output is released, thus turning off system power. This time delay does not include t DB, ON or t ONT. Note 4: The K I L L turn off delay is the maximum delay from the initiation of a shutdown sequence ( I N T falling), to the release of the enable output. If the K I L L input switches low at any time during this period, enable is released, thus turning off system power. This time is internally fixed at 124ms. This time delay does not include t DB, OFF or t OFFT. Note 5: The enable lock out time is designed to allow an application to properly power down such that the next power up sequence starts from a consistent powered down confi guration. P B is ignored during this lock out time. This time delay does not include t DB, ON or t ONT. 3
TYPICAL PERFOR A CE CHARACTERISTICS W Supply Current vs Temperature 1 = 26.4V 8 Supply Current vs Supply Voltage 1 8 I VIN (µa) 6 4 = 3.3V = 2.7V I VIN (µa) 6 4 2 2 5 25 25 5 TEMPERATRE ( C) 75 1 5 1 15 2 25 3 (V) 295 G1 295 G2 Internal Default Turn On Debounce Time (t DB, ON ) vs 5 1 Turn On Debounce Time (t DB, ON + t ONT ) vs ONT External Capacitor = 3.3V 3.4 ONT Pull-Down Current vs Temperature t DB, ON (ms) 4 3 2 1 t DB, ON + t ONT (ms) 1 1 ONT PLL-DOWN CRRT (µa) 3.2 3. 2.8 = 2.7V = 26.4V 5 1 15 2 25 3 (V) 1 1 1 1 ONT EXTERNAL CAPACITOR (nf) 1 2.6 5 25 25 5 75 1 TEMPERATRE ( C) 295 G3 295 G4 295 G5 t DB, OFF (ms) Internal Default Turn Off Debounce Time (t DB, OFF ) vs 5 4 3 2 1 t DB, OFF + t OFFT (ms) 1 1 1 Turn Off Debounce Time (t DB, OFF + t OFFT ) vs OFFT External Capacitor = 3.3V OFFT PLL-DOWN CRRT (µa) 3.4 3.2 3. 2.8 OFFT Pull-Down Current vs Temperature = 2.7V = 26.4V 5 1 15 2 (V) 25 3 1 1 1 1 OFFT EXTERNAL CAPACITOR (nf) 1 2.6 5 25 25 5 75 1 TEMPERATRE ( C) 295 G6 295 G7 295 G8 4
TYPICAL PERFOR A CE CHARACTERISTICS W 25 2 P B Current vs P B Voltage = 3.3V 3 25 P B Voltage vs External P B Resistance to Ground = 3.3V CRRT (µa) 15 1 VOLTAGE (mv) 2 15 1 T A = 1 C T A = 45 C 5 5 1 5 5 1 15 2 25 3 VOLTAGE (V) 5 1 15 2 EXTERNAL RESISTANCE TO GROND (kω) 295 G9 295 G1 / VOLTAGE (mv) 5 4 3 2 1 / E N V OL vs Current Load = 3.3V (V) 1..8.6.4.2 (LTC295-1) Voltage vs 1k PLL-P FROM TO (V) 4 3 2 1 E N (LTC295-2) Voltage vs 1k PLL-P FROM TO 2 4 6 8 1 / CRRT LOAD (ma) 1 2 3 (V) 4 1 2 3 4 (V) 295 G11 295 G12 295 G13 5
PI F CTIO S (TSOT-23/DFN) (Pin 1/Pin 4): Power Supply Input: 2.7V to 26.4V. P B (Pin 2/Pin 3): Push Button Input. Connecting P B to ground through a momentary switch provides on/off control via the / E N pin. An internal 1k pull-up resistor connects to an internal 1.9V bias voltage. The rugged P B input can be pulled up to 26.4V externally without consuming extra current. ONT (Pin 3/Pin 2): Additional Adjustable Turn On Time Input. Placing an external capacitor to ground determines the additional time (beyond the internal default 32ms) the P B pin must be held low before the enable output is asserted. Floating this pin results in a default turn on debounce time of 32ms. GND (Pin 4/Pin 1): Device Ground. I N T (Pin 5/Pin 8): Open Drain Interrupt Output. After a push button turn-off event is detected, the LTC295 interrupts the system (µp) by bringing the I N T pin low. Once the system finishes its power down and housekeeping tasks, it sets K I L L low, which in turn releases the enable output. If at the end of the power down timer (124ms) K I L L is still high, the enable output is released immediately. I N T may optionally be tied to K I L L to release the enable output immediately after the turn-off event has been detected ( I N T = low). (LTC295-1, Pin 6/Pin 7): Open Drain Enable Output. This pin is intended to enable system power. is asserted high after a valid P B turn on event. is released low if: a) K I L L is not driven high (by μp) within 512ms of the initial valid P B power turn-on event, b) K I L L is driven low during normal operation, c) a second valid P B event (power turn-off) is detected. The operating range for this pin is V to 1V. E N (LTC295-2, Pin 6/Pin 7): Open Drain Enable Output. This pin is intended to enable system power. E N is asserted low after a valid P B turn-on event. E N releases high if: a) K I L L is not driven high (by μp) within 512ms of the initial valid P B power turn-on event, b) K I L L is driven low during normal operation, c) a second valid P B event (power turn-off) is detected. The operating range of this pin is V to 1V. OFFT (Pin 7/Pin 6): Additional Adjustable Turn Off Time Input. A capacitor to ground determines the additional time (beyond the internal default 32ms) that the P B pin must be held low before initiating a power down sequence ( I N T falling). Floating this pin results in a default turn off time of 32ms. K I L L (Pin 8/Pin 5): K I L L Input. Forcing K I L L low releases the enable output. During system turn on, this pin is blanked by a 512ms internal timer to allow the system to pull K I L L high. This pin has an accurate.6v threshold and can be used as a voltage monitor input. Exposed Pad (Pin 9): Exposed Pad may be left open or connected to device ground. 6
BLOCK DIAGRA W / 2.7V TO 26.4V REGLATOR 2.4V 2.4V 1k OSCILLATOR LOGIC DEBONCE.6V.8V OSCILLATOR GND ONT OFFT 295 BD TI I G DIAGRA S W W t (PW) t (PD) / 295 TD1 7
TI I G DIAGRA S W W & IGNORED t DB, ON t ONT t, ON BLANK 16 CYCLES (LTC295-1) (LTC295-2) 295 TD2 Power On Timing IGNORED t DB, OFF t OFFT OFFT 16 CYCLES t, OFF DELAY (LTC295-1) (LTC295-2) 295 TD3 Power Off Timing, K I L L >.6V 8
APPLICATIO S I FOR Description ATIO W The LTC295 is a low power (6µA), wide input voltage range (2.7V to 26.4V), push button on/off controller that can interface to a µp and a power supply. The turn-on and turn-off debounce times are extendable using optional external capacitors. A simple interface ( I N T output, K I L L input) allows a system to power on and power off in a controlled manner. Turn On When power is first applied to the LTC295, the part initializes the output pins. Any DC/DC converters connected to the / E N pin will therefore be held off. To assert the enable output, P B must be held low for a minimum of 32ms (t DB, ON ). The LTC295 provides additional turn on debounce time via an optional capacitor connected to the ONT pin (t ONT ). The following equation describes the additional time that P B must be held low before asserting the enable output. C ONT is the ONT external capacitor: C ONT = 1.56E-4 [μf/ms] (t ONT 1ms) Once the enable output is asserted, any DC/DC converters connected to this pin are turned on. The K I L L input from the µp is ignored during a succeeding 512ms blanking time (t K I L L, ON BLANK ). This blanking time represents the maximum time required to power up the DC/DC converter and the µp. If K I L L is not brought high during this 512ms time window, the enable output is released. The assumption is that 512ms is sufficient time for the system to power up. Turn Off To initiate a power off sequence, P B must be held low for a minimum of 32ms (t DB, OFF ). Additional turn off debounce time may be added via an optional capacitor connected to the OFFT pin (t OFFT ). The following equation describes the additional time that P B must be held low to initiate a power off sequence. C OFFT is the OFFT external capacitor: C OFFT = 1.56E-4 [μf/ms] (t OFFT 1ms) Once P B has been validly pressed, I N T is switched low. This alerts the µp to perform its power down and housekeeping tasks. The power down time given to the µp is 124ms. Note that the K I L L input can be pulled low (thereby releasing the enable output) at any time after t K I L L, ON BLANK period. Simplifi ed Power On/Off Sequence Figure 1 shows a simplified LTC295-1 power on and power off sequence. A high to low transition on P B (t 1 ) initiates the power on sequence. This diagram does not show any bounce on P B. In order to assert the enable output, the P B pin must stay low continuously ( P B high resets timers) for a time controlled by the default 32ms and the external ONT capacitor (t 2 t 1 ). Once goes high (t 2 ), an internal 512ms blanking timer is started. This blanking timer is designed to give suffi cient time for the DC/DC converter to reach its fi nal voltage, and to allow the µp enough time to perform power on tasks. The K I L L pin must be pulled high within 512ms of the pin going high. Failure to do so results in the pin going low 512ms after it went high. ( = low, see Figure 2). Note that the LTC295 does not sample K I L L and P B until after the 512ms internal timer has expired. The reason P B is ignored is to ensure that the system is not forced off while powering on. Once the 512ms timer expires (t 4 ), the release of the P B pin is then debounced with an internal 32ms timer. The system has now properly powered on and the LTC295 monitors P B and K I L L (for a turnoff command) while consuming only 6µA of supply current. A high to low transition on P B (t 5 ) initiates the power off sequence. P B must stay low continuously ( P B high resets debounce timer) for a period controlled by the default 32ms and the external OFFT capacitor (t 6 t 5 ). At the completion of the OFFT timing (t 6 ), an interrupt ( I N T) is set, signifying that will be switched low in 124ms. Once a system has fi nished performing its power down operations, it can set K I L L low (t 7 ) and thus immediately set low), terminating the internal 124ms timer. The release of the P B pin is then debounced with an internal 32ms timer. The system is now in its reset state: where the LTC295 is in low power mode (6µA). P B is monitored for a high to low transition. 9
APPLICATIO S I FOR ATIO W t 1 t 2 t 3 t 4 t 5 t 6 t 7 & IGNORED IGNORED t DB, ON t ONT t, ON BLANK t DB, OFF < t, OFF DELAY ONT t OFFT OFFT <t, OFF DELAY 295 F1 Figure 1. Simplifi ed Power On/Off Sequence for LTC295-1 t ABORT t DB, ON + t ONT 512ms ERNAL TIMER POWER ON TIMING µp FAILED TO SET HIGH POWER TRNED OFF 295 F2 Figure 2. Aborted Power On Sequence for LTC295-1 1
APPLICATIO S I FOR Aborted Power On Sequence ATIO W The power on sequence is aborted when the K I L L remains low after the end of the 512ms blanking time. Figure 2 is a simplified version of an aborted power on sequence. At time t ABORT, since K I L L is still low, pulls low (thus turning off the DC/DC converter). µp Turns Off Power During Normal Operation Once the system has powered on and is operating normally, the µp can turn off power by setting K I L L low, as shown in Figure 3. At time t K I L L, K I L L is set low by the µp. This immediately pulls low, thus turning off the DC/DC converter. DC/DC Turn Off Blanking When the DC/DC converter is turned off, it can take a significant amount of time for its output to decay to ground. It is desirable to wait until the output of the DC/DC converter is near ground before allowing the user (via P B) to restart the converter. This condition guarantees that the µp has always powered down completely before it is restarted. Figure 4 shows the µp turning power off. After a low on K I L L releases enable, the internal 256ms timer ignores the P B pin. This is shown as t / E N, LOCKOT in Figure 4. LTC295-1, LTC295-2 VERSIONS The LTC295-1 (high true ) and LTC295-2 (low true E N) differ only by the polarity of the / E N pin. Both versions allow the user to extend the amount of time that the P B must be held low in order to begin a valid power on/off sequence. An external capacitor placed on the ONT pin adds additional time to the turn on time. An external capacitor placed on the OFFT pin adds additional time to the turn off time. If no capacitor is placed on the ONT (OFFT) pin, then the turn on (off) duration is given by an internally fi xed 32ms timer. The LTC295 fi xes the K I L L turn off delay time (t K I L L, OFF DELAY) at 124ms. This means that the / E N pin will be switched low/high a maximum of 124ms after initiating a valid turn off sequence. Note that in a typical application, a µp or µc would set K I L L low prior to the 124ms timer period (t 7 in Figure 1). The following equations describe the turn on and turn off times. C ONT and C OFFT are the external programming capacitors: t BD,ON + t ONT = 32ms + 1ms + (6.7x1 6 ) C ONT t BD,OFF + t OFFT = 32ms + 1ms + (6.7x1 6 ) C OFFT t /, LOCKOT POWER ON IGNORED t BLANKING DC/DC TRNS OFF 256ms DC/DC TRNS OFF µp SETS LOW µp SETS LOW XXX DON T CARE XXX DON T CARE 295 F3 295 F4 Figure 3. µp Turns Off Power (LTC295-1) Figure 4. DC/DC Turn Off Blanking (LTC295-1) 11
APPLICATIO S I FOR ATIO W High Voltage Pins The and P B pins can operate at voltages up to 26.4V. P B can, additionally, operate below ground ( 6V) without latching up the device. P B has an ESD HBM rating of ±1kV. If the push button switch connected to P B exhibits high leakage current, then an external pull-up resistor to is recommended. Furthermore, if the push button switch is physically located far from the LTC295 P B pin, parasitic capacitances may couple onto the high impedance P B input. Additionally, parasitic series inductance may cause unpredictable ringing at the P B pin. Placing a 5k resistor from the P B pin to the push button switch would mitigate parasitic inductance problems. Placing a.1µf capacitor on the P B pin would lessen the impact of parasitic capacitive coupling. TYPICAL APPLICATIO S Voltage Monitoring with K I L L Input The K I L L pin can be used as a voltage monitor. Figure 5 shows an application where the K I L L pin has a dual function. It is driven by a low leakage open drain output of the µp. It is also connected to a resistor divider that monitors battery voltage ( ). When the battery voltage falls below the set value, the voltage at the K I L L pin falls below.6v and the pin is quickly pulled low. Note that the resistor values should be as large as possible, but small enough to keep leakage currents from tripping the.6v K I L L comparator. The DC/DC converter shown has an internal pull-up current on its S H D N pin. A pull-up resistor on is thus not needed. Operation Without µp Figure 6 shows how to connect the K I L L pin when there is no circuitry available to drive it. The minimum pulse width detected is 3µs. If there are glitches on the resistor pull-up voltage that are wider than 3µs and transition below.6v, then an appropriate bypass capacitor should be connected to the K I L L pin. 9V V OT 3.3V 9V V OT 3.3V LT1767-3.3 SHDN LT1767-3.3 SHDN C4.1µF 5.4V THRESHOLD LTC295-1 GND ONT OFFT R3 86k 1% R2 1k 1% R1 1k µp (OP DRAIN) C4.1µF LTC295-1 GND ONT OFFT + R1 1k C3*.1µF 295 F5 C ONT *.33µF C OFFT *.33µF *OPTIONAL C ONT *.33µF C OFFT *.33µF *OPTIONAL 295 F6 Figure 5. Input Voltage Monitoring with K I L L Input Figure 6. No µp Application 12
TYPICAL APPLICATIO S Power Path Switching The E N open drain output of the LTC295-2 is designed to switch on/off an external power PFET. This allows a user to connect/disconnect a power supply (or battery) to its load by toggling the P B pin. Figure 7 shows the LTC295-2 controlling a two cell Li-Ion battery application. The I N T and K I L L pins are connected to the output of the PFET through a resistor divider. The K I L L pin serves as a voltage monitor. When V OT drops below 6V, the E N pin is open circuited 3µs later. LTC295-1/LTC295-2 P B Pin in a Noisy Environment The rugged P B pin is designed to operate in noisy environments. Transients below ground (> 6V) and above (<3V) will not damage the rugged P B pin. Additionally, the P B pin can withstand ESD HBM strikes up to ±1kV. In order to keep external noise from coupling inside the LTC295, place an R-C network close to the P B pin. A 5k resistor and a.1µf capacitor should suffi ce for most noisy applications (see Figure 8). R5 1K M1 V OT V OT,TRIP PO = 6V 4.2V SINGLE CELL Li-Ion BATTERY 4.2V SINGLE CELL Li-Ion BATTERY + C4.1µF CERAMIC + LTC295-2 GND ONT OFFT C ONT *.33µF OP DRAIN OTPT V TH =.6PT C OFFT *.33µF *OPTIONAL R4 1k 1% R1 99k 1% OPTIONAL GLITCH FILTER CAPACITOR C3*.1µF 295 F7 Figure 7. Power Path Control with 6V nder Voltage Detect PARASITICS TRACE CAPACITANCE NOISE R6 5k LTC295-1 TRACE INDCTANCE C5.1µF GND ONT OFFT DETAILS OMITTED FOR CLARITY 295 F8 Figure 8. Noisy P B Trace 13
TYPICAL APPLICATIO S External Pull-p Resistor on P B An internal pull-up resistor on the P B pin makes an external pull-up resistor unnecessary. Leakage current on the P B board trace, however, will affect the open circuit voltage on the P B pin. If the leakage is too large (>2µA), the P B voltage may fall close to the threshold window. To mitigate the effect of the board leakage, a 1k resistor to is recommended (see Figure 9). Reverse Battery Protection To protect the LTC295 from a reverse battery connection, place a 1k resistor in series with the pin (see Figure 1). R7 1k EXTERNAL BOARD LEAKAGE CRRT >2µA IF EXTERNAL PARASITIC BOARD LEAKAGE >2µA, SE EXTERNAL PLL-P RESISTOR LTC295-1/ LTC295-2 2.4V 1k GND PINS OMITTED FOR CLARITY 295 F9 Figure 9. External Pull-p Resistor on P B Pin 14
PACKAGE DESCRIPTIO DDB Package 8-Lead Plastic DFN (3mm 2mm) (Reference LTC DWG # 5-8-172) 2.55 ±.5 1.15 ±.5.61 ±.5 (2 SIDES).25 ±.5.5 BSC 2.2 ±.5 (2 SIDES).7 ±.5 PACKAGE OTLINE RECOMMDED SOLDER PAD PITCH AND DIMSIONS PIN 1 BAR TOP MARK (SEE NOTE 6).2 REF 3. ±.1 (2 SIDES) 2. ±.1 (2 SIDES).75 ±.5.5 R =.5 TYP.56 ±.5 (2 SIDES) R =.115 TYP 5.4 ±.1 4 1.25 ±.5.5 BSC 2.15 ±.5 (2 SIDES) BOTTOM VIEW EXPOSED PAD 8 PIN 1 R =.2 OR.25 45 CHAMFER (DDB8) DFN 95 REV B NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OTLINE M-229 2. DRAWING NOT TO SCALE 3. ALL DIMSIONS ARE IN MILLIMETERS 4. DIMSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLDE MOLD FLASH. MOLD FLASH, IF PREST, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE S8 Package 8-Lead Plastic Small Outline (Reference LTC DWG # 5-8-1637).52 MAX.65 REF 2.9 BSC (NOTE 4) 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.8 BSC 1.5 1.75 (NOTE 4) PIN ONE ID RECOMMDED SOLDER PAD LAYOT PER IPC CALCLATOR.65 BSC.22.36 8 PLCS (NOTE 3).8.9.2 BSC DATM A 1. MAX.1.1.3.5 REF.9.2 1.95 BSC (NOTE 3) TS8 TSOT-23 82 NOTE: 1. DIMSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMSIONS ARE INCLSIVE OF PLATING 4. DIMSIONS ARE EXCLSIVE OF MOLD FLASH AND METAL BRR 5. MOLD FLASH SHALL NOT EXCEED.254mm 6. JEDEC PACKAGE REFERCE IS MO-193 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15
TYPICAL APPLICATIO 9V BATTERY + R8 1k R5 91k V OT LT1761-1.8 SHDN 1.8V C4.1µF LTC295-1 R1 1k µp GND ONT OFFT C ONT *.33µF C OFFT *.33µF *OPTIONAL 295 F1 Figure 1. Reverse Battery Protection RELATED PARTS PART NMBER DESCRIPTION COMMTS LTC29 Programmable Quad Supply Monitor Adjustable R E S E T, 1-Lead MSOP and 3mm x 3mm DFN Packages LTC294/295 Pin-Programmable Dual Supply Monitors Adjustable R E S E T and Tolerance, 8-Lead SOT-23 and 3mm x 2mm DFN Packages LTC4411 2.6A Low Loss Ideal Diode in ThinSOT No External MOSFET, Automatic Switching Between DC Sources LTC4412HV Power Path Controller in ThinSOT Effi cient Diode-ORing, Automatic Switching Between DC Sources, 3V to 36V LTC455 SB Power Controller and Li-Ion Charger Automatic Switchover, Charges 1-Cell Li-Ion Batteries 16 LT/LWI 76 REV A PRED IN SA Linear Technology Corporation 163 McCarthy Blvd., Milpitas, CA 9535-7417 (48) 432-19 FAX: (48) 434-57 www.linear.com LINEAR TECHNOLOGY CORPORATION 25