Members of the Texas Itruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True s Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed and Pin Configuration Minimizes High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) -m Process 500-mA Typical Latch-Up Immunity at 5 C Package Optio Include Shrink Small-Outline (DL) 300-mil Packages Using 5-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 5-mil Center-to-Center Pin Spacings description The SN54ACT6373 and 74ACT6373 are 6-bit D-type traparent latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit latches or one 6-bit latch. The outputs of the latches follow the data (D) inputs if enable C is taken high. When C is taken low, the outputs are latched at the levels set up at the D inputs. SN54ACT6373, 74ACT6373 6-BIT D-TYPE TRANSPARENT LATCHES SCASC MARCH 990 REVISED SEPTEMBER 996 SN54ACT6373... WD PACKAGE 74ACT6373... DL PACKAGE (TOP VIEW) A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operatio of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74ACT6373 is packaged in TI s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ACT6373 is characterized for operation over the full military temperature range of 55 C to 5 C. The 74ACT6373 is characterized for operation from 40 C to 85 C. OE 3 4 5 6 7 8 3 4 5 6 7 8 OE 3 4 5 6 7 8 9 0 3 4 5 6 7 8 9 0 3 4 48 47 46 45 44 43 4 4 40 39 38 37 36 35 34 33 3 3 30 9 8 7 6 5 C D D D3 D4 D5 D6 D7 D8 D D D3 D4 D5 D6 D7 D8 C Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Itruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 996, Texas Itruments Incorporated POST OFFICE BOX 655303 DALLAS, TEXAS 7565
SN54ACT6373, 74ACT6373 6-BIT D-TYPE TRANSPARENT LATCHES SCASC MARCH 990 REVISED SEPTEMBER 996 logic symbol FUNCTION TABLE INPUTS OUTPUT OE C D L H H H L H L L L L X 0 H X X Z OE C OE C 48 4 5 EN C EN C4 D D D3 D4 D5 D6 D7 D8 D D D3 D4 D5 D6 D7 D8 47 46 44 43 4 40 38 37 36 35 33 3 30 9 7 6 D 3D 4 3 5 6 8 9 3 4 6 7 9 0 3 3 4 5 6 7 8 3 4 5 6 7 8 This symbol is in accordance with ANSI/IEEE Std 9-984 and IEC Publication 67-. POST OFFICE BOX 655303 DALLAS, TEXAS 7565
SN54ACT6373, 74ACT6373 6-BIT D-TYPE TRANSPARENT LATCHES SCASC MARCH 990 REVISED SEPTEMBER 996 logic diagram (positive logic) OE OE 4 C 48 C 5 D 47 C D D 36 C D 3 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range,.......................................................... 0.5 V to 7 V Input voltage range, V I (see Note )............................................ 0.5 V to + 0.5 V voltage range, V O (see Note )......................................... 0.5 V to + 0.5 V Input clamp current, I IK (V I < 0 or V I > )................................................. ±0 ma clamp current, I OK (V O < 0 or V O > )............................................ ±50 ma Continuous output current, I O (V O = 0 to ).............................................. ±50 ma Continuous current through or.................................................. ±400 ma Maximum power dissipation at T A = 55 C (in still air) (see Note ): DL package.................... W Storage temperature range, T stg.................................................... 65 C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.. The maximum package power dissipation is calculated using a junction temperature of 50 C and a board trace length of 750 mils. recommended operating conditio (see Note 3) SN54ACT6373 74ACT6373 MIN MAX MIN MAX VCC Supply voltage (see Note 4) 4.5 5.5 4.5 5.5 V VIH High-level input voltage V VIL Low-level input voltage 0.8 0.8 V VI Input voltage CC CC V VO voltage CC CC V IOH High-level output current 4 4 ma IOL Low-level output current 4 4 ma t/v Input traition rise or fall rate 0 0 0 0 /V TA Operating free-air temperature 55 5 40 85 C NOTES: 3. Unused inputs should be tied to VCC through a pullup resistor of approximately 5 k or greater to prevent them from floating. 4. All VCC and pi must be connected to the proper voltage supply. POST OFFICE BOX 655303 DALLAS, TEXAS 7565 3
SN54ACT6373, 74ACT6373 6-BIT D-TYPE TRANSPARENT LATCHES SCASC MARCH 990 REVISED SEPTEMBER 996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = 50 A IOH = 4 ma TA = 5 C SN54ACT6373 74ACT6373 MIN TYP MAX MIN MAX MIN MAX 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.7 3.8 5.5 V 4.94 4.7 4.8 IOH = 50 ma 5.5 V 3.85 IOH = 75 ma 5.5 V 3.85 IOL =50A IOL =4mA 4.5 V 0. 0. 0. 5.5 V 0. 0. 0. 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 IOL = 50 ma 5.5 V.65 IOL = 75 ma 5.5 V.65 II VI = VCC or 5.5 V ±0. ± ± A IOZ VO = VCC or 5.5 V ±0.5 ±0 ±5 A ICC VI = VCC or, IO = 0 5.5 V 8 60 80 A ICC One input at 3.4 V, Other inputs at or VCC 5.5 V 0.9 ma Ci VI = VCC or 5 V 4.5 pf Co VI = VCC or 5 V pf Not more than one output should be tested at a time, and the duration of the test should not exceed 0 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than to VCC. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure ) TA = 5 C SN54ACT6373 74ACT6373 MIN MAX MIN MAX MIN MAX tw Pulse duration, LE high 4 4 tsu Setup time, data before LE th Hold time, data after LE 5 5 5 V V switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure ) PARAMETER tpzh tpzl tphz tplz FROM TO TA = 5 C SN54ACT6373 74ACT6373 (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX D 3.8 7.9 9.4 3.8.8 3.8. 3. 8. 9.7 3. 3 3..3 LE 4.6 9.3 0.8 4.6 3.7 4.6.8 4.5 9. 0.5 4.5 3 4.5. OE 3. 8 9.5 3. 3 3.. 3.8 9.4. 3.8 5. 3.8 4. OE 5.3 8.6 9.9 5.3 5.3 0.7 4.3 7.4 8.7 4.3 9.8 4.3 9.4 4 POST OFFICE BOX 655303 DALLAS, TEXAS 7565
SN54ACT6373, 74ACT6373 6-BIT D-TYPE TRANSPARENT LATCHES SCASC MARCH 990 REVISED SEPTEMBER 996 operating characteristics, = 5 V, T A = 5 C Cpdd PARAMETER TEST CONDITIONS TYP s enabled 43 Power dissipation capacitance per latch CL =50pF pf, f=mhz pf s disabled 4.5 PARAMETER MEASUREMENT INFORMATION From Under Test CL = 50 pf (see Note A) 500 Ω 500 Ω S VCC Open TEST / tplz/tpzl tphz/tpzh S Open VCC Input LOAD CIRCUIT tw.5 V.5 V Timing Input Data Input tsu.5 V.5 V th.5 V Input In-Phase Out-of-Phase.5 V.5 V Control (low-level enabling) Waveform S at VCC (see Note B) Waveform S at (see Note B) tpzl tpzh.5 V tplz tphz.5 V 0% VCC 80% VCC VCC NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 3, tf = 3. D. The outputs are measured one at a time with one input traition per measurement. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 DALLAS, TEXAS 7565 5
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