S Series Power MOSFET PRODUCT SUMMARY at T J max. (V) 65 R DS(on) max. at 25 C (Ω) = V.9 Q g max. (nc) 98 Q gs (nc) 7 Q gd (nc) 25 Configuration Single D D 2 PAK (TO263) FEATURES Generation one High E AR capability Lower figureofmerit R on x Q g % avalanche tested Available Ultra low R on dv/dt ruggedness Ultra low gate charge (Q g ) Material categorization: for definitions of compliance please see www.vishay.com/doc?9992 APPLICATIONS G D S G S NChannel MOSFET PFC power supply stages Hard switching topologies Solar inverters UPS Motor control Lighting Server telecom ORDERING INFORMATION Package Lead (Pb)free and Halogenfree Lead (Pb)free D 2 PAK (TO263) GE3 E3 ABSOLUTE MAXIMUM RATINGS (T C = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 6 V GateSource Voltage ± 3 T C = 25 C 22 Continuous Drain Current at V I D T C = C 3 Pulsed Drain Current a I DM 65 D Linear Derating Factor 2 PAK 2 W/ C (TO263) Single Pulse Avalanche Energy b E AS 69 mj Repetitive Avalanche Energy a E AR 25 Maximum Power Dissipation D 2 PAK (TO263) P D 25 W DrainSource Voltage Slope T J = 25 C 37 dv/dt Reverse Diode dv/dt d 5.3 V/ns Operating Junction and Storage Temperature Range T J, T stg 55 to 5 Soldering Recommendations (Peak Temperature) c for s 3 C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. = 5 V, starting T J = 25 C, L = 28.2 mh, R g = 25 Ω, I AS = 7 A. c..6 mm from case. d. I SD I D, di/dt = A/μs, starting T J = 25 C. A S5982Rev. F, 27Apr5 Document Number: 9395
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient D 2 PAK (TO263) R thja 62 Maximum JunctiontoCase (Drain) D 2 PAK (TO263) R thjc.5 C/W SPECIFICATIONS (T J = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage = V, I D = ma 6 V Temperature Coefficient Δ /T J Reference to 25 C, I D = ma.7 V/ C GateSource Threshold Voltage (N) (th) =, I D = 25 μa 2. 4. V GateSource Leakage I GSS = ± 2 V ± na = ± 3 V ± μa = 6 V, = V Zero Gate Voltage Drain Current I DSS = 6 V, = V, T J = 5 C μa DrainSource OnState Resistance R DS(on) = V I D = A.6.9 Ω Forward Transconductance a g fs = 5 V, I D = 3 A 9.4 S Dynamic Input Capacitance C iss VGS = V, 28 Output Capacitance C oss = 25 V, 48 Reverse Transfer Capacitance C rss f =. MHz 33 pf Effective Output Capacitance (Time Related) C oss eff. (TR) a = V = V to 48 V 55 Total Gate Charge Q g 75 GateSource Charge Q gs = V I D = 22 A, = 48 V 7 nc GateDrain Charge Q gd 25 TurnOn Delay Time t d(on) 24 5 Rise Time t r = 38 V, I D = 22 A, 68 TurnOff Delay Time t d(off) R g = 9. Ω, = V 77 5 ns Fall Time t f 59 9 Gate Input Resistance R g f = MHz, open drain.65 Ω DrainSource Body Diode Characteristics Continuous SourceDrain Diode Current I S MOSFET symbol D 22 showing the integral reverse G Pulsed Diode Forward Current I SM p n junction diode 88 S A Diode Forward Voltage V SD T J = 25 C, I S = 22 A, = V.2 V Reverse Recovery Time t rr 462 69 ns Reverse Recovery Charge Q rr T J = 25 C, I F = I S, di/dt = A/μs, V R = 25 V 8.3 6 μc Reverse Recovery Current I RRM 3 6 A Note a. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while is rising from % to 8 %. S5982Rev. F, 27Apr5 2 Document Number: 9395
TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) 5 4 3 2 4 V Top 5 V 4 V 3 V 2 V V V 9 V 8 V 7 V 6 V 5 V Bottom 4 V 4 8 2 6 2 24, DraintoSource Voltage (V) T J = 25 C R DS(on), DraintoSource On Resistance (Normalized) 3.5 3 2.5 2.5.5 I D = 22 A = V 6 4 2 2 4 6 8 2 4 6 8 T J, Junction Temperature ( C) Fig. Typical Output Characteristics, T J = 25 C Fig. 4 Normalized OnResistance vs. Temperature 3 24 8 2 6 4. V Top 5 V 4 V 3 V 2 V V V 9 V 8 V 7 V 6 V 5 V Bottom 4 V 4 8 2 6 2 24, DraintoSource Voltage (V) T J = 5 C Capacitance (pf) C oss C rss = V, f = MHz C iss = C gs C gd C ds shorted C rss = C gd C oss = C ds C gd C iss, DraintoSource Voltage (V) Fig. 2 Typical Output Characteristics, T J = 5 C Fig. 5 Typical Capacitance vs. DraintoSource Voltage 6 5 4 3 2 TJ = 5 C T J = 25 C, GatetoSource Voltage (V) 2.. 8. 6. 4. 2. I D = 22 A = 48 V = 3 V = 2 V 2 4 6 8, GatetoSource Voltage (V). 2 3 4 5 6 7 8 9 Q G, Total Gate Charge (nc) Fig. 3 Typical Transfer Characteristics Fig. 6 Typical Gate Charge vs. GatetoSource Voltage S5982Rev. F, 27Apr5 3 Document Number: 9395
25 I SD, Reverse Drain Current (A).... T J = 5 C T J = 25 C = V.2.4.6.8.2.4 V SD, SourcetoDrain Voltage (V) 2 5 5 25 5 75 25 5 T C, Case Temperature ( C) Fig. 7 Typical SourceDrain Diode Forward Voltage Fig. 9 Maximum Drain Current vs. Case Temperature 725 Operation in this area limited by R DS(on) µs ms T C = 25 C ms T J = 5 C Single Pulse., DraintoSource Voltage (V), DraintoSource Breakdown Voltage (V) 7 675 65 625 6 575 55 6 4 2 2 4 6 8 2 4 6 8 T J, Junction Temperature ( C) Fig. 8 Maximum Safe Operating Area Fig. DraintoSource Breakdown Voltage normalized Effective Transient Thermal Impedance. Duty Cycle =.5.2..5.2 Single Pulse. 4 3 2. Square Wave Pulse Duration (s) Fig. Normalized Thermal Transient Impedance, JunctiontoCase S5982Rev. F, 27Apr5 4 Document Number: 9395
R D Q G R g D.U.T. Q GS Q GD V Pulse width µs Duty factor. % Fig. 2 Switching Time Test Circuit V G Charge Fig. 6 Basic Gate Charge Waveform 9 % Current regulator Same type as D.U.T. 5 kω 2 V.2 µf.3 µf % t d(on) t r t d(off) t f D.U.T. V DS Fig. 3 Switching Time Waveforms 3 ma Vary t p to obtain required I AS L Fig. 7 Gate Charge Test Circuit I G I D Current sampling resistors R g I AS D.U.T V t p. W Fig. 4 Unclamped Inductive Test Circuit t p I AS Fig. 5 Unclamped Inductive Waveforms S5982Rev. F, 27Apr5 5 Document Number: 9395
Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test Driver gate drive P.W. Period D = P.W. Period = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt Reapplied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. = 5 V for logic level devices Fig. 8 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?9395. S5982Rev. F, 27Apr5 6 Document Number: 9395
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