E Series Power MOSFET PRODUCT SUMMARY (V) at T J max. 65 R DS(on) max. at 25 C ( ) = V.25 Q g max. (nc) 3 Q gs (nc) 5 Q gd (nc) 39 Configuration Single FEATURES Low FigureofMerit (FOM) R on x Q g Low Input Capacitance (C iss ) Reduced Switching and Conduction Losses Ultra Low Gate Charge (Q g ) Avalanche Energy Rated (UIS) Material categorization: For definitions please see www.vishay.com/doc?9992 TO22AB G DS G D S NChannel MOSFET APPLICATIONS Server and Telecom Power Supplies Switch Mode Power Supplies (SMPS) Power Factor Correction Power Supplies (PFC) Lighting HighIntensity Discharge (HID) Fluorescent Ballast Lighting LED Lighting Industrial Welding Induction Heating Motor Drives Battery Chargers Renewable Energy Solar (PV Inverters) ORDERING INFORMATION Package Lead (Pb)free Lead (Pb)free and Halogenfree TO22AB E3 GE3 ABSOLUTE MAXIMUM RATINGS (T C = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 6 GateSource Voltage ± 2 V GateSource Voltage AC (f > Hz) 3 Continuous Drain Current (T J = 5 C) at V T C = 25 C 29 T C = C 8 A Pulsed Drain Current a M 65 Linear Derating Factor 2 W/ C Single Pulse Avalanche Energy b E AS 69 mj Maximum Power Dissipation P D 25 W Operating Junction and Storage Temperature Range T J, T stg 55 to 5 C DrainSource Voltage Slope T J = 25 C 37 dv/dt Reverse Diode dv/dt d 8 V/ns Soldering Recommendations (Peak Temperature) for s 3 c C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. V DD = 5 V, starting T J = 25 C, L = 28.2 mh, R g = 25, I AS = 7 A. c..6 mm from case. d. I SD, di/dt = A/μs, starting T J = 25 C. S233 Rev. E, 24Dec2 Document Number: 9456
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient R thja 62 C/W Maximum JunctiontoCase (Drain) R thjc.5 SPECIFICATIONS (T J = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage = V, = 25 μa 6 V Temperature Coefficient /T J Reference to 25 C, = 25 μa.64 V/ C GateSource Threshold Voltage (N) (th) =, = 25 μa 2. 4. V GateSource Leakage I GSS = ± 2 V ± na = 6 V, = V Zero Gate Voltage Drain Current SS = 6 V, = V, T J = 5 C μa DrainSource OnState Resistance R DS(on) = V = 5 A.4.25 Forward Transconductance a g fs = 8 V, = 3 A 5.4 S Dynamic Input Capacitance C iss VGS = V, 26 Output Capacitance C oss = V, 38 Reverse Transfer Capacitance C rss f =. MHz 3 Effective Output Capacitance, Energy pf Related b C o(er) 98 = V to 48 V, = V Effective Output Capacitance, Time Related c C o(tr) 346 Total Gate Charge Q g 85 3 GateSource Charge Q gs = V = 5 A, = 48 V 5 nc GateDrain Charge Q gd 39 TurnOn Delay Time t d(on) 9 4 Rise Time t r V DD = 38 V, = 5 A, 32 65 TurnOff Delay Time t d(off) = V, R g = 4.7 63 95 ns Fall Time t f 36 75 Gate Input Resistance R g f = MHz, open drain.63 DrainSource Body Diode Characteristics MOSFET symbol D Continuous SourceDrain Diode Current I S 29 showing the integral reverse G Pulsed Diode Forward Current I SM S p n junction diode 65 Diode Forward Voltage V SD T J = 25 C, I S = 5 A, = V.3 V Body Diode Reverse Recovery Time t rr 42 65 ns Body Diode Reverse Recovery Charge Q rr T J = 25 C, I F = I S = 5 A, di/dt = A/μs, V R = 2 V 7 5 μc Reverse Recovery Current I RRM 32 65 A Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. C oss(er) is a fixed capacitance that gives the same energy as C oss while is rising from % to 8 % S. c. C oss(tr) is a fixed capacitance that gives the same charging time as C oss while is rising from % to 8 % S. A S233 Rev. E, 24Dec2 2 Document Number: 9456
TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) Drain Current (A) 8 7 6 5 4 3 T J = 25 C TOP 5 V 4 V 3 V 2 V V V 9. V 8. V 7. V 6. V BOTTOM 5. V, Drain Current (A) 8 6 4 T J = 25 C T J = 5 C 2 2 5 V 5 5 2 25 3 DraintoSource Voltage (V) Fig. Typical Output Characteristics, T C = 25 C 5 5 2 25, GatetoSource Voltage (V) Fig. 3 Typical Transfer Characteristics 5 3. Drain Current (A) 4 3 2 TOP 5 V 4 V 3 V 2 V V V 9. V 8. V 7. V 6. V BOTTOM 5. V R DS(on) OnResistance (Normalized) 2.5 2..5. = 5 A = V.5 T J = 5 C 5 5 2 25 3 DraintoSource Voltage (V) Fig. 2 Typical Output Characteristics, T C = 5 C. 6 4 2 2 4 6 8 2 4 6 T J Junction Temperature ( C) Fig. 4 Normalized OnResistance vs. Temperature S233 Rev. E, 24Dec2 3 Document Number: 9456
C Capacitance (pf) C iss C rss C oss = V, f = MHz C iss = C gs C gd x C ds shorted C rss = C gd C oss = C ds C gd 2 3 4 5 6 DraintoSource Voltage (V) Fig. 5 Typical Capacitance vs. DraintoSource Voltage, Drain Current (A). Operation in this area limited by R DS(on) T C = 25 C T J = 5 C Single Pulse M Limited BVDSS Limited., DraintoSource Voltage (V) * > minimum at which R DS(on) is specified Fig. 8 Maximum Safe Operating Area μs ms ms 24 3. GatetoSource Voltage (V) 2 6 2 8 4 = 5 A = 2 V = 3 V = 48 V, Drain Current (A) 25. 2. 5.. 5. 25 5 75 25 5 Q g Total Gate Charge (nc) Fig. 6 Typical Gate Charge vs. GatetoSource Voltage 25 5 75 25 5 T C Temperature( C) Fig. 9 Maximum Drain Current vs. Case Temperature 725 I S Source Current (A).. T J = 5 C T J = 25 C, DraintoSource Breakdown Voltage (V) 7 675 65 625 6 575...2.4.6.8..2.4.6 V SD SourcetoDrain Voltage (V) Fig. 7 Typical SourceDrain Diode Forward Voltage 55 6 4 2 2 4 6 8 2 4 6 T J Temperature( C) Fig. Temperature vs. DraintoSource Voltage S233 Rev. E, 24Dec2 4 Document Number: 9456
Normalized Effective Transient Thermal Impedance. Duty Cycle =.5.2..5.2 Single Pulse..... Square Wave Pulse Duration (s) Fig. Normalized Thermal Transient Impedance, JunctiontoCase R D t p R G V Pulse width µs Duty factor. % D.U.T. Fig. 2 Switching Time Test Circuit V DD V DD I AS Fig. 5 Unclamped Inductive Waveforms 9 % V Q G Q GS Q GD % t d(on) t r t d(off) t f V G Vary t p to obtain required I AS Fig. 3 Switching Time Waveforms R G V t p I AS L D.U.T. Ω V DD Charge Fig. 6 Basic Gate Charge Waveform Current regulator Same type as D.U.T. 2 V 5 kω.2 µf.3 µf D.U.T. V DS Fig. 4 Unclamped Inductive Test Circuit 3 ma Fig. 7 Gate Charge Test Circuit I G Current sampling resistors S233 Rev. E, 24Dec2 5 Document Number: 9456
Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. = 5 V for logic level devices Fig. 8 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?9456. S233 Rev. E, 24Dec2 6 Document Number: 9456
Package Information TO22AB D L H() Q L() E 2 3 M * b() Ø P A F MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. A 4.25 4.65.67.83 b.69..27.4 b().2.73.47.68 c.36.6.4.24 D 4.85 5.49.585.6 E.4.5.395.44 e 2.4 2.67.95.5 e() 4.88 5.28.92.28 F.4.4.45.55 H() 6.9 6.48.24.255 J() 2.4 2.92.95.5 L 3.35 4.2.526.552 L() 3.32 3.82.3.5 Ø P 3.54 3.94.39.55 Q 2.6 3..2.8 ECN: T3724Rev. O, 4Oct3 DWG: 547 Note * M =.32 mm to.62 mm (dimension including protrusion) Heatsink hole for HVM e b C e() J() Revison: 4Oct3 Document Number: 795
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