D Series Power MOSFET SiHD3N5D PRODUCT SUMMARY (V) at T J max. 55 R DS(on) max. () at 25 C V GS = V 3.2 Q g max. (nc) 2 Q gs (nc) 2 Q gd (nc) 3 Configuration Single DPAK (TO252) D G ORDERING INFORMATION Package Lead (Pb)free Lead (Pb)free and Halogenfree S G D S NChannel MOSFET FEATURES Optimal design Low area specific onresistance Low input capacitance (C iss ) Reduced capacitive switching losses High body diode ruggedness Available Avalanche energy rated (UIS) Optimal efficiency and operation Low cost Simple gate drive circuitry Low figureofmerit (FOM): R on x Q g Fast switching Material categorization: for definitions of compliance please see www.vishay.com/doc?9992 APPLICATIONS Consumer electronics Displays (LCD or plasma TV) Server and telecom power supplies SMPS Industrial Welding Induction heating Motor drives Battery chargers DPAK (TO252) SiHD3N5DE3 SiHD3N5DGE3 SiHD3N5DTGE3 SiHD3N5DT4GE3 SiHD3N5DT5GE3 ABSOLUTE MAXIMUM RATINGS (T C = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 5 GateSource Voltage ± 3 V V GS GateSource Voltage AC (f > Hz) 3 Continuous Drain Current (T J = 5 C) V GS at V T C = 25 C 3. I D T C = C.9 A Pulsed Drain Current a I DM 5.5 Linear Derating Factor.56 W/ C Single Pulse Avalanche Energy b E AS.4 mj Maximum Power Dissipation P D 69 W Operating Junction and Storage Temperature Range T J, T stg 55 to 5 C DrainSource Voltage Slope T J = 25 C 24 dv/dt Reverse Diode dv/dt d.22 V/ns Soldering Recommendations (Peak Temperature) c for s 3 C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. V DD = 5 V, starting T J = 25 C, L = 2.3 mh, R g = 25, I AS = 3 A. c..6 mm from case. d. I SD I D, starting T J = 25 C. S6Rev. D, 25Jan6 Document Number: 9495 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
SiHD3N5D THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient R thja 62 Maximum JunctiontoCase (Drain) R thjc.8 C/W SPECIFICATIONS (T J = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage V GS = V, I D = 25 μa 5 V Temperature Coefficient /T J Reference to 25 C, I D = 25 μa.56 V/ C GateSource Threshold Voltage (N) V GS(th) = V GS, I D = 25 μa 3 5 V GateSource Leakage I GSS V GS = ± 3 V ± na = 5 V, V GS = V Zero Gate Voltage Drain Current I DSS = 4 V, V GS = V, T J = 25 C μa DrainSource OnState Resistance R DS(on) V GS = V I D = 2.5 A 2.6 3.2 Forward Transconductance a g fs = 8 V, I D =.5 A S Dynamic Input Capacitance C iss VGS = V, 75 Output Capacitance C oss = V, 2 Reverse Transfer Capacitance C rss f = MHz 5 Effective Output Capacitance, Energy pf Related b C o(er) 2 = V to 4 V, V GS = V Effective Output Capacitance, Time Related c C o(tr) 26 Total Gate Charge Q g 6 2 GateSource Charge Q gs V GS = V I D =.5 A, = 4 V 2 nc GateDrain Charge Q gd 3 TurnOn Delay Time t d(on) 2 24 Rise Time t r V DD = 4 V, I D =.5 A 9 8 TurnOff Delay Time t d(off) R g = 9., V GS = V 22 ns Fall Time t f 3 26 Gate Input Resistance R g f = MHz, open drain 3.3 DrainSource Body Diode Characteristics Continuous SourceDrain Diode Current I MOSFET symbol D S 3 showing the G integral reverse Pulsed Diode Forward Current I SM P N junction diode 2 S A Diode Forward Voltage V SD T J = 25 C, I S =.5 A, V GS = V.2 V Reverse Recovery Time t rr 293 ns Reverse Recovery Charge Q rr T J = 25 C, I F = I S =.5 A, di/dt = A/μs, V R = 2 V.74 μc Reverse Recovery Current I RRM 5 A Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. C oss(er) is a fixed capacitance that gives the same energy as C oss while is rising from % to 8 % S. c. C oss(tr) is a fixed capacitance that gives the same charging time as C oss while is rising from % to 8 % S. S6Rev. D, 25Jan6 2 Document Number: 9495 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
SiHD3N5D TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) I D, DraintoSource Current (A) 6 5 4 3 2 TOP 5 V 4 V 3 V 2 V V V 9 V T J = 25 C 8 V 7 V 6 V 5 5 2 25 3, DraintoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) 3 I D =.5 A 2.5 2.5 V GS = V.5 6 4 2 2 4 6 8 2 4 6 T J, Junction Temperature ( C) Fig. Typical Output Characteristics Fig. 4 Normalized OnResistance vs. Temperature I D, DraintoSource Current (A) 4 3 2 TOP 5 V 4 V 3 V 2 V V V 9. V 8. V 7. V 6. V 5. V T J = 5 C Capacitance (pf) C iss C oss C rss V GS = V, f = MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd 5 5 2 25 3, DraintoSource Voltage (V) Fig. 2 Typical Output Characteristics 2 3 4 5, DraintoSource Voltage (V) Fig. 5 Typical Capacitance vs. DraintoSource Voltage I D, DraintoSource Current (A) 6 5 4 3 2 T J = 5 C T J = 25 C V GS, GatetoSource Voltage (V) 24 2 6 2 8 4 = 4 V = 25 V = V 5 5 2 25 V GS, GatetoSource Voltage (V) 3 6 9 2 Q g, Total Gate Charge (nc) Fig. 3 Typical Transfer Characteristics Fig. 6 Typical Gate Charge vs. GatetoSource Voltage S6Rev. D, 25Jan6 3 Document Number: 9495 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
SiHD3N5D 3. I SD, Reverse Drain Current (A). T J = 5 C T J = 25 C V GS = V I D, Drain Current (A) 2.5 2..5..5..2.4.6.8..2.4.6 V SD, SourceDrain Voltage (V) 25 5 75 25 5 T J, Case Temperature ( C) Fig. 7 Typical SourceDrain Diode Forward Voltage Fig. 9 Maximum Drain Current vs. Case Temperature I D, Drain Current (A).. Operation in this area limited by R DS(on) Limited by R DS(on) * T C = 25 C T J = 5 C Single Pulse BVDSS Limited μs ms ms, DraintoSource Voltage (V) * V GS > minimum V GS at which R DS(on) is specified, DraintoSource Breakdown Voltage (V) 625 6 575 55 525 5 475 6 4 2 2 4 6 8 2 4 6 T J, Junction Temperature ( C) Fig. 8 Maximum Safe Operating Area Fig. Typical DraintoSource Voltage vs. Temperature Normalized Effective Transient Thermal Impedance. Duty Cycle =.5.2..5.2 Single Pulse..... Pulse Time (s) Fig. Normalized Thermal Transient Impedance, JunctiontoCase S6Rev. D, 25Jan6 4 Document Number: 9495 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
SiHD3N5D R D V GS D.U.T. V Q G R G V DD Q GS Q GD V Pulse width µs Duty factor. % Fig. 2 Switching Time Test Circuit V G Charge Fig. 6 Basic Gate Charge Waveform 9 % Current regulator Same type as D.U.T. 5 kω 2 V.2 µf.3 µf % V GS t d(on) t r t d(off) t f D.U.T. V DS V GS Fig. 3 Switching Time Waveforms 3 ma I G I D Current sampling resistors L Fig. 7 Gate Charge Test Circuit Vary t p to obtain required I AS R G I AS D.U.T V DD V t p. Ω Fig. 4 Unclamped Inductive Test Circuit t p V DD I AS Fig. 5 Unclamped Inductive Waveforms S6Rev. D, 25Jan6 5 Document Number: 9495 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
SiHD3N5D Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period V GS = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 8 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?9495. S6Rev. D, 25Jan6 6 Document Number: 9495 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
Package Information TO252AA Case Outline E b3 A C2 MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. L3 A 2.8 2.38.86.94 A.27.5 b.64.88.25.35 b2.76.4.3.45 D H b3 4.95 5.46.95.25 C.46.6.8.24 C2.46.89.8.35 b e e b2 L4 L5 gage plane height (.5 mm) C A L D 5.97 6.22.235.245 D 4..6 E 6.35 6.73.25.265 E 4.32.7 H 9.4.4.37.4 e 2.28 BSC.9 BSC e 4.56 BSC.8 BSC L.4.78.55.7 L3.89.27.35.5 D L4.2.4 L5..52.4.6 E ECN: T6236Rev. P, 6May6 DWG: 5347 Notes Dimension L3 is for reference only. Revision: 6May6 Document Number: 797 For technical questions, contact: pmostechsupport@vishay.com ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
Application Note 826 RECOMMENDED MINIMUM PADS FOR DPAK (TO252).224 (5.69).9 (2.286).87 (2.22).42 (.668).243 (6.8).8 (4.572).55 (.397) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72594 www.vishay.com Revision: 2Jan8 3
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