D Series Power MOSFET TO22 FULLPAK D G S G D S NChannel MOSFET PRODUCT SUMMARY (V) at T J max. 55 R DS(on) max. () at 25 C V GS = V.28 Q g max. (nc) 76 Q gs (nc) Q gd (nc) 7 Configuration Single ORDERING INFORMATION Package Lead (Pb)free FEATURES Optimal design Low area specific onresistance Low input capacitance (C iss ) Available Reduced capacitive switching losses High body diode ruggedness Avalanche energy rated (UIS) Optimal efficiency and operation Low cost Simple gate drive circuitry Low figureofmerit (FOM): R on x Q g Fast switching Material categorization: for definitions of compliance please see www.vishay.com/doc?9992 Note * This datasheet provides information about parts that are RoHScompliant and / or parts that are non RoHScompliant. For example, parts with lead (Pb) terminations are not RoHScompliant. Please see the information / tables in this datasheet for details APPLICATIONS Consumer electronics Displays (LCD or Plasma TV) Server and telecom power supplies SMPS Industrial Welding Induction heating Motor drives Battery chargers TO22 FULLPAK E3 ABSOLUTE MAXIMUM RATINGS (T C = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT Drainsource voltage 5 Gatesource voltage ± 3 V V GS Gatesource voltage AC (f > Hz) 3 Continuous drain current (T J = 5 C) e V GS at V T C = 25 C 8 I D T C = C A Pulsed drain current a I DM 53 Linear derating factor.3 W/ C Single pulse avalanche energy b E AS 5 mj Maximum power dissipation P D 39 W Operating junction and storage temperature range T J, T stg 55 to 5 C Drainsource voltage slope T J = 25 C 24 dv/dt Reverse diode dv/dt d.4 V/ns Soldering recommendations (peak temperature) c For s 3 C Mounting torque M3 screw.6 Nm Notes a. Repetitive rating; pulse width limited by maximum junction temperature b. V DD = 5 V, starting T J = 25 C, L = 2.3 mh, R g = 25, I AS = A c..6 mm from case d. I SD I D, starting T J = 25 C e. Limited by maximum junction temperature S855Rev. C, 22Jan8 Document Number: 957
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum junctiontoambient R thja 65 Maximum junctiontocase (drain) R thjc 3.2 C/W SPECIFICATIONS (T J = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drainsource breakdown voltage V GS = V, I D = 25 μa 5 V temperature coefficient /T J Reference to 25 C, I D = 25 μa.58 V/ C Gate threshold voltage (N) V GS(th) = V GS, I D = 25 μa 3. 5. V Gatesource leakage I GSS V GS = ± 3 V ± na = 5 V, V GS = V Zero gate voltage drain current I DSS = 4 V, V GS = V, T J = 25 C μa Drainsource onstate resistance R DS(on) V GS = V I D = 9 A.23.28 Forward transconductance g fs = 5 V, I D = 9 A 6.4 S Dynamic Input capacitance C iss VGS = V, 5 Output capacitance C oss = V, 3 Reverse transfer capacitance C rss f =. MHz 4 Effective output capacitance, energy pf related a C o(er) 3 V GS = V, = V to 4 V Effective output capacitance, time related b C o(tr) 64 Total gate charge Q g 38 76 Gatesource charge Q gs V GS = V I D = 9 A, = 4 V nc Gatedrain charge Q gd 7 Turnon delay time t d(on) 9 38 Rise time t r V DD = 4 V, I D = 9 A, 36 72 Turnoff delay time t d(off) V GS = V, R g = 9. 36 72 ns Fall time t f 3 6 Gate input resistance R g f = MHz, open drain.7 DrainSource Body Diode Characteristics Continuous sourcedrain diode current I MOSFET symbol D S 8 showing the G integral reverse Pulsed diode forward current I SM P N junction diode 72 S A Diode forward voltage V SD T J = 25 C, I S = 9 A, V GS = V.2 V Reverse recovery time t rr 354 ns Reverse recovery charge Q rr T J = 25 C, I F = I S = 9 A, di/dt = A/μs, V R = 2 V 3.9 μc Reverse recovery current I RRM 2 A Notes a. C oss(er) is a fixed capacitance that gives the same energy as C oss while is rising from % to 8 % S b. C oss(tr) is a fixed capacitance that gives the same charging time as C oss while is rising from % to 8 % S S855Rev. C, 22Jan8 2 Document Number: 957
www.vishay.com TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) I D, Drain to Source Current (A) 6 5 4 3 2 TOP 5V 4V 3V 2V V V 9.V 8.V 7.V 6.V T J = 25 C R DS(on), DraintoSource On Resistance (Normalized) 3 2.5 2.5.5 I D = 9 A V GS = V 5. V 5 5 2 25 3, Drain to Source Voltage (V) Fig. Typical Output Characteristics 6 4 2 2 4 6 8 2 4 6 T J, Junction Temperature ( C) Fig. 4 Normalized OnResistance vs. Temperature I D, DraintoSource Current (A) 4 TOP 5V 4V 3V 2V 32 V V 9.V 8.V 24 7.V 6.V BOTYTOM 5.V 6 8 T J = 5 C Capacitance (pf) C iss C oss C rss V GS = V, f = MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd 5. V 5 5 2 25 3, DraintoSource Voltage (V) 2 3 4 5, DraintoSource Voltage (V) Fig. 2 Typical Output Characteristics Fig. 5 Typical Capacitance vs. DraintoSource Voltage 6 24 I D, Drain tosource Current (A) 5 4 3 2 T J = 5 C T J = 25 C V GS, GatetoSource Voltage (V) 2 6 2 8 4 = 4 V = 25 V = V 5 5 2 25 V GS, GatetoSource Voltage (V) 2 3 4 5 6 7 Q g, Total Gate Charge (nc) Fig. 3 Typical Transfer Characteristics Fig. 6 Typical Gate Charge vs. GatetoSource Voltage S855Rev. C, 22Jan8 3 Document Number: 957
2. I SD, Reverse Drain Current (A) T J = 5 C T J = 25 C I D, Drain Current (A) 6. 2. 8. 4. V GS = V..2.4.6.8.2.4.6 V SD, SourceDrain Voltage (V) Fig. 7 Typical SourceDrain Diode Forward Voltage 25 5 75 25 5 T J, Case Temperature ( C) Fig. 9 Maximum Drain Current vs. Case Temperature 625 Operation in this area limited by R DS(on) 6 I D, Drain Current (A) Limited by R DS(on) * μs ms, DraintoSource Breakdown Voltage (V) 575 55 525. T C = 25 C T J = 5 C Single Pulse BVDSS Limited ms, DraintoSource Voltage (V) * V GS > minimum V GS at which R DS(on) is specified 5 475 6 4 2 2 4 6 8 2 4 6 T J, Junction Temperature ( C) Fig. 8 Maximum Safe Operating Area Fig. Typical DraintoSource Voltage vs. Temperature Duty cycle =.5 Normalized Effective Transient Thermal Impedance..2..5.2 Single pulse..... Pulse Time (s) Fig. Normalized Thermal Transient Impedance, JunctiontoCase S855Rev. C, 22Jan8 4 Document Number: 957
R D V GS D.U.T. V Q G R G V DD Q GS Q GD V Pulse width µs Duty factor. % Fig. 2 Switching Time Test Circuit V G Charge Fig. 6 Basic Gate Charge Waveform 9 % Current regulator Same type as D.U.T. 5 kω 2 V.2 µf.3 µf % V GS t d(on) t r t d(off) t f D.U.T. V DS V GS Fig. 3 Switching Time Waveforms 3 ma L I G I D Current sampling resistors Vary t p to obtain required I AS Fig. 7 Gate Charge Test Circuit R G I AS D.U.T V DD V t p. Ω Fig. 4 Unclamped Inductive Test Circuit t p V DD I AS Fig. 5 Unclamped Inductive Waveforms S855Rev. C, 22Jan8 5 Document Number: 957
Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period V GS = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 8 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?957. S855Rev. C, 22Jan8 6 Document Number: 957
Package Information TO22 FULLPAK (HIGH VOLTAGE) n E Ø P A A d d3 D u L V L b e b2 b3 c A2 MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. A 4.57 4.83.8.9 A 2.57 2.83.. A2 2.5 2.85.99.2 b.622.89.24.35 b2.229.4.48.55 b3.229.4.48.55 c.44.629.7.25 D 8.65 9.8.34.386 d 5.88 6.2.622.635 d3 2.3 2.92.484.59 E.36.63.48.49 e 2.54 BSC. BSC L 3.2 3.73.52.54 L 3. 3.5.22.38 n 6.5 6.5.238.242 Ø P 3.5 3.45.2.36 u 2.4 2.5.94.98 v.4.5.6.2 ECN: X926Rev. B, 26Oct9 DWG: 5972 Notes. To be used only for process drawing. 2. These dimensions apply to all TO22, FULLPAK leadframe versions 3 leads. 3. All critical dimensions should C meet C pk >.33. 4. All dimensions include burrs and plating thickness. 5. No chipping or package damage. Document Number: 9359 www.vishay.com Revision: 26Oct9
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