Low Power and High Performance Level-up Shifters for Mobile Devices with Multi-V DD

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.5, OCTOBER, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/jsts.2017.17.5.577 ISSN(Online) 2233-4866 Low and High Performance Level-up Shifters for Mobile Devices with Multi-V DD Dong-Ik Jeon, Kwang-Soo Han, and Ki-Seok Chung Abstract Reducing power consumption in a processor using multiple supply voltages is commonly adopted in mobile embedded systems. Level shifters are crucial components in such systems to interface two modules operating with different supply voltage levels. In this paper, we propose two low power and high performance level-up shifters called dual step level-up shifter (DSLS) and stacked dual step level-up shifter (SDSLS). DSLS has a dual step buffer structure to improve the speed and the circuit size over conventional level-up shifters as well as power consumption by avoiding contention. SDSLS is proposed to improve DSLS further for low power consumption by utilizing transistor stacking. By selectively using these two level-up shifters according to the difference between high and low supply voltages, delay is reduced by up to 79.0% and power consumption is reduced by up to 50.2%. Index Terms Level shifter, multi-v DD, power gating additional interface circuit called level shifter is necessary to adjust different voltage levels in the multi- V DD system. Since the level shifter plays a key role in stable operation of such system, designing low power and high performance level shifters will be important. There are two types of level shifters. We call a level-up shifter when the circuit adjusts the voltage level up from a low voltage region to a high voltage region. A leveldown shifter carries out the opposite operation. While level-down shifting can be implemented with a simple structure like buffers, level-up shifters are more complicated because they commonly employ differential logic structures. However, differential logic structures often suffer from contention between the NMOS logic and the PMOS logic. This contention may result in large amount of power consumption and significant delay. To resolve this issue, we propose two low power and high performance level-up shifters called dual step level-up shifter (DSLS) and stacked dual step level-up shifter (SDSLS) in this paper. I. INTRODUCTION II. RELATED WORKS consumption has become one of the most critical issues in designing mobile embedded systems [1]. Dynamic power consumption of digital CMOS circuits is often much larger than static power consumption. Therefore, to reduce the dynamic power consumption, designing circuits with multiple levels of supply voltages (multi-v DD ) is commonly employed [2]. However, the Manuscript received Dec. 12, 2013; accepted Jan. 21, 2015 Department of Electronic and Computer Engineering, Hanyang University, Seoul, Korea E-mail : kchung@hanyang.ac.kr Fig. 1(a) shows a commonly used level-up shifter where a differential structure is employed. This differential structure may suffer from significant power consumption and delay due to contention between the PMOS and the NMOS logics. To relieve this problem, a level-up shifter called contention mitigated level-up shifter (CMLS) was suggested as shown in Fig. 1(b) [4]. This converter greatly reduced the contention by adding a couple of PMOS transistors between the existing PMOS and NMOS logics. The results in [4] reported that CMLS had a 24% reduction in the power consumption

578 DONG-IK JEON et al : LOW POWER AND HIGH PERFORMANCE LEVEL-UP SHIFTERS FOR MOBILE DEVICES WITH and a 50% reduction in the delay with a 4% increase in the circuit size. However, it could not avoid the overhead on power consumption and delay due to contention completely. III. PROPOSED LEVEL-UP SHIFTERS 1. Background A level-down shifter can be constructed using a simple buffer structure as shown in Fig. 2. However, a level-up shifter with such buffer structure may not work properly. Fig. 3(a) shows a level-up shifter with the buffer structure. When the input is V DDL, the gate-to-source voltage of the P1 transistor becomes V DDL - V DDH. If this exceeds the threshold voltage of P1 ( Vtp ), the P1 will turn ON and burn contention current. As a result, the input voltage (V DDL ) should be bigger than V DDH - Vtp, which implies that the voltage difference in two domains should be very small. Therefore, a level-up shifter needs some additional circuitry to complement the low input signal which is the differential structure as shown in Fig. 1(a). However, if the supply voltage of the front inverter is lower than the high voltage (V DDH ), the operational range of the input voltage becomes wider. We call this dual step effect. Suppose that the supply voltage of the front inverter is V DDM which is an intermediate value between V DDL and V DDH (V DDL < V DDM < V DDH ) as shown in Fig. 3(b). Then the input voltage should be bigger than V DDM - Vtp. Therefore, the operational range is bigger than the buffer structure in Fig. 3(a) by V DDH - V DDM. On the other hand, when input is 0 V, V DDM goes through the back inverter input. However, the back inverter has no problem as long as V DDM is bigger than V DDH Vtp. Fig. 4 shows the input range difference between the level-up shifter in Fig 3(a) and that in Fig. 3(b) with respect to the back inverter s DC characteristics, when V DDL = 3 V, V DDM = 4.5 V, V DDH = 5 V, and Vtn = Vtp = 1.5 V. As shown in Fig. 4, the low input voltage region of the buffer structure is greater than 1 V due to the front inverter s contention current. But the low voltage of the level-up shifter with the dual step is below 1 V, because V DDM induces a dual step effect. As long as V DDM is greater than V DDH Vtp, the back inverter will operate properly. Due to this reason, it is noted that Dual step input range is left-shifted from Buffer structure input range. This shifted characteristic curve shows that, by (a) Fig. 1. (a) Conventional level-up shifter [3], (b) Contention mitigated level-up shifter (CMLS) [4]. applying the dual step, a balanced input range is achieved compared to a skewed buffer structure with the single voltage supply. This means that the dual step design works better as a level-up shifter. Therefore, the proposed level-up shifters are based on the dual-step effect. 2. Dual Step Level-up Shifter and Stacked Dual Step Level-up Shifter Fig. 5 shows one of the two proposed shifters called dual step level-up shifter (DSLS). The shifter consists of a buffer with N1, N2, P1, and P2, and an additional P3 which is always-on to generate some voltage drop. Node V X between P3 and P1 will have different operation voltages on the pull-up and the pull-down operations, respectively. (b) Fig. 2. A level-down shifter with buffer structure. (a) Fig. 3. (a) Improper level-up shifter with the buffer structure, (b) Conceptual structure of level-up shifter with dual step effect. (b)

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.5, OCTOBER, 2017 579 (a) Fig. 4. The input range difference in the back inverter s DC characteristics. (b) Fig. 6. (a) Pull-down operation of the DSLS front inverter, (b) Pull-up operation of the DSLS front inverter. Fig. 5. Dual step level-up shifter (DSLS). Fig. 6(a) shows the pull-down operation in the front inverter when the input voltage is V DDL. Typically, the input voltage to level-up shifters has a lower voltage level than V DDH, and this causes some static (leakage) current to flow in the front inverter. Therefore, a certain amount of voltage drop may happen and a dual step effect takes place according to the voltage difference. Even though static power consumption due to the leakage current is unavoidable, the amount of the total power consumption is much less than that due to contention of conventional level-up shifters. Section IV will address simulation results regarding this. The pullup operation in the front inverter when the input signal is 0 V (GND) is shown in Fig. 6(b) where P1 is completely ON, and N1 completely is OFF. Therefore, the input of the back inverter is connected to V DDH. The graph in Fig. 7 shows the voltage and static current curve at V X according to DSLS input voltage at the front inverter with 32 nm NMOS width and 64 nm PMOS width. When V DDH =1 V and the input voltage is in the range of 0.6 V to 0.9 V, V X will have a value between the input voltage and V DDH. However, to have an appropriate voltage at V X, some amount of static Fig. 7. Voltage and static current at V X of DSLS. current should exist. This implies that the amount of power consumption due to the leakage current would be quite large, especially if the input voltage has a big difference from V DDH. To reduce this large leakage current, we can utilize transistor stacking which connects an additional transistor in series to reduce sub-threshold leakage current [5]. Therefore, we propose another levelup shifter which is a DSLS with transistor stacking called Stacked DSLS (SDSLS), and it is shown in Fig. 8. In the SDSLS design, the added P4 causes the size and the delay to increase a little, but the power dissipation due to static current to decrease. Due to stacking with P4 and P1, the sub-threshold leakage decreases significantly when we compare SDSLS with DSLS. Reducing the subthreshold leakage in SDSLS seemingly results in

580 DONG-IK JEON et al : LOW POWER AND HIGH PERFORMANCE LEVEL-UP SHIFTERS FOR MOBILE DEVICES WITH Fig. 8. Stacked dual step level-up shifter (SDSLS). Fig. 10. comparison of level-up shifters. IV. SIMULATION RESULTS Fig. 9. Voltage and static current at V X of SDSLS. reducing the amount of voltage drop, which may cause some problem in how DSLS works using the dual step logic due to the small voltage difference between front and back inverter. However, the voltage drop in SDSLS is sufficiently big due to high resistance in P4 when the input is connected to V DDL. Fig. 9 shows the voltage and the current curves at V X in SDSLS. The amounts of static current of DSLS and SDSLS are 6 ua and 0.1 ua, respectively when the input is 0.6 V. The amount of current in SDSLS will be merely 2% of that of DSLS, and therefore the power consumption due to static current is considerably reduced when the input voltage is V DDL. However, due to high resistance at P4, the voltage stays at 0.83 V for input voltages ranging from 0.6 V to 0.9 V. Thus, when the input is greater than 0.8 V, SDSLS may not be able to have a dual step effect properly, which implies that DSLS is advantageous over SDSLS because SDSLS is bigger and slower due to the added transistor. Therefore, the best trade-off among delay, size and power consumption can be found by using DSLS when we know that the input voltage ranges from 0.8 V to 0.9 V, and by using SDSLS when the input voltage ranges from 0.6 V to 0.8 V. To evaluate the quality of the proposed designs, we compared the proposed designs with aforementioned two existing designs: the conventional level-up shifter (CLS) in Fig. 1(a) and CMLS in Fig. 1(b) in terms of delay and power consumption. All the experiments were conducted using Synopsys HSPICE, and a 32 nm predictive technology model was employed. The NMOS width and that PMOS width are 32 nm and 64 nm, respectively. The threshold voltages (V TH ) of NMOS and PMOS are 0.49 V and -0.49 V, respectively. V DDH was set to 1.0 V and the V DDL ranged from 0.6 V to 0.9 V. The input pulse is set with a pulse period of 1 ns and the rising/falling time of 0.1 ns. 1. Fig. 10 shows the averages of rising and falling delays of all designs that we compared. According to Table 1, the delay of CMLS is about the same as the one in CLS. However, the delay of CLS and CMLS increase as V DDL decreases. This is because detrimental effect of contention leads to significant increase in delay when V DDL is low. Though, since CMLS was proposed to reduce the effect of contention, the delay increased at a lower rate than CLS. On the other hand, in case of DSLS and SDSLS, the contention does not exist, and the existence of P3 and P4 helps the delay decrease significantly. Consequently, for V DDL =0.6 V, DSLS and SDSLS showed less delay than CLS by up to 79.0% and 73.5%, respectively.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.5, OCTOBER, 2017 581 Table 1. Simulation results of level-up shifters in each input voltages Input Voltage (V DDL) 0.6 V 0.7 V 0.8 V 0.9 V CLS 63.4 1.52 0.0056 44.4 1.22 0.0015 30.9 1.30 0.0013 25.2 1.37 0.0033 CMLS 64.9 0.98 0.0011 49.1 0.93 0.0014 37.1 0.90 0.0012 29.3 1.03 0.0016 DSLS 13.3 1.63 0.0063 11.7 1.03 0.0084 11.2 1.11 0.0061 10.6 1.20 0.0031 SDSLS 16.8 0.76 0.0045 17.4 0.83 0.0029 14.9 0.95 0.0032 15.3 1.14 0.0026 Fig. 12. -delay product comparison. Fig. 11. consumption of level-up shifters. 2. Consumption Fig. 11 shows comparison results on power consumption of CLS, CMLS, DSLS and SDSLS. First, in case of CLS and CMLS, CMLS consumes less power than CLS by up to 35.5%. That is because the added PMOS transistor greatly reduces the contention and the leakage power consumption in CMLS. However, for CLS and CMLS, the amount of power consumption due to the contention is quite significant. When V DDL decreases, the amount of negative impact of the contention in CLS grows rapidly, which causes large amount of power to dissipate. On the contrary, in DSLS, contention does not exist. However, in case of DSLS, static power consumption exists, and the amount of static power consumption will increase exponentially as V DDL is reduced. This is because the leakage current of DSLS rapidly increases at the input voltage below 0.8 V, as shown in Fig. 7. To resolve this issue, SDSLS was designed with transistor stacking to reduce the static current. Although the size and the delay are increased slightly, the power consumption is significantly reduced. Consequently, for V DDL =0.6 V, SDSLS consumes less power than CLS does by up to 50.2%. 3. -delay Product Fig. 12 shows the comparison results with respect to power-delay products (PDP) of CLS, CMLS, DSLS and SDSLS. Comprehensively speaking, DSLS and SDSLS show much better results than CMLS and CLS. For all input voltage conditions, the PDP values of DSLS and SDSLS are better than CLS by at least 49.3% up to 86.8%. Also, in case of DSLS and SDSLS, SDSLS shows a better PDP value when the input is less than 0.8 V while DSLS shows a better value otherwise. Therefore, DSLS and SDSLS should be used selectively based on the input voltage level. 4. Level-up shifters are key interface circuits in multi- V DD systems. Thus, stable and reliable operation is crucial. can be estimated by checking the output voltage when the input voltage is V DDL, and analyzing how far it deviates from the ideal V DDH. Table

582 DONG-IK JEON et al : LOW POWER AND HIGH PERFORMANCE LEVEL-UP SHIFTERS FOR MOBILE DEVICES WITH 1 shows the offset amount of the output signals from the ideal V DDH voltage when we variably change V DDL from 0.6 V to 0.9 V. Under all input values, the amounts of deviation of the proposed DSLS and SDSLS are similar to other level-up shifters. Hence, we confirm that the operation of the proposed design is very reliable. V. CONCLUSION Minimizing power consumption is arguably one of the most important design goals in modern VLSI systems. Since dynamic power consumption often accounts for the major source of the total power dissipation, multi-v DD designs are quite popular. In this multi-v DD design, designing efficient level-up shifters is crucial. In this paper, we proposed novel level-up shifters called dual step level-up shifter (DSLS) and stacked dual step levelup shifter (SDSLS), and compared the designs with two conventional designs, a conventional level-up shifter (CLS) and contention mitigated level-up shifter (CMLS) in terms of delay, power consumption and power-delay product (PDP) values. DSLS is very effective when the difference between high and low voltages is under 20%, but SDSLS is better otherwise. From simulations, in case of DSLS and SDSLS, we verified that (1) the delays are less than CLS by up to 79.0% and 73.5%, respectively, (2) the power consumptions are less than CLS by up to 14.1% and 50.2%, respectively, and finally (3) the PDP values are better than CLS by at least 77.4% up to 86.8%. In conclusion, the quality of DSLS and SDSLS is excellent in all design quality perspectives. ACKNOWLEDGMENTS This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (R7119-16- 1009, Development of Intelligent Semiconductor Core Technologies for IoT Devices based on Harvest Energy). Techniques for Dual VDD Circuits, Asia and South Pacific Design Automation Conference, 2006, ASP-DAC 2006, pp.838-843, 2006 [3] Neil H.E. Weste, et al, CMOS VLSI design: A Circuits and Systems Perspective, Addison Wesley. [4] Canh Q. Tran, et al, Low-power High-speed Level Shifter Design for Block-level Dynamic Voltage Scaling Environment, IEEE International Conference on Integrated Circuit Design and Technology, 2005, ICICDT, pp.229-232, 2005. [5] Siva Narendra, et al, Scaling of stack effect and its application for leakage reduction, International Symposium on Low Electronics and Design, 2001, ISLPED, pp.195-200, 2001. Dong-Ik Jeon is received his B.S. in Electronics & Communication Engineering from Hanyang University, Ansan, Korea in 2012, and he is currently working toward a Ph.D. in Electronics and Computer Engineering from Hanyang University, Seoul, Korea. His research interests include the memory controller, DRAM memory architecture, and hybrid memory cube (HMC). Kwang-Soo Han is received his B.S. in Media Communication Engineering in 2011, and MS in Electronics and Computer Engineering from Hanyang University, Seoul, Korea in 2013. He is currently working toward a Ph.D. degree in Electronics and Computer Engineering from University of California, San Diego, United States. His interest research includes VLSI design, and embedded multi-core architecture. REFERENCES [1] Ariantha P. Chandrakasan, et al, Minimizing Consumption in Digital CMOS Circuits, Proceedings of the IEEE, Vol.83, pp.498-523, 1995. [2] Sarvesh H. Kulkarni, et al, Distribution

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.5, OCTOBER, 2017 583 Ki-Seok Chung is received his B.S. in Computer Engineering from Seoul National University, Seoul, Korea in 1989, and Ph.D. in Computer Science from University of Illinois at Urbana-Champaign in 1998. He was a Senior R&D Engineer at Synopsys, Inc. in Mountain View, CA from 1998 to 2000, and was a Staff Engineer at Intel Corp. in Santa Clara, CA from 2000 to 2001. He also worked as an Assistant Professor at Hongik University, Seoul, Korea from 2001 to 2004. Currently, he is a Professor at Hanyang University, Seoul, Korea. His research interests include low power embedded system design, multi-core architecture, image processing, reconfigurable processor and DSP design, SoC-platform based verification and system software for MPSoC.