ECE1756, Experiment 02, 2015 Communications Lab, University of Toronto Exploring DSP Performance Bruno Korst, Siu Pak Mok & Vaughn Betz Abstract The performance of two DSP architectures will be probed using an FIR routine in C and assembly. Results obtained here will be used for a comparison with an FPGA platform. Keywords FPGA DSP Floating Point Fixed Point Assembly Optimization Code Composer Studio Contents Introduction 1 1 Equipment and Software Tools 2 2 Connecting the Target Hardware 2 2.1 Floating Point Target............................................................... 2 2.2 Fixed Point Target................................................................. 2 3 Running Programs on the Target Hardware 2 3.1 FIR Filter Program................................................................. 3 4 Conclusion 5 References 5 Introduction In this experiment, you will run a given digital filtering program on two DSP platforms, in order to assess its performance and to compare it with a similar filter running on an FPGA. This is not an experiment on programming, nor it is an experiment on DSP. What is important here is to observe the difference in performance for a given code on different architectures, languages (i.e., C and assembly) and code optimization levels. You will be guided through the steps to make the program run, and will be required to identify and change parameters as needed. This outline pertains to the DSP portion of the experiment only; the FPGA portion is described in the companion handout in this.zip file. The DSP platforms utilized are a fixed point development board based on the TMS320C5505 processor and a development board based on a dual-core ARM/TMS320C6748 floating-point processor. Both are from Texas Instruments. These families of processors (the c5x and the c6x) are widely utilized in industry, and are suitable platforms for this experiment. The platforms have a stereo codec which operates for this experiment at a fixed sampling rate of 48KHz. Both channels will be utilized in the experiment. One signal path will go through a digital filter implemented in C and the other path will go through the same filter implemented in assembly. The sampling rate determines that a sample is taken every 10.4µs. The floating point DSP operates at 300 MHz, which gives 3.3 ns for every instruction cycle. Therefore, the maximum number of cycles available to process each sample under these conditions is 3151. The code utilized in this experiment is based on the C5000 Texas Instruments training material, prepared by Dr. Richard Sikora [1]. You will use a sinusoidal signal from an Arbitrary Signal Generator as an input and will monitor the output using an oscilloscope. It is assumed that you are familiar with these devices. You will also use Code Composer Studio v.6.1 (called CCS from here on) to monitor CPU cycles on particular routines. The programs will be opened from within CCS.
Exploring DSP Performance 2/5 1. Equipment and Software Tools The following list of equipment and software tools will be utilized in this experiment. Hardware: One Signal Generator; One Two-Channel Oscilloscope; One TI LCDK (ARM/TMS320C6748) floating-point development board; One TI TMS320C5505/TMS320VC5505 ezdsp fixed-point development board; Coaxial cables BNC-to-BNC and a T connector. Software: Code Composer Studio (CCS), v.6.1.0. 2. Connecting the Target Hardware You should start working with the floating-point platform first, and then move on to the fixed-point. 2.1 Floating Point Target The LCDK board is the PCB covered with thick plexiglass that has a power supply and a USB cable attached. It is the default platform for CCS, and is already connected to the workstation. Since the hardware is permanently on, all you have to do is to turn on the workstation, which will bring CCS up by default. The board has four BNC connectors. The two BNC connectors that have a resistor and capacitor attached to them are the output. Always connect both inputs and outputs. Inputs are connected to the Arbitrary signal generator, outputs to the scope. On the Arbitrary Signal Generator, select the Sine Wave as your signal and set it to 0.5V pp, 1KHz. Before turning the output on, ensure that the output impedance on the Arbitrary Signal Generator is set to High Z. This is found under the output setup on the Signal Generator. Now turn the output on. If you want, check whether you do have a signal at all connecting signal generator directly to scope. Do not forget to reconnect your input signal to the target hardware after you check if your input on. 2.2 Fixed Point Target You will use the fixed-point target after you use the floating-point one. If you try to plug the fixed-point platform with CCS open, there will be a conflict between the two platforms when you try to load your project onto the platform. Make sure to close CCS before connecting the fixed-point target. With CCS closed, plug in the board, connect the target hardware with a USB cable to the front panel of the workstation and open CCS. LEDs should be lighted up on the target. In addition to a male USB connector, to which the cable is connected, the hardware has four other connectors. Take a look at the labels on the PCB now and identify the two inputs and two outputs. If you want (you will be prompted again), connect the two inputs to the Arbitrary Signal Generator, and the two outputs to the two channels on the oscilloscope. Turn both devices on. The setup of the Arbitrary Signal Generator is the same as described above for the floating-point target. 3. Running Programs on the Target Hardware This section will describe the main steps to get the filtering program to run on the target platform. It is assumed that you are somewhat familiar with digital filtering, but some more details are given below. There are three CCS projects given to you: ECE1756 Floating Point, ECE1756 Fixed Point 5505 and ECE1756 Fixed Point VC5505. The two fixed-point projects are specific to which type of board you are using. The PCBs are labeled with the type C5505 or VC5505. Inspect your fixed-point hardware now to see which project you will run. As mentioned before, you should start with the floating-point hardware. Below are some details on the programs you will run: The projects are already configured for the respective platform (i.e., fixed point or floating point). The file which defines the target has the extension.ccxml. Please avoid changing these files;
Exploring DSP Performance 3/5 Always Compile/Rebuild the project. This will generate a.out file, which is your executable file; When you make any modifications, find the bug button on the CCS top, just under the menu, and click on it to recompile and reload the selected (active) project. When you make any changes, always click on the bug; Figure 1. The Bug Button When the compilation/building is done, CCS will switch to the debug view of the IDE. In order to run your program, you must press on the play button, which is a right-pointing green triangle found just below the menu items at the top of your window. With CCS open, click first on the project named ECE1756 Floating Point. This will highlight it and set it as active project. Explore the project, identifying where the FIR routines (C and assembly) are, and where the coefficients for the filter are found. You can expand the project tree and see the files comprising the project by clicking on the plus sign to the left of the project name. When a project is active, this means that the selected project is the one which will be compiled/built and loaded when you click on the bug. Be careful not to edit one project and compile another. It happens. Try to keep open only the files pertaining to the active project, so there won t be any mistakes. The IDE allows you to work on the debug view and an editing view, but you can actually edit code on either one of them. You just have to recompile afterwards (that means, click on the bug). After the program is compiled, built and loaded, you must place breakpoints at strategic places in the code that is ready to run. Breakpoints are placed by double clicking on the left column where the line numbers are displayed. The program you will run on the DSP platforms contains a long loop which polls samples from the A/D converter and puts them out to the D/A. There are two calls within this loop: one to an assembly function and one to a C function. Both of these implement an FIR (Finite Impulse Response) filter by means of a convolution. Specific details on how to run this program are given below. 3.1 FIR Filter Program The Low Pass FIR program uses coefficients generated using a Kaiser Window, designed for a 2KHz cutoff frequency. The sampling rate is 48KHz. The impulse response (or the coefficients ) for this filter are found in fir.cof, and are all represented in short format. You probably know that since this filter is a Low Pass, the coefficients should draw a sinc curve when plotted, as shown in Figure 2 below. Figure 2. Time Doman impulse response (sinc function), Low Pass Filter, Kaiser Window, 2 khz Cutoff, 48 khz sampling Freq. Note two things. First, the time domain plot on Figure 2 shows a truncated sinc function, represented by 51 coefficients. The fact that we are aiming at a 2KHz cutoff while using a 48KHz sampling rate, and using only 51 coefficients (i.e. order 50),
Exploring DSP Performance 4/5 Figure 3. Frequency Response, Low Pass Filter, Kaiser Window, 2 khz Cutoff, 48 khz sampling Freq. limits the extent to which the sinc function will be represented in the plot. Should we use a higher cutoff frequency, there would be more of the sinc represented here. Likewise, should we increase the order of our filter, we would achieve a sharper rolloff at 2KHz and, again, more of the sinc would be represented in the time domain. The numbers on the horizontal axis just represent the number of coefficients for Figure 2. Second, both vertical axes have strange-looking numbers. In the time domain (Figure 2), the coefficients are represented in fixed-point format, which explains the large values on the vertical axis. In the frequency domain (Figure 3), the values are the absolute values of the FFT performed on the coefficients. For the horizontal axis, if we consider that a 1024-point FFT was taken on a 48KHz sampled signal, it follows that point number 32 represents 1.5KHz. The filter was designed for a 2KHz cutoff. Check if the plot makes sense. Now turn your attention to the program main.c. You should see that the same filter is run twice; once for each output channel. For one channel it is run using the routine called in assembly and for the other it runs the routine in C. Note that since the channels are selected in software, it makes no sense to talk about which one is left or right; this can be changed in code. Your objective is to compare the performance in terms of cycles between these two routines, for different types of release and for different optimization levels of the compiler. You must set breakpoints to achieve this. Before you start setting them up, make sure the program compiles, loads and runs by clicking on the bug button. Test the program to see if it is doing what it should when it runs, i.e., it is a low pass filter with a 2KHz cutoff. Vary the input sinusoidal signal in frequency to observe a decay on the amplitude of the output occurring around 2KHz, and fill in the table below. You can find out the peak-to-peak voltage by pressing the Measure button on the oscilloscope. Having made sure it runs, open the files where the filtering routines are located. You should be able to visualize both files. If your program is running, stop your program (click on the red square icon). Your target should be connected and the executable program loaded. It s a good idea to run it and pause it prior to doing this. You may note that the fixed-point platform presents an attenuation of about 0.5 across all frequencies if compared to the floating-point platform. This is due to the way the A/D converter is set up on the platform. Also, the output sine wave appears noisier on the fixed-point platform. This is due to the lack of an RC Lowpass filter after the D/A converter as the floating-point platform presents. Since the exercise is to measure the cutoff frequency, none of these items impact the work at hand. Record on the table below the values you find for the output voltage at different frequency values. Frequency 1.0 khz 1.5 khz 2.0 khz 2.5 khz V out (C5x) V out (C6x) Pause execution of the FIR filter, using the pause button. Now you will set breakpoints so you can time the C and assembly versions of the FIR filter. The breakpoints are set by double clicking beside the line number on the leftmost column of the editor. Be sure to set the breakpoints at a reasonable place, so that the comparison will be meaningful. Before starting program execution, and while still within the CCS Debug, select Run -- Clock -- Enable. At the bottom of the IDE window you should see a little clock appearing. This is where your cycle reading will be done. When you click Play (green arrow), the program will run until a breakpoint and the cycle count will be displayed beside the little clock. If you double-click on the clock, the cycle count will be reset. You should reset the clock prior to pressing Play. So far you have been running the debug version of the program, with no compiler optimizations. To test the effect of compiler optimizations you will choose different optimization levels. The options are found under Project -- Properties. A new window will open. Under the Compiler, expand the menu and choose Optimization options, and set the
Exploring DSP Performance 5/5 Optimization to blank (no optimization) or level 2 as shown in Figure 4. Figure 4. Changing Optimization to level 2 Note that every time you change these parameters, you must rebuild your project. When you are done, record below the values you found. Feel free to run many times to see what happens. Assembly C no opt. C opt -o2 C5x Debug C6x Debug 4. Conclusion The experiment today lead you to explore the performance of a Digital Signal Processor when performing a filtering function. You have explored two implementations in C and in assembly and compared them in terms of cycles. In a future experiment, you will do the same for an FPGA platform, and hopefully you will draw conclusions as to the pros and cons of each type of architecture. References [1] R. Sikora. C5000 Teaching Material CD. Texas Instruments, 2009.