Power MOSFET IRFP27N60K, SiHFP27N60K PRODUCT SUMMRY V DS (V) 600 R DS(on) ( ) V GS = V 8 Q g (Max.) (nc) 80 Q gs (nc) 56 Q gd (nc) 86 Configuration Single TO-27C S G D ORDERING INFORMTION Package Lead (Pb)-free SnPb G D S N-Channel MOSFET FETURES Low Gate Charge Q g Results in Simple Drive Requirement Improved Gate, valanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and valanche Voltage and Current Enhanced Body Diode dv/dt Capability Compliant to RoHS Directive 2002/95/EC PPLICTIONS Hard Switching Primary or PFC Switch Switch Mode Power Supply (SMPS) Uninterruptible Power Supply High Speed Power Switching Motor Drive TO-27C IRFP27N60KPbF SiHFP27N60K-E3 IRFP27N60K SiHFP27N60K vailable RoHS* COMPLINT BSOLUTE MXIMUM RTINGS (T C = 25 C, unless otherwise noted) PRMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 600 V Gate-Source Voltage V GS ± 30 Continuous Drain Current V GS at V T C = 25 C 27 I D T C = 0 C 8 Pulsed Drain Current a I DM Linear Derating Factor.0 W/ C Single Pulse valanche Energy b E S 530 mj Repetitive valanche Current a I R 27 Repetitive valanche Energy a E R 50 mj Maximum Power Dissipation T C = 25 C P D 500 W Peak Diode Recovery dv/dt c dv/dt 3 V/ns Operating Junction and Storage Temperature Range T J, T stg - 55 to 50 Soldering Recommendations (Peak Temperature) for s 300 d C Mounting Torque 6-32 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Starting T J = 25 C, L =. mh, R g = 25, I S = 27, dv/dt = 3 V/ns (see fig. 2). c. I SD 27, di/dt 390 /μs, V DD V DS, T J 50 C. d..6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply lbf in. N m Document Number: 929 www.vishay.com S-087-Rev. C, 2-Mar- THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
IRFP27N60K, SiHFP27N60K THERML RESISTNCE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junction-to-mbient R thj - 0 Case-to-Sink, Flat, Greased Surface R thcs 0.2 - C/W Maximum Junction-to-Case (Drain) R thjc - 0.29 SPECIFICTIONS (T J = 25 C, unless otherwise noted) PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static Drain-Source Breakdown Voltage V DS V GS = 0 V, I D = 250 μ 600 - - V V DS Temperature Coefficient V DS /T J Reference to 25 C, I D = m - 60 - mv/ C Gate-Source Threshold Voltage V GS(th) V DS = V GS, I D = 250 μ 3.0-5.0 V Gate-Source Leakage I GSS V GS = ± 30 V - - ± 0 n V DS = 600 V, V GS = 0 V - - 50 Zero Gate Voltage Drain Current I DSS V DS = 80 V, V GS = 0 V, T J = 25 C - - 250 μ Drain-Source On-State Resistance R DS(on) V GS = V I D = 6 b - 8 0.22 Forward Transconductance g fs V DS = 50 V, I D = 6 - - S Dynamic Input Capacitance C iss V GS = 0 V - 660 - Output Capacitance C oss V DS = 25 V - 60 - Reverse Transfer Capacitance C rss f =.0 MHz, see fig. 5 - - pf V GS = 0 V V DS =.0 V, f =.0 MHz - 590 - Output Capacitance C oss V GS = 0 V V DS = 80 V, f =.0 MHz - 20 - Effective Output Capacitance C oss eff. V GS = 0 V V DS = 0 V to 80 V - 250 - Total Gate Charge Q g - - 80 I D = 27, V DS = 80 V Gate-Source Charge Q gs V GS = V - - 56 nc see fig. 6 and 3 b Gate-Drain Charge Q gd - - 86 Turn-On Delay Time t d(on) - 27 - Rise Time t r V DD = 300 V, I D = 27 - - Turn-Off Delay Time t d(off) R g =.3, V GS = V, see fig. b - 3 - ns Fall Time t f - 38 - Drain-Source Body Diode Characteristics D Continuous Source-Drain Diode Current I S MOSFET symbol - - 27 showing the G integral reverse Pulsed Diode Forward Current a I SM S p - n junction diode - - T b J Body Diode Voltage V SD T J = 25 C, I S = 27, V GS = 0 V b - -.5 V Body Diode Reverse Recovery Time t rr - 620 920 ns Body Diode Reverse Recovery Charge Q rr = 25 C, I F = 27, di/dt = 0 /μs - 6 μc Reverse Recovery Current I RRM - 36 53 Forward Turn-On Time t on Intrinsic turn-on time is negligible (turn-on is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Pulse width 300 μs; duty cycle 2 %. c. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 % to 80% V DS. www.vishay.com Document Number: 929 2 S-087-Rev. C, 2-Mar- THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
I D, Drain-to-Source Current () I D, Drain-to-Source Current () I D, Drain-to-Source Current (Α ) IRFP27N60K, SiHFP27N60K TYPICL CHRCTERISTICS (25 C, unless otherwise noted) 00 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 00.00 0.00.00 T J = 50 C 0.00 5.0V 20µs PULSE WIDTH Tj = 25 C 0 V DS, Drain-to-Source Voltage (V) Fig. - Typical Output Characteristics.00 T J = 25 C 0. V DS = 0V 20µs PULSE WIDTH 5.0 7.0 9.0.0 3.0 5.0 V GS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V 20µs PULSE WIDTH Tj = 50 C 0 V DS, Drain-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.5 I D = 28 3.0 2.5 2.0.5.0 0.5 V GS = V 0.0-60 -0-20 0 20 0 60 80 0 20 0 60 T J, Junction Temperature ( C) Fig. 2 - Typical Output Characteristics Fig. - Normalized On-Resistance vs. Temperature Document Number: 929 www.vishay.com S-087-Rev. C, 2-Mar- 3 THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
I D, Drain-to-Source Current () IRFP27N60K, SiHFP27N60K 0000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED 00 C rss = C gd C, Capacitance(pF) 000 00 0 C oss = C ds C gd Ciss Coss Crss I SD, Reverse Drain Current () 0 T J= 50 C T J= 25 C 0 00 V DS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage V GS= 0 V 0.2 0.5 0.8.. V SD,Source-to-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage V GS, Gate-to-Source Voltage (V) 2 7 5 2 I D = 28 V DS = 80V V DS = 300V V DS = 20V 0 0 30 60 90 20 50 Q G, Total Gate Charge (nc) 00 0 OPERTION IN THIS RE LIMITED BY R DS (on) 0µsec msec Tc = 25 C Tj = 50 C msec Single Pulse 0 00 000 V DS, Drain-toSource Voltage (V) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating rea www.vishay.com Document Number: 929 S-087-Rev. C, 2-Mar- THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
IRFP27N60K, SiHFP27N60K 30 V DS R D 25 R G V GS D.U.T. - V DD I D, Drain Current () 20 5 V Pulse width µs Duty factor % Fig. a - Switching Time Test Circuit 5 V DS 90 % 0 25 50 75 0 25 50 T C, Case Temperature ( C) % V GS t d(on) t r t d(off) t f Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. b - Switching Time Waveforms Thermal Response (Z thjc ) D = 0.50 0.20 0. 0.05 0.02 SINGLE PULSE (THERML RESPONSE) P DM t t 2 Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc T C 0.00 0.0000 0.000 0.00 t, Rectangular Pulse Duration (s) Fig. - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 929 www.vishay.com S-087-Rev. C, 2-Mar- 5 THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
IRFP27N60K, SiHFP27N60K V DS 5 V t p V DS L Driver R G D.U.T - V DD I S 20 V I t p Ω S Fig. 2a - Unclamped Inductive Test Circuit Fig. 2b - Unclamped Inductive Waveforms 950 760 TOP BOTTOM I D 3 8 28 E S, Single Pulse valanche Energy (mj) 570 380 90 0 25 50 75 0 25 50 Starting Tj, Junction Temperature ( C) Fig. 2c - Maximum valanche Energy vs. Drain Current Current regulator Same type as D.U.T. Q G 50 kω V GS 2 V 0.2 µf 0.3 µf Q GS Q GD D.U.T. V - DS V G V GS Charge Fig. 3a - Basic Gate Charge Waveform 3 m Fig. 3b - Gate Charge Test Circuit I G I D Current sampling resistors www.vishay.com Document Number: 929 6 S-087-Rev. C, 2-Mar- THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
IRFP27N60K, SiHFP27N60K Peak Diode Recovery dv/dt Test Circuit D.U.T. - Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer - - R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. - device under test - V DD Driver gate drive P.W. Period D = P.W. Period V GS = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. V DS waveform Diode recovery dv/dt V DD Re-applied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. - For N-Channel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?929. Document Number: 929 www.vishay.com S-087-Rev. C, 2-Mar- 7 THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
www.vishay.com TO-27C (High Voltage) Package Information 3 B R/2 Q E E/2 S 2 7 ØP (Datum B) Ø k M D B M ØP D2 2 x R (2) D D 2 3 D Thermal pad 5 L C 2 x b2 3 x b 0. M C M b Lead ssignments. Gate 2. Drain 3. Source. Drain 2 x e L See view B C DDE (b, b2, b) () Section C - C, D - D, E - E MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX..58 5.3 80 0.209 D2 0.5.30 0.020 0.05 2.2 2.59 0.087 0.2 E 5.29 5.87 0.602 0.625 2.7 2.9 0.06 0.098 E 3.72-0.50 - b 0.99.0 0.039 0.055 e 5.6 BSC 0.25 BSC b 0.99.35 0.039 0.053 Ø k 0.25 0.0 b2.53 2.39 0.060 0.09 L.20 6.25 0.559 0.60 b3.65 2.37 0.065 0.093 L 3.7.29 6 69 b 2.2 3.3 0.095 35 N 7.62 BSC 0.300 BSC b5 2.59 3.38 0.2 33 Ø P 3.5 3.66 38 c 0.38 0.86 5 0.03 Ø P - 7.39-0.29 c 0.38 0.76 5 0.030 Q 5.3 5.69 0.209 0.22 D 9.7 20.82 0.776 0.820 R.52 5.9 78 0.26 D 3.08-0.55 - S 5.5 BSC 0.27 BSC ECN: X3-03-Rev. D, 0-Jul-3 DWG: 597 Notes. Dimensioning and tolerancing per SME Y.5M-99. 2. Contour of slot optional. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 27 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body.. Thermal pad contour optional with dimensions D and E. 5. Lead finish uncontrolled in L. 6. Ø P to have a maximum draft angle of.5 to the top of the part with a maximum hole diameter of 3.9 mm (5"). 7. Outline conforms to JEDEC outline TO-27 with exception of dimension c. 8. Xian and Mingxin actually photo. E View B C C Planting (c) E M D B M View - (b, b3, b5) Base metal c Revision: 0-Jul-3 Document Number: 9360 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
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