A Seres Connected Three-Level Inverter Topology For Medum Voltage Squrrel Cage Motor Drve Applcatons Suvajt Mukherjee Electrcal Engneerng Department Indan Insttute of Technology Kharagpur, Inda m_suvajt@yahoo.com Gautam Poddar Electrcal Engneerng Department Indan Insttute of Technology Kharagpur, Inda gpoddar@ee.tkgp.ernet.n Abstract The applcaton of PWM voltages usng two level hgh voltage nverters to a squrrel cage nducton motor (SQIM) can cause hgh bearng currents, heatng of rotor shaft, voltage spke across the motor termnals, etc. The ncrease n the number of steps of the motor voltage and hence decreasng the dv/dt appled to the machne termnals can be a soluton to ths problem. The exstng topologes that generate ths mult-step voltage nclude cascadng of a number of sngle-phase nverters or use of hgher order mult-level nverters. In ths paper a topology wth seres connecton of three phase three-level nverters s proposed that addresses the problems of medum voltage drves. The desgn of the nverter topology and ts varous PWM technques are presented n the paper. Ths nverter topology and ts control are verfed on a 7.5 hp squrrel cage nducton motor (SQIM) drve. Expermental results valdate the steady-state and dynamc performances of the drve. Keywords- Medum voltage ac drves, Mult-level converter topologes NOMENCLATURE L s, L r Stator and rotor self nductances referred to the stator L 0 Magnetzng nductance σ s, σ r Stator and rotor leakage factors σ Total leakage factor R s, R r Stator and rotor resstances referred to stator P Number of poles of the motor V, V d-axs and q-axs stator voltages sq Vrd, Vrq d-axs and q-axs rotor voltages ε Angle between stator and rotor axes ρmr, ρ r Rotor flux angle wth respect to stator and rotor axs ψ, ψ α-β axs rotor flux n statonary reference frame rsα rsβ I. INTRODUCTION In normal squrrel cage nducton motor (SQIM) drve, the motor normally s fed wth pulse wdth modulated (PWM) voltages whch cause hgh bearng currents (due to dv/dt) and heatng of rotor shaft [1, 14]. In certan applcatons, shaft voltages [1] can cause drect damage, e.g., sparks n a hazardous envronment, and are very undesrable. Ths s a matter of bg concern for varable speed medum voltage drves where the voltage levels are very hgh. The above problem can be resolved by applyng varable voltage wth low dv/dt. By ncreasng the number of steps of the motor voltage lke multcell technologes [2, 3], the gravty of ths problem can be reduced. The proposed topology of seres connected threelevel nverters ncreases the number of steps n the appled voltage and hence decreasng the dv/dt appled to the machne termnals. Smlar voltage profles can also be obtaned by usng hgher order neutral pont clamped (NPC) mult-level nverters [4, 5] or by cascadng a number of two level nverters [2, 3]. But, the mult-level NPC nverters suffer from dc bus mbalance [11-13], devce underutlzaton problems and unequal ratngs of the clamped dodes, etc [5, 6] whch are not so serous problems for the nverters wth three-level or below. The capactor voltage mbalance for fve-level are presented n [11-13] whch suggest the need of extra hardware n the form of dc choppers or a back to back connecton of multlevel converters. The cascaded H-brdge topology [2-4] suffers from the drawbacks of usage of huge dc bus capactors and complex nput transformers for solated dc bus for each module. These drawbacks are addressed n the proposed topology. Furthermore, the power crcut s modular n structure and hence the number of modules to be connected n seres depends on the power of the drve. In ths paper, the proposed topology and ts varous PWM control strateges are expermentally valdated on a vector controlled squrrel cage nducton motor drve [8-10]. It has two three-level nverters connected n seres and drves the motor. II. POWER CONVERTER TOPOLOGY The proposed general confguraton of n number of threelevel nverters connected n seres s shown n fgure 1. Each nverter module s a three-phase neutral pont clamped (NPC) three-level nverter. At the output stage, transformers are used to have the seres connecton of three-level nverters as shown n fgure 1. If V dc s the dc bus voltage of each nverter module, α s the turns rato of each transformer, and n s the 978-1-4244-2279-1/08/$25.00 2008 IEEE 1
number of nverter modules then for sne PWM strategy, the motor rms phase voltage ( V Ph _ motor ) can be expressed as follows. rms of VPh _ motor = Vdc 3α mn 2 2 (1) where m s the modulaton ndex of the nverter topology defned as follows. peak of Vph_ nverter m V dc n 2 Vph _ nverter s the total phase voltage reference of the nverter topology. For gven peak of V Ph _ motor, peak of V can be computed as below. ph _ nverter peak of Vph _ motor peak of Vph _ nverter = (3) 3α The generaton of ndvdual reference voltage sgnal of each nverter s dscussed as follows. The gate pulses for each three-level nverter module can be derved usng two carrer sgnals. Thus, n numbers of such three-level nverter modules requre 2n number of carrers [6, 7]. The three-phase voltage reference sgnals are then compared wth these carrer waves to produce the gate pulses for the nverters. For example, the carrer waves and the snusodal modulatng voltage sgnal (SPWM technque) for R- phase s shown n fgure 2 for 4 numbers of seres connected three-level nverters. The carrer waves 1 and 1 / (fgure 2) wth R-phase voltage reference controls the nverter module 1. Smlarly, 2-2 /, 3-3 /, and 4-4 / carrer waves wth R-phase voltage reference generate the gate pulses for the three-level nverter modules 2, 3, and 4 respectvely. Thus each nverter module produces the voltage proportonal to a part of the reference phase voltage sgnals. It s mportant to note that no two three-level nverter modules swtch smultaneously (fgure 2). Thus, the maxmum dv/dt rate of the output voltage of ths topology s lmted to that of a sngle three-level nverter module (fgure 5). The references of each nverter are shown n fgure 3. The correspondng output lne voltages of each nverter are shown n fgure 4. The four wndngs, one from each transformer, are connected n seres and produced the net R-phase voltage as shown n fgure 5. Smlarly, the other two phase voltages are generated. The lne voltage spectrums of ndvdual nverters are presented n fgure 4 for swtchng frequency of 2.5 khz. These lne voltages get added to produce the net phase voltage of the topology. The voltage spectrums are expressed as a percentage of the maxmum total fundamental ( V peak ) that can be produced by the topology. Input Transformer Rectfer DC Bus 3-level Module 1 Output Transformer SQIM Rectfer DC Bus 3-level Module 2 Rectfer DC Bus 3-level Module n Fg.1. Block dagram of three phase three-level nverter modules connected n seres drvng a SQIM 2
V = 2 V (4) peak Ph _ motor or, V = 2078.5 V for V dc = 600 V, n = 4, α = 1 and m peak = 1 usng equaton (1). Hence the spectrums show the percentage share of the fundamental of each nverter module. These spectrums also suggest that the lne voltages of all these nverters contan addtonal small amount of 5 th, 7 th, 11 th, 13 th, and hgher order harmoncs bees the normal swtchng harmoncs. However, the net phase voltage and lne voltage of ths topology do not contan any of these harmoncs as suggested by the spectrums shown n fgure 5. These harmoncs get canceled when the lne voltages of the ndvdual nverters are added by the transformers to produce the net phase voltages. Fg.2. The carrer waves and the snusodal modulatng voltage sgnal for R-phase n sne PWM (SPWM) technque Fg.4. Smulated lne voltage and harmonc spectrum of nverter 1, nverter 2, nverter 3 and nverter 4 when four nverters are connected n seres wth sne PWM technque for V dc = 600V, α = 1 and m = 1 Fg.3. Generaton of modulatng voltage sgnal for R- phase of each of the four nverters n seres for sne PWM strategy Fg.5. Smulated phase voltage when four nverters are connected n seres wth sne PWM technque for f sw = 2.5 khz, V dc = 600 V, α = 1 and m = 1 3
III. DESIGN OF INVERTER MODULES The general confguraton of a sensorless squrrel cage nducton motor drve wth n number of 3-phase voltage source modules connected n seres s shown n fgure 1. Each voltage source module conssts of a three-phase dode rectfer, a dc bus, a three-phase three-level NPC nverter and a three-phase transformer. In ths secton, desgn gudelnes are presented for each module to drve a motor of voltage and current ratngs V s and I s respectvely. A. Desgn of transformer and nverter for each module The prmary e of each 3-phase transformer s chosen as delta connected whle the secondary e s kept open for the seres connecton between the modules. Normally, the dc bus voltage (V dc ) of each module s chosen such that the standard IGBT module (say, 1400V IGBT, 300A) can be used. Smlarly, the current ratng (I nv ) of each nverter module s chosen. Now, the current requred on the motor e of the transformer s I s. Then the current drawn from the nverter s Is α 3 and must be equal to I nv. Here, α s the transformer turns rato defned as follows. number of transformer phaseturns onthe motor e α = number of transformer phaseturns onthe nverter e (5) Thus, the turns rato of the transformer (α ) s obtaned as below. Inv α = (6) 3 Is For n number of modules, the maxmum lne n voltage, ths topology can produce, s 3 V α dc 2 assumng space vector PWM strategy. Ths voltage must match the requred motor lne voltage V s. Thus, the number of modules n can be selected as below. 2 Vs 2 Vs Is n = = (7) 3 α V Vdc I dc nv At maxmum modulaton ndex n the lnear modulaton zone, all the modules share the net fundamental output voltages almost equally. Addtonally, all the modules also have some amount of 5 th, 7 th, and hgher order voltage harmoncs bees very small amount of swtchng harmoncs. These voltage harmoncs must be taken care of whle desgnng the standard transformer for each module. However, all the module currents and hence the transformer currents reman almost snusodal. B. Selecton of DC Bus Capactor for Each Module In sngle phase nverters the dc bus carres second harmonc currents n addton to the swtchng currents. So the sze of the capactors ncreases when sngle phase nverters are used n cascaded H-brdge topology [2]. Snce the proposed drve has three-phase nverter at the output stage the low frequency (second harmonc) rpple n the capactor wll not be present. So, the sze of the capactor wll be relatvely small n the case of the proposed topology. IV. SQIM DRIVE USING PROPOSED CONVERTER The general confguraton of a sensorless squrrel cage nducton motor drve wth n number of neutral pont clamped (NPC) three-level nverter s shown n fgure 1. All the three-level nverters, connected n seres, drve the motor and share the load. A. Rotor-Flux Orented Squrrel Cage Inducton Motor In ths topology the stator leakage nductance value has to be modfed to ncorporate the leakage nductance of the output transformers ( L lt ). Also the effectve stator resstance changes due to the presence of transformer wndng resstances ( R lt ). By neglectng the magnetzng branch of the nverter transformer, the equvalent crcut of the transformer s a smple R-L crcut as shown n fgure 6. Thus the modfed values of the stator leakages are as follows. / Ls = σls + LlT / s = s + lt σ (8) R R R Hence the modfed dynamcal equatons of the SQIM voltages and currents n d-q plane are presented as follows. / / d / 1 dψ r V = Rs + σls σlsωmrsq + (9) dt (1 + σ ) dt d ψω V = R + L + L + (10) (1 + ) / / sq / r mr sq s sq σ s σ sωmr dt σ r Here, the d-axs s algned wth the rotor flux vector ( ψ r ) [10, 16]. The rotor flux vector n statonary coordnates ( ψ rs ) s expressed n terms of stator flux as Lr ψrs = { ψs σlss} (11) L0 The stator flux ψ s s estmated from stator voltage V s as below. ψ s = ( Vs Rss ωcψ s) (12) The problem ntegraton at low frequency s tackled by replacng the pure ntegraton of stator voltage wth a lowpass flter (cut-off frequency = ω ) [10, 15]. B. Motor Controller The d-axs and the q-axs motor voltage equatons (9) and (10) show the frst-order dynamcs of the stator currents ( and sq ) f the underlned terms are decoupled. So, smple PI-controllers wth unty feedback system can control the d-q axs motor currents to control the flux and the torque of the motor as shown n fgure 7. By choosng the proper gan values of the PI controllers, the desred c r 4
bandwdth ( 1 τ m ) of the motor current controller s acheved [10]. Thus, the closed loop transfer functons of and sq become as follows. ( s) 1 sq ( s) 1 = and = (13) ( ) 1 s m ( ) 1 s s + τ sq s + τm In the present work, the desred response tme τ m of the motor current s chosen as 4 msec. Fnally, the outputs of the PI controllers are added to the underlned couplng terms of (9) and (10) to get the actual d-axs and the q-axs voltage references ( V, Vsq) [10]. It s mportant to note that the motor phase voltages and the nverter phase voltages are not n phase. The motor phase voltage s n phase wth the lne voltages of the nverter modules. Hence a phase shft of 30 o s provded to the three motor phase voltage references obtaned to generate the three nverter phase voltage references. The phase reference obtaned s the total phase reference of the topology. Hence ths reference s obtaned by addng the reference of the ndvdual nverter modules. Fgures 8 and 9 show the ndvdual nverter lne voltages that are beng added up. The voltage references for ndvdual converters n bus clamp technque are shown n fgure 10. Fgure 11 shows the nverter phase voltage references wth carrer based PWM wth thrd harmonc njecton technque and also wth centered space vector PWM technque [7]. The phase voltage waveform along wth ts spectrum analyss s shown n fgure 12. It confrms stepped voltage waveform and low dv/dt that s appled to the motor. Fgure 13 shows the steady state motor lne voltage and motor current. Fgure 14 shows the varaton of motor phase voltage and motor speed for a step change n torque command. Fgure 15 shows the response of the torque current ( sq ) for a step change n torque current command ( sq ). Ths fgure suggests that the sq has a response tme constant 4 ms as per desgnng. 200 V/dv Rlp L lp Rls L ls neglected L = L + L R = R + R lt lp ls lt lp ls Fg.6. Equvalent crcut of a sngle phase transformer wth 1:1 turns rato 4 ms/dv Fg.8. Expermental waveform of steady state nverter1 lne voltage sq, + - K Pm K + s m V V sq, R 1 / / s +σ Ls sq, 200 V/dv Fg.7. d-axs and q-axs motor current controller V. EXPERIMENTAL RESULTS The expermental verfcaton s carred out on a 7.5-hp squrrel-cage nducton motor. The nverters used for ths drve are three-phase 5 KVA three-level dode clamped nverters. Two nverters are used to demonstrate the control strategy as dscussed above. The swtchng frequency of the ndvdual nverter s 5 khz. The complete control strategy s mplemented on a dgtal controller. 4 ms/dv Fg.9. Expermental waveform of steady state nverter 2 lne voltage 5
Inverter 2 ref. 2V/dv Fundamental 200V/dv 4ms/dv 35 V/dv 1.56 khz/dv Inverter 1 ref. 4ms/dv (a) Fg.10. Expermental waveform of nverter references n bus clamp technque 200 V/dv 4 ms/dv 2 V/dv 3.13 khz/dv (b) Fg.12. (a) Expermental waveform of steady state motor phase voltage ( V s1 ) and ts spectral analyss showng the relatve magntude of fundamental and harmoncs; (b) Zoomed harmonc spectrum (f sw = 5 khz) (a) 4 ms/dv Voltage 200 V/dv Current 10 A/dv (b) Fg.13. Expermental waveform of steady state motor current ( s1) and motor lne voltage Fg.11. Expermental waveform of nverter reference wth (a) carrer based PWM wth thrd harmonc njecton technque; (b) centered space vector PWM technque 6
200V/dv 4ms/dv Speed 1dv = 0.75p.u. applcaton n the frequency range near 8Hz to 50Hz due to the problems of sensorless control n low frequency operatons and also due to the problems of low frequency operaton of a standard transformer. Dfferent PWM strateges are used for ths nverter control. Usng the feed forward control strategy for the motor, a frst order response s acheved for the motor currents wth a tme constant of 4 msec. The motor termnal voltage shows a number of steps at dfferent operatng condtons. So, the lfe of the motor s also expected to be very hgh due to the low appled dv/dt. The modularty of the proposed drve gves flexblty n dfferent hgh power applcatons. If one module of the topology fals, the nverter can operate at reduced power level smlar to the sngle phase H-brdge topology [2]. Fg.14. Motor phase voltage durng speed transent Fg.15. Torque current ( sq ) for step change n torque current command ( sq ) VI. sq CONCLUSION 1 p.u. 0 p.u. 1 p.u. 0 p.u. A seres connecton of three-level nverters s proposed for medum voltage sensorless vector control SQIM drve wth ncreased voltage capacty. The topology ensures hgh power operatons wth medum voltage output havng several voltage levels. The reducton n the ratngs of dc bus capactor and reduced mbalance problems n the dc bus [11-13] are some of the advantages of the proposed topology over the exstng topologes. The dsadvantage of the proposed topology s that t requres addtonal output transformers whch ntroduce addtonal cost and losses. However, these transformers do not have complex underutlzed wndngs lke that requred n cascaded H- brdge topologes [2-4]. A scaled down (10 kva) laboratory proto-model of ths nverter s developed for vector controlled SQIM drve applcaton. The topology s tested for SQIM drve sq APPENDIX Motor Parameters: Rated power 7.5 hp; Rated frequency 50Hz; Rated speed 1435rpm; Number of pole 4; Stator lne voltage 415V; Rated lne current 10.8A; R s = 1.3Ω ; R r = 0.476Ω ; L0 = 0.1310H ; σ s = 0.0396H ; σ r = 0.0396H ; REFERENCES [1] Fe Wang, Motor Shaft Voltages and Bearng Currents and ther Reducton n Multlevel Medum- Voltage PWM Voltage-Source-Inverter Drve Applcatons, IEEE Transactons on Industry Applcatons, Vol.36, No. 5, September/October 2000, pp. 1336-1341. [2] P.W. Hammond, A New Approach to Enhanced Power Qualty for Medum Voltage Drves, IEEE Transactons on Industry Applcatons, Vol.33, No.1, January/February 1997, pp.202-208. [3] R. Teodorescu, F. Blaabjerg, J.K. Pederson, E. Cengelc, P.N. Enjet, Multlevel Inverter by Cascadng Industral VSI, IEEE Trans. on Industral Electroncs, vol.49, no. 4, pp. 832-838 August 2002. [4] Akra Nabae, Isao Takahash and Hrofum Akag, A new neutral pont clamped nverter, IEEE Trans. on Industry Applcatons, vol.17, no.5, Sept/Oct.1981, pp. 518-523. [5] Jh-Sheng La and Fang Zheng Peng, Multlevel converters - a new breed of power converters, IEEE Transactons on Industry Applcatons, Vol. 32, No. 3, pp. 509 517, May/June 1996. [6] G. Cararra, S. Gardella, M. Marcheson, R. Salutar, and G. Scutto, A new multlevel PWM method: A 7
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