NOT REOMMENDED FOR NEW DESIGNS REOMMENDED REPLAEMENT PART ISL Data Sheet 2V, W Quad SPST Switch with Latched Parallel Interface DATASHEET FN92 Rev The ISL32 is a quad analog bidirectional switch device targeted at industrial applications, including test and measurement equipment. It features low resistance and low leakage along with 2V operation and can be digitally controlled via a latched parallel interface. This parallel interface features a latch input pin that can be used to connect multiple devices into a parallel arrangement. The ISL32 can operate from a single, or split bipolar power supply and has a 3V logic interface. The ISL32 is specified for use over the - to +8 temperature range and is available in a 2 Ld x QFN Pb-free package. Table summarizes the performance of this family. ONFIGURATION Pinout TABLE. FEATURES AT A GLANE ISL32 (2 LD QFN) TOP VIEW QUAD SPST r ON t ON /t OFF Package 2B 2A 2 N VDD VLOGI 2ns/8ns 2 Ld QFN x VPLUS 2 9 8 7 3A 3B Features independently controlled SPST switches ON-resistance @ 2V........................... Single or split supply voltage operation r ON flatness.................................... < r ON matching between channels................. <.2 Turn-on/Turn-off time....................... 2ns/8ns Switch bandwidth............................ MHz Parallel data interface up to MHz 3V logic interface 2 Ld QFN package Pb-free (RoHS compliant) Related Literature TB33 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) TB389 PB Land Pattern and Surface Mount Guidelines for QFN Packages AN7 Recommended Test Procedures for Analog Switches Ordering Information PART NUMBER (Note) PART MARKING TEMP. RANGE ( ) PAKAGE (Pb-free) PKG. DWG. # ISL32IRZ* 32IRZ - to +8 2 Ld x QFN L2.x B A S-LATH 3 7 8 9 S-TRL S2-TRL S3-TRL S-TRL 3 2 A B N *Add -T for tape and reel. Please refer to TB37 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-2. ISL32 Block Diagram VLOGI S-TRL S2-TRL S3-TRL S-TRL LATHES VDD LEVEL SHIFTER VPLUS OF SW-A SW-B S-LATH FN92 Rev Page of
Pin Descriptions PIN NUMBER PIN NAME PIN DESRIPTION 2B Switch 2 signal terminal 2 2A Switch 2 signal terminal 3 B Switch signal terminal A Switch signal terminal S-LATH hip Select input S-TRL Switch one logic control 7 S2-TRL Switch two logic control 8 Device ground terminal 9 S3-TRL Switch three logic control S-TRL Switch four logic control N Not internally connected 2 B Switch signal terminal 3 A Switch signal terminal 3B Switch 3 signal terminal 3A Switch 3 signal terminal VPLUS Positive analog power supply 7 VLOGI Logic supply voltage 8 VDD Level shifter supply voltage 9 Negative analog power supply 2 N Not internally connected FN92 Rev Page 2 of
Absolute Maximum Ratings VPLUS to................................ -.3V tov VDD to.................................. -.3V to V VLOGI to.............................. -.3V to V to.................................. -V to.3v VPLUS to.............................. -.3V to V All Other Pins (Note )........ (() -.3V) to ((VPLUS) +.3V) ontinuous urrent (Any Terminal)..................... 3mA Peak urrent, A-A,B-B (Pulsed ms, % Duty ycle, Max)................. ma ESD Rating Human Body Model................................>3kV DM.......................................... >kv Machine Model....................................3V Thermal Information Thermal Resistance (Typical) JA ( /W) J ( /W) 2 Ld QFN Package (Notes 2, 3)...... 32. Maximum Junction Temperature (Plastic Package)........ + Maximum Storage Temperature Range............ - to + Pb-free reflow profile..........................see link below http://www.intersil.com/pbfree/pb-freereflow.asp Operating onditions Analog Switch Signal Range........ + V to VPLUS - V Temperature Range..........................- to +8 AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES:. Signals on A-A,B-B, exceeding VPLUS or are clamped by internal diodes. DATA_IN, LOK_IN, S_LATH exceeding VLOGI or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB379. 3. For J, the case temp location is the center of the exposed metal pad on the package underside. Electrical Specifications Test onditions: VPLUS = +9V, = -3V Supply, VLOGI = 3V, VDD = = V, V INH = 2.2V, V INL =.8V, Unless Otherwise Specified. PARAMETER TEST ONDITIONS TEMP ( ) MIN (Note 9) TYP (Note ) MAX (Note 9) UNITS ANALOG SWITH HARATERISTIS ON-resistance, r ON r ON Matching Between hannels, r ON r ON Flatness, r FLAT(ON) I OM = ma, VXA, VXB within analog signal (see Figure ) I OM = ma, VXA, VXB within analog signal range (Note ) I OM = ma, VXA, VXB within analog signal range (Note ) 2 Full 2.2 Full.3 2. Full. OFF Leakage urrent, I NO(OFF) VXA, VXB within analog signal range 2 na Full -2 +2 na DIGITAL INPUT HARATERISTIS (Note 8) Input Voltage High, Digital Interface SW-TRL(-), S_LATH Full 2.2.7 V Input Voltage Low, Digital Interface SW-TRL(-), S_LATH Full.7.8 V SW-TRL (-) Into S_Latch Setup Time SW-TRL (-) Into S_Latch Hold Time t SETUP (Note, Figure ) Full ns t HOLD (Note, Figure ) Full ns Input urrent, I INH, I INL V IN = V or VLOGI Full - µa S_LATH Rise, Fall Time % to 9% and 9% to % Full 3 ns S_LATH Minimum Pulse Width Rising to Falling Edge % Points Full ns SWITH DYNAMI HARATERISTIS Turn-ON Time, t ON VXA, VXB = 3V, R L = 3, L = 3pF, V IN = V to 3V, (see Figure ) 2 ns Full ns FN92 Rev Page 3 of
Electrical Specifications Test onditions: VPLUS = +9V, = -3V Supply, VLOGI = 3V, VDD = = V, V INH = 2.2V, V INL =.8V, Unless Otherwise Specified. (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) MIN (Note 9) TYP (Note ) MAX (Note 9) UNITS Turn-OFF Time, t OFF VXA, VXB = 3V, R L = 3, L = 3pF, V IN = V to 3V, (see Figure ) 2 9 ns Full 9 ns OFF apacitance, OFF f = MHz, VXA or VXB = V 2 pf ON apacitance, OM(ON) f = MHz, VXA or VXB = V 2 pf OFF Isolation R L =, L = pf, f = MHz, 2 - db rosstalk (Note ) VXA or VXB = V P-P (see Figure 3) 2 - db Switch ontact 3dB Bandwidth R L =, L = pf MHz harge Injection, Q L = nf, V G = V, R G = see Figure 2) 2 2 p POWER SUPPLY HARATERISTIS VPLUS Supply, I (Quiescent) 2 µa Full 7 µa VPLUS Supply, I (MHz) 2 8 µa Full 22 µa Supply, I (Quiescent) 2 µa Full 22 µa Supply, I (MHz) 2 ma Full ma VDD Supply, I (Quiescent) 2 µa Full µa VDD Supply, I (MHz) 2. ma Full. ma VLOGI Internal Logic Supply, I (Quiescent) VLOGI Internal Logic Supply, I (MHz) 2 µa Full µa 2 ma Full ma Electrical Specifications Test onditions: VPLUS = +7V, = V Supply, VLOGI= 3V, VDD = 3V, = V, V INH = 2.2V, V INL =.8V, Unless Otherwise Specified. PARAMETER TEST ONDITIONS ANALOG SWITH HARATERISTIS ON-resistance, r ON I OM = ma, VXA, VXB within Analog Signal Range (see Figure ) r ON Matching Between hannels, r ON I OM = ma, VXA, VXB within Analog Signal Range (Note ) TEMP ( ) MIN (Note 9) TYP (Note ) MAX (Note 9) UNITS 2 2.7 Full 2. Full. r ON Flatness, r FLAT(ON) I OM = ma, VXA, VXB within Analog Signal Range 2 (Note ) Full. OFF Leakage urrent, I NO(OFF) VXA = V, V, VXB= V, V 2 3 na Full -2 3 2 na DIGITAL INPUT HARATERISTIS (Note 8) Input Voltage High, Digital Interface SW-TRL(-), S_LATH Full 2.2.7 V Input Voltage Low, Digital Interface SW-TRL(-), S_LATH Full.7.8 V FN92 Rev Page of
Electrical Specifications PARAMETER Test onditions: VPLUS = +7V, = V Supply, VLOGI= 3V, VDD = 3V, = V, V INH = 2.2V, V INL =.8V, Unless Otherwise Specified. (ontinued) TEST ONDITIONS SW-TRL (-) Into S_Latch t SETUP (Note, Figure ) Full ns Setup Time SW-TRL (-) Into S_Latch Hold t HOLD (Note, Figure ) Full ns Time Input urrent, I INH, I INL V IN = V or VLOGI Full - µa S_LATH Rise, Fall Time % to 9% and 9% to % Full 3 ns S_LATH Minimum Pulse Width Rising to Falling Edge % Points Full ns DYNAMI HARATERISTIS Turn-ON Time, t ON VXA or VXB = 3V, R L = 3, L = 3pF 2 2 ns (see Figure ) Full 3 ns Turn-OFF Time, t OFF VXA or VXB = 3V, R L = 3, L = 3pF 2 8 ns (see Figure ) Full 8 ns OFF apacitance, OFF f = MHz, VXA or VXB = V OM = V 2 pf ON apacitance, OM(ON) f = MHz, VXA or VXB = V OM = V 2 pf OFF Isolation R L =, L = pf, f = MHz, 2 - db rosstalk (Note ) VXA or VXB= V P-P (see Figure 3) 2 - db Switch ontact 3dB Bandwidth R L =, L = pf 2 MHz harge Injection, Q L = nf, V G = V, R G = see Figure 2) 2 2 p POWER SUPPLY HARATERISTIS VPLUS Supply, I (Quiescent) 2 3 µa Full µa VPLUS Supply, I (MHz) 2 8 µa Full 2 µa Supply, I (Quiescent) 2 µa Full 9 µa Supply, I (MHz) 2.7 ma Full.7 ma VDD Supply, I (Quiescent) 2 µa Full µa VDD Supply, I (MHz) 2. ma Full ma VLOGI Internal Logic Supply, I 2 µa (Quiescent) Full µa VLOGI Internal Logic Supply, I 2 3.2 ma (MHz) Full 3.2 ma NOTES:. Flatness is defined as the delta between the maximum and minimum r ON values over the specified voltage range.. Between any two switches.. S_LATH must remain low when changing SW-TRL(-) condition. Likewise, while S_LATH is being toggled, it is important to keep SW- TRL(-) in the intended switch condition. 7. Typical Values are not production tested 8. Digital haracteristics remain stable with respect to VPLUS and variation. These parameters are controlled by the difference between and VDD, which the user should maintain at a constant spread of VDD = + 3V. 9. Parts are % tested at +2. Temperature limits established by characterization and are not production tested.. Limits established by characterization and are not production tested. TEMP ( ) MIN (Note 9) TYP (Note ) MAX (Note 9) UNITS FN92 Rev Page of
Test ircuits and Waveforms S-LATH INPUT 3V V % t r < 2ns t f < 2ns VPLUS VDD VLOGI V NB SWITH OUTPUT V NB t ON V OUT 2% t OFF 7% V OUT Switch changes state on rising edge of S-LATH. V NA = VOUT at all times. FIGURE A. MEASUREMENT POINTS V NB FIGURE. SWITHING TIMES SWITH INPUTS -B SX-RTL INPUT IN LATH -A Repeat test for all switches. L includes fixture and stray capacitance. R L V OUT = V --------------------------- (NB) R L + r ON FIGURE B. TEST IRUIT V OUT R L 3 L 3pF VPLUS VDD VLOGI SWITH OUTPUT V OUT V OUT R G -A -B V OUT ON ONTROLLER SEQUENE SW: ON/OFF/ON OFF ON Q = V OUT x L 3V V V G LATH IN L Switch changes state on rising edge of S-LATH. FIGURE 2A. MEASUREMENT POINTS Repeat test for all switches. L includes fixture and stray capacitance. FIGURE 2B. TEST IRUIT FIGURE 2. HARGE INJETION VPLUS VDD VLOGI VPLUS VDD VLOGI SIGNAL GENERATOR -A r ON = V /ma -A V XA S-LATH/SX-RTL ma V S-LATH/SX-RTL ANALYZER -B -B R L Repeat test for all switches. Repeat test for all switches. FIGURE 3. OFF ISOLATION TEST IRUIT FIGURE. r ON TEST IRUIT FN92 Rev Page of
Test ircuits and Waveforms (ontinued) SX-TRL SHOULD REMAIN IN DESIRED STATE, BEFORE DURING AND AFTER S-LATH. S-LATH INPUT % % SX-TRL t SETUP t HOLD % % DATA = DATA = FIGURE. SETUP AND HOLD TIMES ISL32 Detailed Description The ISL32 quad analog switches offer switching capability from a split-supply -3V and +9V or single V and V to 2V supply. Please review Power Supply onsiderations on page 7 before powering up the device. The user can employ multi-device control data in two ways. The S-S-TRL lines can be connected to several devices, with each device having its own S-LATH connection to the system controller. The other way is to have separate S--TRL connections for each switch and a single S-LATH connection to all ISL32s. Power Supply onsiderations The ISL32 construction consists of MOS analog switches and four supply pins: VPLUS,, VLOGI, VDD and. VPLUS and determine the switch voltage range of the four SPST MOS switches and set their analog voltage limits. There are no connections between the switch contact signal path and. VLOGI and power the digital input/output logic level shifters (thus setting the digital switching point). The level shifters convert the external logic levels to VDD and signals to drive the internal digital circuitry. VDD and power the internal logic of the device. VDD must always be held at a fixed 3V above to avoid device damage. Whether operating split or single device, will always be @ V and VLOGI will always be @ 3V. VDD should always remain 3V above. to VPLUS should not exceed a maximum spread of more than 2V. For examples, see the following: SPLIT POSITIVE AND NEGATIVE SWITH RANGE OPERATION = -3V, VDD = +V, VPLUS = +9V, VLOGI = 3V = -V, VDD = +2V, VPLUS = +V, VLOGI = 3V POSITIVE SWITH RANGE OPERATION = V, VDD = +3V, VPLUS = +2V, VLOGI = 3V ISL32 Parallel ommunications The ISL32 operates based on parallel data. TRL and LATH inputs are 3V level compatible. Setup and Hold times relative to the rising the edge of the S-LATH input must be maintained for proper operation. Switch control data is clocked into internal registers on the rising edge of S-LATH. MULTIPLE DEVIE ONNETION The user can configure the four SX-TRL inputs to connect to several ISL32 s. In this configuration each ISL32 requires a separate/dedicated S-LATH input. Therefore, each device will update at different times. So in essence, the S-S-TRL signals are multiplexed and connected to all switch control inputs in parallel (see Figure 8). For non-multiplexed connections, each SX-TRL input must have a dedicated logic input for each switch/each device. If three ISL32s are being used, the user must supply 2 dedicated SX-TRL signals. All switches are then tied to the same S-LATH pin and all devices would change state at the same time. ISL32 S-LATH Pin Discussion The ISL32 s operational state does not change while SX-TRL inputs are changing. The user must insure that the S-LATH pin remains low and does not change state while SX-TRL inputs are changing. Once the user has set the SX-TRL inputs, the S-LATH pin is then utilized. Just as the S-LATH pin must remain low during SX-TRL setup, the SX-TRL pins must remain stable during and after the S-LATH operation. The switch from present to next operation occurs on the rising edge on the S-LATH pin. This rising edge transfers data to the internal -bit switch control registers. This transfer updates opening/closing of the four switches. ISL32 Power On Reset (POR) Switch conditions are controlled during POR (Power On Reset). During and after a POR condition, the switches are opened until closed by the controller. FN92 Rev Page 7 of
SW2-B S3 ONTROL SW3-A SW2-A S2 ONTROL SW3-B INTERNAL S-LATH REGISTERS INTERNAL S-LATH REGISTERS SW-B S ONTROL SW-A SW-A S ONTROL SW-B LEVEL SHIFTER LEVEL SHIFTER LEVEL SHIFTER LEVEL SHIFTER LEVEL SHIFTER S-LATH S-TRL S2-TRL S3-TRL S-TRL FIGURE. ISL32 FUNTIONAL DIAGRAM Supply Sequencing and Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the I. All switch contact I/O pins contain ESD protection diodes from the pin to VPLUS and to (see Figure 7). To prevent forward biasing these diodes, VPLUS, and must be applied before any input signals, and switch signal voltages must remain between VPLUS and. Digital control signals should be limited to VLOGI and. SPEIFI POWER SEQUENE. 2. Typical........... 3V to V with respect to 3. VPLUS Typical....... +V to +9V with respect to. VDD................... +3V to with respect to. VLOGI.................. +3V with respect to If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a k resistor in series with the input. The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low r ON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 7). These additional diodes limit the analog signal from V below VPLUS to V above. The leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. ESD Protection The device contains ESD protection on the device pins. These devices are design to work based on dv/dt. During power-up, the user should review the rise/fall times on the power connections. The rise time of the power rails should not be faster than µs. VPLUS VLOGI VPLUS LAMP VDD LAMP VLOGI LAMP ONE FOR EAH PIN LISTED: A, B, 2A, 2B, 3A, 3B, A, B, VDD, VLOGI ONE FOR EAH PIN LISTED: S-TRL, S2-TRL, S3-TRL, S-TRL, S-LATH FIGURE 7. ESD/OVERVOLTAGE PROTETION FN92 Rev Page 8 of
Logic-Level Thresholds VLOGI and power the internal logic level shifter stages, so VPLUS and have no affect on logic thresholds. Thus, SX-TRL, S-LATH receive thresholds which will remain constant, despite changes to VPLUS and. Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both VPLUS and. One of these diodes conducts if any analog signal exceeds VPLUS or. ISL32 Device Programming Programming the device entails accessing the internal switch control registers. To write data into the register, the data must be transferred via the S-LATH pin. Via the S-LATH pin, the programmer has complete control as to when data is transferred to the internal latches. Until such time as the S-LATH pin is toggled, the device will remain as previously programmed. Therefore, data transitions on the SX-TRL inputs will not effect the switch s operational condition. FN92 Rev Page 9 of
VPLUS (VSUB+ TO VSUB+2V) VLOGI ( + 3V) VDD (VSUB +3V) VSUB (-3V TO V).7µF 2.7µF 3.7µF.7µF SWITH ONTAT ONNETIONS S-LATH DEVIE DIGITAL INPUTS FROM SYSTEM ONTROLLER S-LATH A B 2A 2B 3 2 SW-TRL SW2-TRL SW3-TRL SW-TRL 7 8 9 SW_TRL SW2_TRL SW3_TRL SW_TRL N B A 3B 3A N 2 9 VDD 8 VLOGI 7 VPLUS 8 9 2 3 ISL32 SWITH ONTAT ONNETIONS S-LATH DEVIE 2 S-LATH A B 2A 2B 3 2 7 8 9 SW_TRL SW2_TRL SW3_TRL SW_TRL N B A 3B 3A N 2 9 VDD 8 VLOGI 7 VPLUS DEVIE DEOUPLING 2 3 2 3 ISL32 SWITH ONTAT ONNETIONS S-LATH DEVIE 3 S-LATH A B 2A 2B 3 2 7 8 9 SW_TRL N 2 SW2_TRL 9 VDD 8 SW3_TRL VLOGI 7 SW_TRL VPLUS N B A 3B 3A 7 2 3 ISL32 SWITH ONTAT ONNETIONS FIGURE 8. ISL32 SW-ONTROL LINES MULTIPLEXED FN92 Rev Page of
Typical Performance urves VLOGI = 3V, T A = +2, V IH = 3V, V IL = V, Unless Otherwise Specified. = -3V, VPLUS = 3V, VDD = V I OM = ma +8 +8 +2 r ON ( ) - +2 r ON ( ) - -3-2 - 2 3 FIGURE 9. ON-RESISTANE vs SWITH VOLTAGE = V, VPLUS = V, VDD = 3V I OM = ma 2 3 FIGURE. ON-RESISTANE vs SWITH VOLTAGE = -3V, VPLUS = 7V, VDD = V I OM = ma = V, VPLUS = 7V, VDD = 3V I OM = ma r ON ( ) +2 - +8 r ON ( ) +2 +8 - -3-2 - 2 3 7 2 3 7 FIGURE. ON-RESISTANE vs SWITH VOLTAGE FIGURE 2. ON-RESISTANE vs SWITH VOLTAGE = -3V, VPLUS = 9V, VDD = V I OM = ma = V, VPLUS = 2V, VDD = 3V I OM = ma r ON ( ) - +8 +2 r ON ( ) - +8 +2-3 -2-2 3 7 8 9 2 3 7 8 9 2 FIGURE 3. ON-RESISTANE vs SWITH VOLTAGE FIGURE. ON-RESISTANE vs SWITH VOLTAGE FN92 Rev Page of
Typical Performance urves VLOGI = 3V, T A = +2, V IH = 3V, V IL = V, Unless Otherwise Specified. (ontinued) = -3V, VPLUS = 3V, VDD = V = V, VPLUS = V, VDD = 3V V OM (na) V OM (na) -3-2 - 2 3 2 3 FIGURE. ON-LEAKAGE vs SWITH VOLTAGE FIGURE. ON-LEAKAGE vs SWITH VOLTAGE = -3V, VPLUS = 7V, VDD = V = V, VPLUS = 7V, VDD = 3V V OM (na) V OM (na) -3-2 - 2 3 7 2 3 7 FIGURE 7. ON-LEAKAGE vs SWITH VOLTAGE FIGURE 8. ON-LEAKAGE vs SWITH VOLTAGE V OM (na) = -3V, VPLUS = 9V, VDD = V -3-2 - 2 3 7 8 9 V OM (na) = V, VPLUS = 2V, VDD = 3V 2 3 7 8 9 2 FIGURE 9. ON-LEAKAGE vs SWITH VOLTAGE FIGURE 2. ON-LEAKAGE vs SWITH VOLTAGE FN92 Rev Page 2 of
Typical Performance urves VLOGI = 3V, T A = +2, V IH = 3V, V IL = V, Unless Otherwise Specified. (ontinued) = -3V, VPLUS = 3V, VDD = V = V, VPLUS = V, VDD = 3V V OM (na) V OM (na) -3-2 - 2 3 2 3 FIGURE 2. OFF-LEAKAGE vs SWITH VOLTAGE FIGURE 22. OFF-LEAKAGE vs SWITH VOLTAGE 9 = -3V, VPLUS = 7V, VDD = V 9 = V, VPLUS = 7V, VDD = 3V 8 8 7 7 V OM (na) V OM (na) 3 3 2 2-3 -2-2 3 7 FIGURE 23. OFF-LEAKAGE vs SWITH VOLTAGE 2 3 7 FIGURE 2. OFF-LEAKAGE vs SWITH VOLTAGE 9 = -3V, VPLUS = 9V, VDD = V 9 = V, VPLUS = 2V, VDD = 3V 8 8 7 7 V OM (na) V OM (na) 3 3 2 2-3 -2-2 3 7 8 9 2 3 7 8 9 2 FIGURE 2. OFF-LEAKAGE vs SWITH VOLTAGE FIGURE 2. OFF-LEAKAGE vs SWITH VOLTAGE FN92 Rev Page 3 of
Typical Performance urves VLOGI = 3V, T A = +2, V IH = 3V, V IL = V, Unless Otherwise Specified. (ontinued).. = -3V, VOM = VPLUS - V, VDD = V I OM = ma.. = V, VOM = VPLUS - V, VDD = 3V I OM = ma r ON ( ) +2 +8-3 7 8 9 VPLUS (V) r ON ( ) +2 +8 -. 7. 9. VPLUS (V) FIGURE 27. ON-RESISTANE vs SUPPLY VOLTAGE FIGURE 28. ON-RESISTANE vs SUPPLY VOLTAGE.9.88 = -3V, VDD = V +2 7... = -3V, VDD = V V IN (V).82.7.7. 8 +8 - VPLUS ( A). +2 - +8 2.. 2.7 2.9 3. 3.3 VPLUS (V) FIGURE 29. DIGITAL SWITHING POINT vs SUPPLY VOLTAGE 3 7 8 9 VPLUS (V) FIGURE 3. DEVIE QUIESENT URRENT (VPLUS) 3 3 VPLUS = 9V, = -3V, VDD = V VPLUS = 9V, = -3V, VDD = V Q (p) 2 2 VPLUS = 2V, = V, VDD = 3V VPLUS = 7V, = V, VDD = 3V TIME (ns) 3 2 VPLUS = 9V, = V, VDD = 3V -3-2 - 2 3 7 8 9 2 FIGURE 3. HARGE INJETION vs SWITH VOLTAGE -3-2 - 2 3 7 8 9 FIGURE 32. t ON vs VOM FN92 Rev Page of
Typical Performance urves VLOGI = 3V, T A = +2, V IH = 3V, V IL = V, Unless Otherwise Specified. (ontinued) - -2-3 VPLUS = 9V, = V, VDD = 3V VPLUS = 9V, = -3V, VDD = V R L = VPLUS = 9V, = V, VDD = 3V VPLUS = 9V, = -3V, VDD = V R L = 2 3 ROSSTALK - - - -7-8 OFF ISOLATION (db) 7 8-9 - - k k k M M M M FREQUENY (Hz) FIGURE 33. ROSSTALK 9 k k k M M M M FREQUENY (Hz) FIGURE 3. OFF-ISOLATION NORMALIZED GAIN (db) - -2-3 - - - GAIN V SS = -3V, V DD = V VPLUS = 9V V SS = V, V DD = 3V VPLUS = V TO 9V, = V, VDD = 3V S-LATH DATA = DATA = SX-RTL -7-8 R L = V IN =.2V P-P to 2V P-P SWITH ON VOUT WITH VOM = 3V SWITH OFF FREQUENY (MHz) ms/div FIGURE 3. FREQUENY RESPONSE FIGURE 3. TIMING opyright Intersil Americas LL 28. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see www.intersil.com FN92 Rev Page of
L2.x 2 LEAD QUAD FLAT NO-LEAD PLASTI PAKAGE Rev, / X A B X 2 PIN # INDEX AREA PIN INDEX AREA 2.7 ±. (X).. M AB TOP VIEW 2X. ±. 2X.2 + / -7 BOTTOM VIEW SEE DETAIL "X" ( 3. 8 TYP ) ( 2. 7 ) ( 2X. ). 9 ±. SIDE VIEW. BASE PLANE SEATING PLANE 8. 2 REF ( 2X. 2 ). MIN.. MAX. ( 2X. ) DETAIL "X" TYPIAL REOMMENDED LAND PATTERN NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Ym-99. 3. Unless otherwise specified, tolerance : Decimal ±... Dimension b applies to the metallized terminal and is measured between.mm and.3mm from the terminal tip. Tiebar shown (if present) is a non-functional feature. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # indentifier may be either a mold or mark feature. FN92 Rev Page of