February 7, 2006 Microsoft X02046 IBM PowerPC Processor from the XBOX 360 Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package 2.2 Package Cross-Section 2.3 Die 2.4 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Polysilicon 3.7 SOI Substrate and Deposited Oxide Isolation 4 Memory Cell Analysis 4.1 Memory Cell Overview 4.2 6T SRAM Plan-View Analysis 4.3 6T-SRAM Cross-Sectional Analysis 5 Materials Analysis 5.1 TEM-EDS Analysis of Dielectrics 5.2 TEM EDS Analysis of the Copper Liner and Gate Silicide 5.3 SEM-EDS Analysis of Solder Bumps 6 References 7 Critical Dimensions 7.1 Package and Die 7.2 Horizontal Dimensions 7.3 Vertical Dimensions Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 XBOX 360 2.1.2 X02046 Heatsink on the Board Inside the XBOX 360 2.1.3 X02046 on the Board Inside the XBOX 360 2.1.4 Package Top (0535 CANADA) 2.1.5 Package Top (0533 TAIWAN) 2.1.6 Package Top (0538 TAIWAN) 2.1.7 Package Bottom (0535 CANADA) 2.1.8 Plan-View Package X-Ray 2.2.1 Package Cross-Section 2.2.2 Die Edge and Die Attach 2.2.3 Die Edge Detail 2.2.4 Minimum Pitch PWB Metal 2.2.5 Solder Bump and Via 2.2.6 Solder Bump SEM 2.2.7 Bond Pad and UBM Detail SEM 2.3.1 Die Photograph 2.3.2 Die Markings 2.3.3 Die Markings 2.3.4 Annotated Metal 3 Die Photograph 2.3.5 Annotated Die Photograph 2.4.1 Die Corner a 2.4.2 Die Corner b 2.4.3 Die Corner c 2.4.4 Die Corner d 2.4.5 Bond Pads at Die Edge 2.4.6 Bond Pads 2.4.7 Bond Pads Detail 3 Process Analysis 3.1.1 General Device Structure 3.1.2 Die Edge and Die Seal 3.1.3 Die Seal 3.2.1 Bond Pad Overview 3.2.2 Bond Pad Edge 3.2.3 Bond Pad Detail 3.3.1 Upper Dielectric Layers 3.3.2 Passivation 3.3.3 Passivation Detail 3.3.4 Passivation TEM 3.3.5 ILD 7 3.3.6 ILD 7 TEM 3.3.7 ILD 6
Overview 1-2 3.3.8 ILD 6 TEM 3.3.9 Lower Dielectric Layers 3.3.10 Lower Dielectric Layers TEM 3.3.11 ILD 5 3.3.12 ILD 5 TEM 3.3.13 ILD 4 3.3.14 ILD 4 TEM 3.3.15 ILD 3 and ILD 2 3.3.16 ILD 3 TEM 3.3.17 ILD 2 TEM 3.3.18 ILD 1 3.3.19 ILD 1 TEM 3.3.20 ILD 0 and PMD 3.3.21 ILD 0 and PMD TEM 3.3.22 PMD and BOX 3.3.23 Dual Stress Liners Detail 3.4.1 Minimum Space Metal 9 3.4.2 Minimum Width Metal 9 3.4.3 Minimum Pitch Metal 8 3.4.4 Metal 8 TEM 3.4.5 Minimum Pitch Metal 7 3.4.6 Minimum Pitch Metal 6 3.4.7 Metal 6 TEM 3.4.8 Minimum Pitch Metal 5 3.4.9 Minimum Pitch Metal 4 3.4.10 Minimum Pitch Metal 3 3.4.11 Minimum Pitch Metal 2 3.4.12 Minimum Pitch Metal 1 3.4.13 Metal 1 TEM 3.4.14 Metal 1 Bottom TEM 3.4.15 Metal 1 Liner Detail TEM 3.4.16 Typical Metal 0 3.5.1 Via 8 Edge 3.5.2 Minimum Pitch Via 7s 3.5.3 Minimum Pitch Via 6s 3.5.4 Minimum Pitch Via 5s 3.5.5 Minimum Pitch Via 4s 3.5.6 Minimum Pitch Via 3s 3.5.7 Minimum Pitch Via 2s 3.5.8 Minimum Pitch Via 1s 3.5.9 Minimum Pitch Via 1 TEM
Overview 1-3 3.5.10 Minimum Pitch Via 0s 3.5.11 Via 0 TEM 3.5.12 Contacts to Poly 3.5.13 Contact to Poly TEM 3.5.14 Butted Contact to Poly and Si 3.5.15 Minimum Pitch Contacts 3.5.16 Contact TEM 3.5.17 Detail of Contact Top TEM 3.6.1 NMOS and PMOS General Structure (Si-Etch) 3.6.2 Minimum Polysilicon Pitch (Glass Etch) 3.6.3 Minimum Gate Length PMOS Transistors TEM 3.6.4 PMOS Transistor Gate TEM 3.6.5 NMOS Transistor Gate TEM 3.6.6 PMOS Gate Oxide TEM 3.6.7 Polysilicon MIS Capacitor 3.6.8 Gate Wrap-Around TEM 3.6.9 Capacitor Gate Oxide TEM 3.7.1 SOI Substrate and Deposited Oxide Isolation 3.7.2 Minimum Deposited Oxide Isolation 4 Memory Cell Analysis 4.1.1 Annotated Die Photograph Metal 3 4.2.1 6T SRAM Cell Schematic 4.2.2 Metal 3 Word Lines 4.2.3 Metal 2 4.2.4 Metal 1 Bit and V DD Bus Lines 4.2.5 Metal 0 Cross-Connects 4.2.6 6T SRAM Poly 4.3.1 Word Line Gate Contacts 4.3.2 NMOS Pull-Down and Access Transistor Gate Lengths 4.3.3 NMOS Pull-Down and Access Transistor Gate Lengths Detail 4.3.4 PMOS Pull-Up Transistor Gate Lengths 4.3.5 PMOS Pull-Up Transistor Gate Lengths Detail 4.3.6 SRAM Transistor Gate Widths 4.3.7 SRAM Transistor Gate Widths Detail
Overview 1-4 5 Materials Analysis 5.1.1 Dielectric Stack 5.1.2 TEM-EDS Spectra for Passivation Layers 5.1.3 TEM-EDS Spectra for ILD 7 Layers 5.1.4 TEM-EDS Spectra for ILD 6 Layers 5.1.5 TEM-EDS Spectra for Low-k Layers for ILD 1 through ILD 5 5.1.6 TEM-EDS Spectra for Sealant Layer for ILD 1 through ILD 5 5.1.7 TEM-EDS Spectra for ILD 0 5.1.8 TEM-EDS Spectra for PMD 5.1.9 TEM-EDS Spectrum of PMOS Stress Liner 5.1.10 TEM-EDS Spectrum of NMOS Stress Liner 5.1.11 TEM-EDS Spectra of BOX 5.2.1 TEM-EDS Spectra for Metal 7 Ta-based Liner 5.2.2 TEM-EDS Spectrum of Contact Metal 0 5.2.3 TEM-EDS Spectrum of the Gate Cobalt Silicide 5.2.4 TEM-EDS Spectrum of the Contact Cobalt Silicide 5.3.1 SEM-EDS Spectrum of PbSn Solder Bump 5.3.2 SEM-EDS Spectrum of Ni UBM
Overview 1-5 1.2 List of Tables 1 Overview 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 Package Markings Summary 2.2.1 Package Vertical Dimensions 2.2.2 Package Horizontal Dimension 2.4.1 Package and Die Dimensions 3 Process Analysis 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Thicknesses 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Transistor and Poly Horizontal Dimensions 3.6.2 Transistor and Poly Vertical Dimensions 3.7.1 SOI Substrate and Deposited Oxide Isolation Vertical Dimensions 4 Memory Cell Analysis 4.3.1 6T SRAM Transistor Sizes 5 Materials Analysis 5.1.1 Summary of Dielectric Composition 7 Critical Dimensions 7.1.1 Package and Die Dimensions 7.2.1 Metallization Horizontal Dimensions 7.2.2 Via and Contact Dimensions 7.2.3 Transistor and Poly Horizontal Dimensions 7.2.4 Isolation 7.2.5 6T SRAM Transistor Sizes 7.3.1 Dielectric Thicknesses 7.3.2 Metallization Thicknesses 7.3.3 Transistor and Poly Vertical Dimensions 7.3.4 SOI Substrate and Deposited Oxide Isolation Vertical Dimensions
About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: 1.613.829.0414 F: 1.613.829.0515 Web site: www.chipworks.com Email: info@chipworks.com Please send any feedback to feedback@chipworks.com