Control Integrated POwer System (CIPOS )

Control Integrated POwer System (CIPOS ) Datasheet Datasheet Please read the Important Notice and Warnings at the end of this document <Revision 2.6> www.infineon.com <268>

Table of Contents CIPOS Control Integrated POwer System... 3 Features... 3 Target Applications... 3 Description... 3 System Configuration... 3 Pin Configuration... 4 Internal Electrical Schematic... 4 Pin Assignment... 5 Pin Description... 5 HIN(U, V, W) and LIN(U, V, W) (Low side and high side control pins, Pin 7 2)... 5 VFO (Faultoutput and NTC, Pin 4)... 6 ITRIP (Over current detection function, Pin 5)... 6 VDD, VSS (Low side control supply and reference, Pin 3, 6)... 6 VB(U, V, W) and VS(U, V, W) (High side supplies, Pin 6)... 6 NW, NV, NU (Low side emitter, Pin 7 9)... 6 W, V, U (High side emitter and low side collector, Pin 2 22)... 6 P (Positive bus input voltage, Pin 23)... 6 Absolute Maximum Ratings... 7 Module Section... 7 Inverter Section... 7 Control Section... 7 Recommended Operation Conditions... 8 Static Parameters... 9 Dynamic Parameters... Bootstrap Parameters... Thermistor... Mechanical Characteristics and Ratings... Circuit of a Typical Application... 2 Switching Times Definition... 3 Electrical characteristic... 4 Package Outline... 5 Revision History... 6 Datasheet 2 <Revision 2.6> <268>

CIPOS Control Integrated POwer System Dual InLine Intelligent Power Module 3Φ bridge 6V / 4A Features Fully isolated Dual InLine molded module Reverse conducting IGBTs with monolithic body diode Rugged SOI gate driver technology with stability against transient and negative voltage Allowable negative VS potential up to V for signal transmission at VBS=5V Integrated bootstrap functionality Over current shutdown Temperature monitor Undervoltage lockout at all channels Low side emitter pins accessible for all phase current monitoring (open emitter) Crossconduction prevention All of 6 switches turn off during protection Leadfree terminal plating; RoHS compliant Target Applications Dish washers Refrigerators Fans Description The CIPOS module family offers the chance for integrating various power and control components to increase reliability, optimize PCB size and system costs. It is designed to control three phase AC motors and permanent magnet motors in variable speed drives for applications like a refrigerator and a dish washer. The package concept is specially adapted to power applications, which need good thermal conduction and electrical isolation, but also EMIsave control and overload protection. The reverse conducting IGBTs are combined with an optimized SOI gate driver for excellent electrical performance. System Configuration 3 half bridges with reverse conducting IGBTs 3Φ SOI gate driver Thermistor Pintoheatsink clearance distance typ..6mm Low power motor drives Datasheet 3 <Revision 2.6> <268>

Pin Configuration Bottom View () VS(U) (2) VB(U) (3) VS(V) (4) VB(V) (5) VS(W) (6) VB(W) (7) HIN(U) (8) HIN(V) (9) HIN(W) () LIN(U) () LIN(V) (2) LIN(W) (3) VDD (4) VFO (5) ITRIP (6) VSS (24) NC (23) P (22) U (2) V (2) W (9) NU (8) NV (7) NW Figure Pin configuration Internal Electrical Schematic NC (24) () VS(U) P (23) (2) VB(U) VB HO RBS VS U (22) (3) VS(V) (4) VB(V) VB2 HO2 RBS2 VS2 V (2) (5) VS(W) (6) VB(W) VB3 HO3 RBS3 VS3 W (2) (7) HIN(U) HIN LO (8) HIN(V) (9) HIN(W) () LIN(U) () LIN(V) HIN2 HIN3 LIN LIN2 LO2 NU (9) (2) LIN(W) (3) VDD LIN3 VDD NV (8) (4) VFO (5) ITRIP VFO ITRIP LO3 (6) VSS VSS NW (7) Thermistor Figure 2 Internal schematic Datasheet 4 <Revision 2.6> <268>

Pin Assignment Pin Number Pin Name Pin Description VS(U) Uphase high side floating IC supply offset voltage 2 VB(U) Uphase high side floating IC supply voltage 3 VS(V) Vphase high side floating IC supply offset voltage 4 VB(V) Vphase high side floating IC supply voltage 5 VS(W) Wphase high side floating IC supply offset voltage 6 VB(W) Wphase high side floating IC supply voltage 7 HIN(U) Uphase high side gate driver input 8 HIN(V) Vphase high side gate driver input 9 HIN(W) Wphase high side gate driver input LIN(U) Uphase low side gate driver input LIN(V) Vphase low side gate driver input 2 LIN(W) Wphase low side gate driver input 3 VDD Low side control supply 4 VFO Fault output / Temperature monitor 5 ITRIP Over current shutdown input 6 VSS Low side control negative supply 7 NW Wphase low side emitter 8 NV Vphase low side emitter 9 NU Uphase low side emitter 2 W Motor Wphase output 2 V Motor Vphase output 22 U Motor Uphase output 23 P Positive bus input voltage 24 NC No Connection Pin Description HIN(U, V, W) and LIN(U, V, W) (Low side and high side control pins, Pin 7 2) These pins are positive logic and they are responsible for the control of the integrated IGBT. The Schmitttrigger input thresholds of them are such to guarantee LSTTL and CMOS compatibility down to 3.3V controller outputs. Pulldown resistor of about 5k is internally provided to prebias inputs during supply startup and a zener clamp is provided for pin protection purposes. Input Schmitttrigger and noise filter provide beneficial noise rejection to short input pulses. The noise filter suppresses control pulses which are below the filter time t FILIN. The filter acts according to Figure 4. CIPOS TM INPUT NOISE FILTER UZ=.5V SWITCH LEVEL VIH; VIL Datasheet 5 <Revision 2.6> <268> HINx LINx VSS Figure 3 5k SchmittTrigger Input pin structure a) b) HIN LIN HO LO Figure 4 t FILIN low HIN LIN HO LO high Input filter timing diagram t FILIN

It is not recommended for proper work to provide input pulsewidth lower than µs. The integrated gate drive provides additionally a shoot through prevention capability which avoids the simultaneous onstate of two gate drivers of the same leg (i.e. HO and LO, HO2 and LO2, HO3 and LO3). When two inputs of a same leg are activated, only former activated one is activated so that the leg is kept steadily in a safe state. A minimum deadtime insertion of typically 38ns is also provided by driver IC, in order to reduce crossconduction of the external power switches. VFO (Faultoutput and NTC, Pin 4) The VFO pin indicates a module failure in case of under voltage at pin VDD or in case of triggered over current detection at ITRIP. A pullup resistor is externally required. VDD VFO VSS Figure 5 Thermistor R ON,FLT CIPOS TM From ITRIP Latch From UV detection Internal circuit at pin VFO The same pin provides direct access to the NTC, which is referenced to VSS. An external pullup resistor connected to +5V ensures that the resulting voltage can be directly connected to the microcontroller. ITRIP (Over current detection function, Pin 5) CIPOS provides an over current detection function by connecting the ITRIP input with the IGBT collector current feedback. The ITRIP comparator threshold (typ..47v) is referenced to VSS ground. An input noise filter (typ.: t ITRIPMIN = 53ns) prevents the driver to detect false overcurrent events. Over current detection generates a shutdown of all outputs of the gate driver after the shutdown propagation delay of typically ns. The faultclear time is set to minimum 4µs. VDD, VSS (Low side control supply and reference, Pin 3, 6) VDD is the control supply and it provides power both to input logic and to output power stage. Input logic is referenced to VSS ground. The undervoltage circuit enables the device to operate at power on when a supply voltage of at least a typical voltage of V DDUV+ = 2.V is present. The IC shuts down all the gate drivers power outputs, when the VDD supply voltage is below V DDUV =.4V. This prevents the external power switches from critically low gate voltage levels during onstate and therefore from excessive power dissipation. VB(U, V, W) and VS(U, V, W) (High side supplies, Pin 6) VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the external high side power device emitter voltage. Due to the low power consumption, the floating driver stage is supplied by integrated bootstrap circuit. The undervoltage detection operates with a rising supply threshold of typical V BSUV+ = 2.V and a falling threshold of V BSUV =.4V. VS(U, V, W) provide a high robustness against negative voltage in respect of VSS of 5V transiently. This ensures very stable designs even under rough conditions. NW, NV, NU (Low side emitter, Pin 7 9) The low side emitters are available for current measurements of each phase leg. It is recommended to keep the connection to pin VSS as short as possible in order to avoid unnecessary inductive voltage drops. W, V, U (High side emitter and low side collector, Pin 2 22) These pins are motor U, V, W input pins. P (Positive bus input voltage, Pin 23) The high side IGBTs are connected to the bus voltage. It is noted that the bus voltage does not exceed 45V. Datasheet 6 <Revision 2.6> <268>

Absolute Maximum Ratings (V DD = 5V and T J = 25 C, if not stated otherwise) Module Section Description Condition Symbol min max Storage temperature range T stg 4 25 C Isolation test voltage RMS, f = 6Hz, t = min V ISOL 2 V Operating case temperature range Refer to Figure 6 T C 4 C Inverter Section Description Condition Symbol Max. blocking voltage I C = 25µA V CES 6 V DC link supply voltage of PN Applied between PN V PN 45 V DC link supply voltage (surge) of PN Applied between PN V PN(surge) 5 V Output current T C = 25 C, T J < 5 C T C = C, T J < 5 C Maximum peak output current less than ms I C(peak) 8 8 A Short circuit withstand time V DC 4V, T J = 5 C t SC 5 µs Power dissipation per IGBT P tot 2.8 W Operating junction temperature range T J 4 5 C Single IGBT thermal resistance, junctioncase I C min 4 2.5 max 4 2.5 R thjc 5.73 K/W A Control Section Description Condition Symbol Module supply voltage V DD 2 V High side floating supply voltage (VB vs. VS) Input voltage LIN, HIN, ITRIP min max V BS 2 V Switching frequency f PWM 2 khz V IN V ITRIP V Allowed number of short circuits: <; time between short circuits: >s. Datasheet 7 <Revision 2.6> <268>

Recommended Operation Conditions All voltages are absolute voltages referenced to V SS potential unless otherwise specified. Description Symbol min typ max DC link supply voltage of PN V PN 4 V High side floating supply voltage (V B vs. V S) V BS 3.5 8.5 V Low side supply voltage V DD 4. 6 8.5 V Control supply variation Logic input voltages LIN, HIN, ITRIP ΔV BS, ΔV DD V IN V ITRIP Between VSS N (including surge) V SS 5 5 V 5 5 V/µs V Figure 6 T C measurement point Any measurement except for the specified point in figure 6 is not relevant for the temperature verification and brings wrong or different information. Datasheet 8 <Revision 2.6> <268>

Static Parameters (V DD = 5V and T J = 25 C, if not stated otherwise) Description Condition Symbol min typ max I C = 2.5A CollectorEmitter saturation voltage T J = 25 C 5 C V CE(sat).6.8 2. V I F = 2.5A EmitterCollector forward voltage T J = 25 C 5 C V F.75.8 2.2 V CollectorEmitter leakage current V CE = 6V I CES ma Logic "" input voltage (LIN, HIN) V IH 2. 2.5 V Logic "" input voltage (LIN, HIN) V IL.7.9 V ITRIP positive going threshold V IT,TH+ 4 47 54 mv ITRIP input hysteresis V IT,HYS 4 7 mv VDD and VBS supply under voltage positive going threshold VDD and VBS supply under voltage negative going threshold VDD and VBS supply under voltage lockout hysteresis V DDUV+ V BSUV+ V DDUV V BSUV V DDUVH V BSUVH.8 2. 3. V 9.5.4.2 V..7 V Input clamp voltage (HIN, LIN, ITRIP) Iin=4mA V INCLAMP 9.. 2.5 V Quiescent VB x supply current (VB x only) Quiescent VDD supply current (VDD only) H IN = V I QBS 3 5 µa L IN = V, H INX = 5V I QDD 37 9 µa Input bias current V IN = 5V I IN+.5 ma Input bias current V IN = V I IN 2 µa ITRIP input bias current V ITRIP = 5V I ITRIP+ 65 5 µa VFO input bias current VFO = 5V, V ITRIP = V I FO 6 µa VFO output voltage I FO = ma, V ITRIP = V V FO.5 V Datasheet 9 <Revision 2.6> <268>

Dynamic Parameters (V DD = 5V and T J = 25 C, if not stated otherwise) Description Condition Symbol min typ max Turnon propagation delay time t on 65 ns V LIN, HIN = 5V, Turnon rise time t r 5 ns I C = 2.5A, Turnon switching time t V DC = 3V c(on) 6 ns Reverse recovery time t rr 7 ns Turnoff propagation delay time V LIN, HIN = V, t off 685 ns Turnoff fall time I C = 2.5A, t f 8 ns Turnoff switching time V DC = 3V t c(off) 2 ns Short circuit propagation delay time From V IT,TH+ to % I SC t SCP 45 ns Input filter time ITRIP V ITRIP = V t ITRIPmin 53 ns Input filter time at LIN, HIN for turn on and off V LIN, HIN = V & 5V t FILIN 29 ns Fault clear time after ITRIPfault V ITRIP = V t FLTCLR 4 65 2 µs Deadtime between low side and high side DT PWM. µs Deadtime of gate drive circuit DT IC 38 ns IGBT turnon energy (includes reverse recovery of diode) IGBT turnoff energy Diode recovery energy V DC = 3V, I C = 2.5A T J = 25 C 5 C V DC = 3V, I C = 2.5A T J = 25 C 5 C V DC = 3V, I C = 2.5A T J = 25 C 5 C E on E off E rec 2 35 4 7 25 µj µj µj Bootstrap Parameters (T J = 25 C, if not stated otherwise) Description Condition Symbol min typ max Repetitive peak reverse voltage V RRM 6 V Bootstrap diode resistance of Uphase VS2 or VS3 = 3V, T J = 25 C VS2 and VS3 = V, T J = 25 C VS2 or VS3 = 3V, T J = 25 C VS2 and VS3 = V, T J = 25 C R BS 35 4 5 65 Ω Reverse recovery time I F =.6A, di/dt = 8A/µs t rr_bs 5 ns Forward voltage drop I F = 2mA, VS2 and VS3 = V V F_BS 2.6 V R BS2 and R BS3 have same values to R BS. Datasheet <Revision 2.6> <268>

Thermistor resistance [kω ] Control Integrated POwer System (CIPOS ) Thermistor Description Condition Symbol min typ max Resistor T NTC = 25 C R NTC 85 k Bconstant of NTC (Negative Temperature Coefficient) B(25/) 492 K 35 Thermistor resistance [kω ] 3 25 2 5 5 35 3 25 2 5 5 Min. Typ. Max. 5 55 6 65 7 75 8 85 9 95 5 5 2 25 3 Thermistor temperature [ ] Figure 7 4 3 2 2 3 4 5 6 7 8 9 2 3 Thermistor temperature [ ] Thermistor resistance temperature curve and table (For more information, please refer to the application note AN26 CIPOS Mini Technical description ) Mechanical Characteristics and Ratings Description Condition min typ max Mounting torque M3 screw and washer.59.69.78 Nm Flatness Refer to Figure 8 5 µm Weight 6.5 g + + Figure 8 Flatness measurement position Datasheet <Revision 2.6> <268>

Control GND line Control Integrated POwer System (CIPOS ) Circuit of a Typical Application NC (24) () VS(U) P (23) (2) VB(U) VB HO RBS VS U (22) #4 (3) VS(V) (4) VB(V) VB2 HO2 (5) VS(W) RBS2 VS2 V (2) 3ph AC Motor (6) VB(W) VB3 HO3 # RBS3 VS3 W (2) #5 (7) HIN(U) HIN (8) HIN(V) HIN2 LO (9) HIN(W) HIN3 NU (9) Micro Controller VDD line () LIN(U) () LIN(V) (2) LIN(W) (3) VDD (4) VFO LIN LIN2 LIN3 VDD VFO LO2 NV (8) #6 #7 Power GND line 5 or 3.3V line (5) ITRIP (6) VSS ITRIP VSS LO3 NW (7) Temperature monitor <Signal for protection> #3 #2 Thermistor Uphase current sensing Vphase current sensing Wphase current sensing <Signal for protection> Figure 9 Typical application circuit. Input circuit To reduce input signal noise by high speed switching, the R IN and C IN filter circuit should be mounted. (Ω, nf) C IN should be placed as close to V SS pin as possible. 2. Itrip circuit To prevent protection function errors, C ITRIP should be placed as close to Itrip and V SS pins as possible. 3. VFO circuit VFO output is an open drain output. This signal line should be pulled up to the positive side of the 5V/3.3V logic power supply with a proper resistor R PU. It is recommended that RC filter be placed as close to the controller as possible. 4. VBVS circuit Capacitor for high side floating supply voltage should be placed as close to VB and VS pins as possible. 5. Snubber capacitor The wiring between CIPOS Mini and snubber capacitor including shunt resistor should be as short as possible. 6. Shunt resistor The shunt resistor of SMD type should be used for reducing its stray inductance. 7. Ground pattern Ground pattern should be separated at only one point of shunt resistor as short as possible. Datasheet 2 <Revision 2.6> <268>

Switching Times Definition HINx LINx.9V 2.V t rr t off t on i Cx 9% 9% % t f t r % % % % v CEx t c(off) t c(on) Figure Switching times definition Datasheet 3 <Revision 2.6> <268>

Z thjc, RCIGBT transient thermal resistance [K/W] Eon, Turn on switching energy loss [mj] Eoff, Turn off switching energy loss [mj] Erec, Reverse recovery energy loss [uj] Ic, Collector Emitter current [A] Ic, Collector Emitter current [A] IF, Emitter Collector current [A] Control Integrated POwer System (CIPOS ) Electrical characteristic 8 7 T J 8 7 8 7 6 6 6 5 5 5 4 4 4 3 2 VDD=3V VDD=2V 3 2 T J T J 3 2 T J T J..5..5 2. 2.5 3. 3.5 4. VCE(sat), Collector Emitter voltage [V] Typ. Collector Emitter saturation voltage..5..5 2. 2.5 3. 3.5 4. 4.5 VCE(sat), Collector Emitter voltage [V] Typ. Collector Emitter saturation voltage..5..5 2. 2.5 3. 3.5 V F, Emitter Collector voltage [V] Typ. Emitter Collector forward voltage.4.35.3.25 VDC=3V.3.27.24.2.8 9 8 7 6 VDC=3V.2.5 5.5.2 4..9.6 3 2.5. 2 3 4 5 6 7 8 Ic, Collector current [A] Typ. Turn on switching energy loss.3 VDC=3V. 2 3 4 5 6 7 8 Ic, Collector current [A] Typ. Turn off switching energy loss 2 3 4 5 6 7 8 Ic, Collector current [A] Typ. Reverse recovery energy loss ton, Turn on propagation delay time [ns] 74 72 7 68 66 64 62 6 58 56 VDC=3V 54 2 3 4 5 6 7 8 Ic, Collector current [A] Typ. Turn on propagation delay time tc(on), Turn on switching time [ns] 3 27 24 2 8 5 2 9 6 3 VDC=3V 2 3 4 5 6 7 8 Ic, Collector current [A] Typ. Turn on switching time toff, Turn off propagation delay time [ns] 9 8 7 6 5 4 3 2 9 8 7 VDC=3V 6 2 3 4 5 6 7 8 Ic, Collector current [A] Typ. Turn off propagation delay time tc(off), Turn off switching time [ns] 9 8 7 6 5 4 3 2 VDC=3V trr, Reverse recovery time [ns] 3 27 24 2 8 5 2 9 6 VDC=3V.. E3 D : duty ratio D=5% D=2% D=% D=5% D=2% Single pulse 3 2 3 4 5 6 7 8 Ic, Collector current [A] Typ. Turn off switching time 2 3 4 5 6 7 8 Ic, Collector current [A] Typ. Reverse recovery time E4 E7 E6 E5 E4 E3.. t P, Pulse width [sec.] IGBT transient thermal resistance at all six IGBTs operation Datasheet 4 <Revision 2.6> <268>

Package Outline Datasheet 5 <Revision 2.6> <268>

Revision History Major changes since the last revision Page or Reference Description of change Additional information and typo corrections 4 Pin configuration 5 Package outline Datasheet 6 <Revision 2.6> <268>

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