Wideband On-die Power Supply Decoupling in High Performance DRAM

Wideband On-die Power Supply Decoupling in High Performance DRAM Timothy M. Hollis, Senior Member of the Technical Staff Abstract: An on-die decoupling scheme, enabled by memory array cell technology, is presented. Resonance mitigation through the introduction of explicit series resistance in the capacitive decoupling path is shown to improve the power delivery characteristics over mid-range frequencies, while degrading the high-frequency power delivery response. A wideband decoupling scheme is proposed, in which a portion of the on-die decoupling is introduced with a corresponding damping resistance, while a second set of capacitors are placed, resistance free, at carefully chosen locations throughout the integrated circuitry. The proposed strategy is shown to minimize resonant behaviors, while enhancing the high frequency response of the power delivery network. Index Terms: power supply decoupling, equivalent series resistance, power supply resonance I. INTRODUCTION High-performance integrated circuits generally require that the corresponding power delivery network (PDN) exhibit a low-impedance profile over a wide frequency band. Unfortunately, on-chip resistance and off-chip inductance introduce parasitic series impedances, which increase with frequency. To mitigate this series impedance, on- and offchip decoupling capacitance is introduced at various levels of the PDN hierarchy. While the decoupling capacitance serves to lower the PDN impedance over high frequencies, a common side effect of explicitly placed capacitance is the formation of resonant tanks in the voltage supply lines, which may be excited through circuit activity. Potential resonances identified during the PDN design phase may be suppressed through the introduction of resistance in the resonant (LC) loop. However, this added series resistance has the tendency to raise the PDN impedance at higher frequencies, increasing the highfrequency on-chip noise. This work presents an alternative on-chip decoupling network which is shown to mitigate PDN resonances without degrading the PDN response at higher frequencies. The following section briefly describes the electrical characteristics of DRAM PDNs, using an abstracted model to illustrate the interaction of the various components, including potential resonances formed between external inductive components and the explicitlyplaced on-chip decoupling capacitors (decaps). The third section presents a decoupling strategy which suppresses PDN resonances at the cost of added high-frequency noise. This decoupling strategy is improved upon in section IV and shown to co-optimize both the mid- and high-frequency response of the PDN. The fifth section summarizes silicon validation of the proposed decap network, while the final section presents conclusions regarding the measured value of the decoupling strategy relative to its implementation complexity. II. DRAM PDN CHARACTERISTICS Fig. 1a presents a simplified model of a typical DRAM PDN, capturing the series inductance (L SYS) and resistance (R SYS) presented by the system (i.e., the package, module, motherboard, etc.), the series resistance (R PB) presented by the on-chip power bus, and the capacitance (C DEC) and resistance (R DEC) associated with the decoupling path. Fig. 1b provides the corresponding frequency-dependent impedance profile for the PDN, as seen from the perspective of the on-chip circuitry. Fig. 1. Simplified representation of the DRAM PDN. Corresponding frequency-dependent impedance profile. By applying fundamental circuit theory to this simple model, the components contributing to the low, high and mid-range frequency response of the PDN can be identified. First, the differential low frequency impedance, looking out from the circuitry, is determined by shortcircuiting the inductances, while open-circuiting the capacitances, which results in a residual impedance value of 2R PB+2R SYS. In a similar way, the high frequency differential impedance, determined by short-circuiting the

capacitances and open-circuiting the inductances, is found to be 2R PB+R DEC. Over the mid-range frequencies, the impedance profile comes to a peak at the point where the impedance incline associated with the series inductance (2 2π L SYS) intersects with the impedance decline associated with the bypass capacitance (1/(2π C DEC)). A more thorough evaluation of the PDN network of Fig. 1a reveals the transfer function captured in eqn 1. It is based on this equation that the quality factor (Q), which helps define the nature of the peaking behavior, is calculated and found to indicate that the peak PDN impedance can be reduced through inductance minimization (e.g., shorter package leads, power planes in the package and/or module, etc.) or through increasing the amount of decap. Further consideration of the Q shows that the peaking is also sensitive to the effective or equivalent series resistance (ESR) residing in the path of the high-frequency LC loop (R SYS and R DEC). It is also noted that the resistance separating the circuitry from the nearest decap (R PB) does not provide any benefit in terms of resonance damping, leading to the recommendation that decap be placed as close to the target circuit as possible. III. RESONANCE MITIGATION Based on the discussion above, and demonstrated in Fig. 2, an early attempt to tune the amount of decapassociated ESR (referenced above as R DEC) consisted of numerically searching for the resistance value which would minimize the maximum PDN impedance over all frequencies for a given combination of L SYS and C DEC. As shown, when the ESR is increased from 1-Ω to about 6-Ω, the peaking quickly disappears, but the impedance above the resonant frequency increases substantially and eventually dominates the response. For the case shown, the algorithm determined that an ESR of approximately 5- Ω would provide the lowest overall impedance. Fig. 2. Frequency-domain-centric ESR optimization. (1) (2) + (3) Because the negative aspects of this approach (e.g., increased PDN impedance at high frequencies) were difficult to indentify in the frequency domain, an alternate time-domain ESR-optimization methodology was developed. In this second technique, the frequency response of the PDN was translated into a corresponding impulse response through the Laplace Transform (See eqns. 2-4, which indentify the formats of the over-damped, under-damped and critically-damped PDN responses, respectively. The coefficients are removed for clarity.). The impulse response was then excited by a data pattern designed to stimulate the PDN at the calculated resonant frequency, as well as at a variety of frequencies related to the target DRAM operation (e.g., standard-specified datarates, etc.). Mathematically this was accomplished by convolving the PDN stimulus vector with the derived, parameterized impulse response. Fig. 3. Exemplary results from the time-domain-centric ESR optimization. As an example, Fig. 3 presents the estimated power and ground noise in a DDR configuration for three levels of ESR. The red curve, resulting from a particular amount of ESR, labeled here as ESR-C, clearly demonstrates a resonant response early in the pattern, while ESR-A and ESR-B exhibit less sensitivity. While this time-domaincentric ESR-optimization approach was found to improve the PDN s transient response, it still led to a trade-off between the resonance and high-frequency noise minimization. To resolve this, the decoupling connectivity would need to be altered. IV. PROPOSED DECOUPLING STRATEGY As the high-frequency PDN impedance is set primarily by the ESR, intuitively, a low-esr parallel path may be added to lower the combined decoupling impedance at (4)

higher frequencies. The schematic presented in Fig. 4 indicates that these two decoupling paths should be connected in parallel between the power rails of the offchip signaling domain. C RF (resonant frequency) is generally a large capacitance intended to lower the overall PDN impedance over mid-range frequencies. R DAMP is connected in series with C RF and is tuned to dampen any anticipated resonant behaviors based on the time-domaincentric ESR-optimization method presented in section III. C HF (high frequency) provides an additional low impedance decoupling path at frequencies above resonance. C CROSS is placed near the voltage domain boundary and is intended to smooth the boundary crossing by reducing the local noise on the internal domain. Fig. 5 demonstrates the effectiveness of the proposed topology. In this case, the value of R DAMP is held constant at 4-Ω, while the ratio C RF/C HF is varied. The legend in the figure represents the ratio, while the total equivalent capacitance was fixed at 350-pF. It is observed that when 100% of the capacitance is captured by C RF, there is a residual high-frequency impedance of 4-Ω, but as the contribution of the parallel, low ESR, path increases, the asymptotic behavior of the high-frequency impedance is eliminated. While there is a corresponding increase in the peak impedance near 100-MHz, were the R DAMP value removed, the impedance peak would scale by orders of magnitude. Thus, it is shown that both the mid-range and high-frequency response of the PDN may be enhanced through the proposed decoupling scheme. The enhancement achieved by the proposed network is more clearly demonstrated through time-domain simulation. Fig. 6a presents the impedance profiles for a variety of combinations of C RF + C HF, and fixed R DAMP (the legend reports the absolute capacitance of the two parallel branches). Fig 6b captures the resulting time-domain responses of each PDN profile, with corresponding colors between the two sub-figures. The bottom window in Fig. 6b presents the current demand under two distinct circuit operations, with black and pink representing continuous and bursty memory READ operations, respectively. The top window of Fig. 6b presents the resulting differential noise observed across the PDN near the point of stimulus for the continuous READ operation. Notice that the noise repeats at a relatively high frequency, corresponding to the on-chip clock frequency, which in this case was 800-MHz. This fundamental component of the clock is also identified in Fig. 6a by the small, dashed oval on the right. Note that the impedance represented by the light green curve, associated with the 50-pF/11-Ω decoupling is significantly larger at, and above, 800-MHz, and the resulting timedomain noise reflects that distinction. Fig. 4. Recommended decoupling connectivity in the DRAM I/O region. VSSQ and VSS are shorted by default. Fig. 5. Impact of the CRF/CHF ratio on the mid-range and high-frequency PDN impedance. Fig. 6. Impedance profiles for a variety of CRF+CHF combinations. Corresponding simulated time-domain behavior.

In contrast, the noise profile captured in the middle window of Fig. 6b corresponds to the bursty READ operation, in which the burst frequency was chosen to align with the anticipated 200-MHz resonance. Comparison of the impedance profiles in Fig. 6a would predict significantly larger noise for the PDN combination represented in red, and the time-domain results validate that prediction. By comparison, as the value of C RF is increased, the PDN appears less sensitive to the bursty READ pattern, yet does not degrade under the continuous pattern either, which is the intent of the proposed strategy. Were the value of C RF to be increased, without the C HF path in place, the noise generated by the continuous READ condition would not improve. V. SILICON VALIDATION To verify the effectiveness of the proposed decoupling scheme, a set of experiments were run on the V89C DDR3. Before defining the experiments, the potential for PDN resonance in the V89C was estimated based on the reported effective CRF, CHF, RDAMP and power loop inductance for the I/O voltage domain. These were determined to be 306-pF, 139-pF, 5-Ω and 1.5-nH, respectively, leading to an anticipated potential resonance near 195-MHz. Using these values, a resonance-exciting data pattern was derived. To ensure that any potential resonance in the 100s of MHz range would be stimulated, a READ pattern was developed in which all of the I/O lines are fundamentally driven with an alternating pattern, but with varying numbers of No-Operations (NOOPs) inserted between the READ bursts. Fig. 7a illustrates the stimulus vector for three distinct NOOP settings (0, 8 and 16 NOOPs between 8-bit bursts). The corresponding signal energy spectrum is presented in Fig. 7b along with the anticipated resonant frequency. It is observed that sweeping the number of inserted NOOPs effectively spreads the signal energy over a wide band of mid-range frequencies encompassing the anticipated resonance. Fig. 7. Subsets of the NOOP-sweep data pattern. Illustration of the corresponding spread spectrum signal energy. The anticipated VCCQ domain resonant frequency is indicated in red, and the clock fundamental and third harmonic are identified for reference. Fig. 8. Placeholder data not taken from actual experimental silicon. Fig. 8 reports the corresponding change in timing margin versus burst frequency (data shown is a placeholder). TBD VI. CONCLUSION Special thanks to ACKNOWLEDGMENT REFERENCES [1] S. Sun, L. D. Smith, and P. Poyle, On-chip PDN noise characterization and modeling, Proceedings of DesignCon, Feb., 2010. [2] S. Naffziger, Supply grid design and analysis, Signal and Power Integrity for SoCs Forum, IEEE International Solid State Circuits Conference, Feb. 11, 2011. [3] T. M. Hollis, S. Bodily and B. A. Millemon, Decoupling techniques and recommendations for enhancing power delivery, Micron Internal Design Seminar, Sept. 30, 2009.

T. M. Hollis received the B.S. degree in electrical engineering from the University of Utah, Salt Lake City, UT, in 2003 and the Ph.D. degree in Electrical Engineering from Brigham Young University, Provo, UT, in 2007, where his graduate work focused on channel equalization and jitter attenuation circuits for high-speed serial interconnects. As a graduate student he interned with Micron Technology, Inc., Boise, ID, and Intel Corporation s Circuit Research Laboratory, Hillsboro, OR. Following graduation he joined Micron s Advanced Architecture Group, where his duties have included I/O circuit design and signal integrity and power delivery analysis for multi-gigabit-per-second memory interfaces. He is currently a Senior Member of the Technical Staff and holds 25 issued patents (24 pending).