November 1, 2005 Analog Devices AD7658 Analog to Digital Converter icmos Process Technology Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
Process Review Table of contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Major Findings 2 Package and Die 2.1 Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Double Poly MIM Capacitors 3.7 Poly Resistors 3.8 MOS Transistors 3.9 Isolation 3.10 Lateral PNP Bipolar Devices 3.11 Diodes 3.12 Wells, Epi and Substrate 3.13 High Voltage MOS Transistors 4 References 5 Critical Dimensions 5.1 Package and Die 5.2 Vertical Dimensions 5.3 Horizontal Dimensions Report Evaluation PPR-0510-901 November 1, 2005
Overview 1-1 1 Overview 1.1 List of Figures 2 Package and Die 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Pin Diagram 2.1.4 Package x-ray Top-View 2.1.5 Package x-ray Side-View 2.2.1 Die Photograph 2.2.2 Die Markings 2.2.3 Die Photograph at Metal 1 2.2.4 Die Photograph at Poly 2.2.5 Annotated Die Photograph 2.3.1 Die Corner a 2.3.2 Die Corner b 2.3.3 Die Corner c 2.3.4 Die Corner d 2.3.5 Minimum Pitch Bond Pads 2.3.6 Single Bond Pad 3 Process 3.1.1 General Structure 3.1.2 Die Edge 3.1.3 Die Edge Seal 3.2.1 Ball Bond to Bond Pad 3.2.2 Bond Pad Edge 3.2.3 Bond Pad Edge Detail 3.3.1 Dielectrics General Structure 3.3.2 Passivation 3.3.3 IMD 2 3.3.4 IMD 1 3.3.5 PMD 3.3.6 PMD and LOCOS Isolation 3.4.1 Metallization General Structure 3.4.2 Minimum Pitch Metal 3 3.4.3 Minimum Pitch Metal 2 3.4.4 Minimum Pitch Metal 1
Overview 1-2 3.5.1 Vias and Contacts General Structure 3.5.2 Minimum Pitch Via 2s 3.5.3 Minimum Pitch Via 1s 3.5.4 Minimum Pitch Contacts to Substrate 3.5.5 Contact to Poly 2 3.5.6 Contacts to Poly 1 3.6.1 Poly MIM Capacitors and Poly Resistors 3.6.2 Poly MIM Capacitor 3.6.3 Contact to Poly MIM Capacitor Detail 3.6.4 Interpoly Dielectric and Cap Oxide 3.7.1 Poly Resistors 3.7.2 Poly Resistor Contact 3.7.3 Poly Resistor Pitch 3.7.4 Poly Resistor Pitch Detail 3.8.1 Minimum Gate Length NMOS Transistor 3.8.2 Minimum Gate Length PMOS Transistor 3.8.3 MOS Transistors (Glass-Etch Only) 3.8.4 Minimum Pitch NMOS Transistors 3.8.5 Minimum Pitch PMOS Transistors 3.8.6 NMOS Transistor with Double Contact Plan-View 3.8.7 NMOS Transistor with Double Contact 3.8.8 Large NMOS Transistor 3.9.1 Minimum Width LOCOS Isolation 3.9.2 Poly over Minimum Width LOCOS Isolation 3.9.3 Poly over LOCOS Isolation 3.10.1 PNP Device at Metal 3 Plan-View 3.10.2 PNP Device at Poly Plan-View 3.10.3 Large PNP Device (Cross-Section 5) 3.10.4 Large PNP Device Detail (Cross-Section 5) 3.10.5 Large PNP Device SCM (Cross-Section 9) 3.10.6 Small PNP Devices SCM (Cross-Section 8) 3.10.7 Small PNP Device Detail SCM (Cross-Section 8) 3.11.1 Diodes at Metal 3 Plan-View 3.11.2 Diode (Cross-Section 2) 3.11.3 Diode SCM 3.11.4 Diode Detail SCM
Overview 1-3 3.12.1 Well and Epi Structure 3.12.2 Shallow Wells SCM 3.12.3 SRP of P-Well 3.12.4 SRP of N-Well 3.13.1 HVMOS Transistors Plan-View 3.13.2 HVMOS Transistors Detail Plan-View 3.13.3 HVNMOS Transistor Overview 3.13.4 HVNMOS Transistor 3.13.5 HVNMOS Transistor Contact to Gate Spacing 3.13.6 HVNMOS Transistor Gate Oxide 3.13.7 HVNMOS Transistor SCM 3.13.8 HVNMOS Transistor SCM Detail 3.13.9 HVPMOS Transistor Overview 3.13.10 HVPMOS Transistor 3.13.11 HVPMOS Transistor Contact to Gate Spacing 3.13.12 HVPMOS Transistor Gate Oxide 3.13.13 HVPMOS Transistor SCM 3.13.14 HVPMOS Transistor SCM Detail
Overview 1-4 1.2 List of Tables 1 Overview 1.5.1 Device Summary 1.6.1 Summary of Major Findings 2 Package and Die 2.3.1 Package and Die Dimensions 3 Process 3.3.1 Dielectric Composition and Thicknesses 3.4.1 Metallization Composition and Thicknesses 3.4.2 Minimum Metals Horizontal Dimensions 3.5.1 Via and Contact Horizontal Dimensions 3.8.1 Transistor and Polysilicon Horizontal Dimensions 3.8.2 Transistor and Polysilicon Vertical Dimensions 3.9.1 Isolation Horizontal Dimensions 3.12.1 Wells and Epi Vertical Dimensions 3.13.1 HV Transistor and Polysilicon Horizontal Dimensions 3.13.2 HV Transistor and Polysilicon Vertical Dimensions 5 Critical Dimensions 5.1.1 Package and Die Dimensions 5.2.1 Vertical Dimensions 5.3.1 Horizontal Dimensions
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