Elpida Memory Inc. B240ABB (die markings), MC77-LL/A (package markings) 46 nm Mobile / Low Power DDR2 SDRAM DRAM Process Report - Preliminary Table of Contents
3 Table of Contents Introduction Major Findings Device Identification Package Photographs Die Photograph and Die Markings General Structure Die Efficiency Calculation Die Delayered to Metal 1 Description of Directions Wordline Direction (SEM) Bitline Direction (SEM) Detailed Structure Bitline Direction RCAT and Silicon Plugs (SEM) RCAT and Silicon Plugs (TEM) Capacitor Bottom Region (TEM) RCAT and Silicon Plugs (TEM, 2) Bitline Contact (TEM) RCAT and Silicon Plugs (TEM, 3) RCAT (TEM) RCAT (TEM, 2) Detailed Structure Wordline Direction RCAT (SEM) Capacitor Contacts (SEM) Bitline Contacts (SEM)
4 Table of Contents (continued) Memory Capacitor Structure Cross Section Wordline Direction (SEM) Capacitor Top Wordline Direction (TEM) Capacitor Top Wordline Direction (TEM, 2) Capacitor Bottom Wordline Direction (TEM) Memory Cell Layout Active Regions at Block Edge (SEM) Calculation of Cell Area Active Regions and RCAT at Block Edge (SEM) Wordlines (SEM) Wordlines, Silicon Plugs, and Bitline Contacts (SEM) Bitlines (SEM) Capacitors at Block Edge (SEM) Square Gap Pattern Near Capacitor Top at Two Magnifications (SEM) Capacitors at Top in Cutout Region (SEM) Active Regions (TEM) Active Regions and RCAT (TEM) Active Regions and RCAT (TEM, 2) Active Regions, RCAT (Wordline), and Silicon Posts (TEM) Active, Wordline, and Silicon Posts (TEM) Wordline and Silicon Posts (TEM) Bitline Contacts and Posts (TEM) Bitline, Bitline Contacts, and Capacitor Contact Posts (TEM) Bitlines and Wordlines (TEM) Capacitor Contact Post, Capacitor Offset Post, and Capacitor Bottom (TEM) Capacitor Offset Post and Capacitor Bottom (TEM) Capacitor Lower Region (TEM) Capacitor Middle Region (TEM) Capacitor Upper Region (TEM) Capacitor Upper Region (TEM, 2)
5 Table of Contents (continued) Memory Cell Layout (continued) Capacitor Top Region Etch Mask (Capacitor Retainer, TEM) Square Gap Pattern Near Capacitor Top (TEM) Capacitor Upper Region and Materials Analysis Dark Field STEM Capacitor Upper Region and Materials Analysis (TEM) Logic Between Memory Blocks Sense Amplifier at the Gate Level (SEM) Wordline Drivers at the Gate Level (SEM) Gate with Thin Gate Dielectric in Sense Amplifiers (TEM) Gate with Thin Gate Dielectric in Sense Amplifiers and Gate Dielectric Image (TEM) Gate with Thick Gate Dielectric in Sense Amplifiers and Gate Dielectric Image (TEM) Gate Stack Used in all Gates Including the Wordlines (TEM) Miscellaneous Images Passivation (TEM) Metal 3 Aluminum (TEM) Metal 2 Copper (TEM) Meal 1 Tungsten (TEM) Contacts (TEM) Gate Width Direction Thin and Thick Gate Dielectrics (TEM) Stacked Contacts (TEM) Top Plate Contact (TEM) Periphery Transistors Silicon Stain (SEM) Statement of Measurement Uncertainty and Scope Variation About Chipworks
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