Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing

Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing 1 Xiaofei Wang, 2 John Keane, 2 Pulkit Jain, 3 Vijay Reddy and 1 Chris H. Kim 1 University of Minnesota, Minneapolis, MN 2 Now at Intel Corporation, Hillsboro, OR 3 Texas Instruments, Dallas, TX xfwang@umn.edu www.umn.edu/~chriskim/ 1/18

Purpose Explore the impact of asymmetric BTI aging on circuit performance Measure the duty-cycle degradation using the silicon odometer framework Study duty-cycle degradation impact on SRAM timing 2/18

Outline Introduction to asymmetric BTI aging and its impact on different circuits Measurement method and test chip results Asymmetric aging impact on SRAM timing Summary 3/18

Asymmetric BTI Aging Effects INPUT 0 1 0 1 OUTPUT 770 T=1ns 1.2V, 65nm LP, 20 C 60 Idle INPUT : OUTPUT: : NBTI t d T No degradation t d : PBTI Active Duty-Cycle=50% Duty-Cycle>50% Delay degrdation Delay (ps) 720 670 620 570 1 st Edge Delay (t d ) 520 0 10 20 V t Shift (%) When input is static, PMOS and NMOS in a signal path are alternately stressed In active mode, the 1 st edge propagates through unstressed devices only 2 nd edge propagates through stressed devices only 50 40 30 20 Duty-Cycle (%) 4/18

Case 1: Local Clock Buffer Aging Duty-Cycle =50% Duty-Cycle 50% PLL Grid En LCB Asym. Aging Global Grid Local Clocking The local clock buffer (LCB) is stressed when global clock signal is gated off clock duty-cycle change Impact on duty-cycle can be small especially if leaflevel gating logic is implemented 5/18

Case 2: Logic Path Aging While clock is gated, the logic path undergoes DC BTI stress Increased logic delay lowers the operating frequency 6/18

Case 3: SRAM Timing Path Aging Internal timing signal paths for SRAM operation are DC stressed when clock is gated off Affects the duty-cycle of critical signals such as WL, SAE, precharge, etc. lower operating frequency 7/18

Prior Work on Asymmetric BTI Aging Product drift from NBTI: Guardbanding, circuit and statistical effects (A. Krishnan, et al., IEDM 2010) Experimentally shows the half-cycle paths under clock gating are more sensitive to transistor degradation Derive formulas to calculate the additional guardband required for the asymmetric aging A TDC-based test platform for dynamic circuit aging characterization (M. Chen, et al., IRPS 2011) Proposed an on-chip TDC-based technique to measure delay degradation Failure analysis of asymmetric aging under NBTI (J. Velamala, et al., TDMR 2012) Proposed a failure diagnosis method for predicting timing violations None of the previous work reported duty-cycle shift data 8/18

Silicon Odometer Beat Frequency Scheme T. Kim, et al., JSSC, 2008 Beat frequency of two free running ROSCs measured by DFF and edge detector Benefits of beat frequency detection system Achieve ps resolution with μs measurement interrupt Insensitive to common mode noise such as temperature drifts Fully digital, scan based interface, easy implementation 9/18

Silicon Odometer Beat Frequency Scheme stress ref ref beat ref stress stress Sample stressed ROSC output with reference ROSC 1% frequency difference before stress N=100 2% frequency difference after stress N=50 f or T sensing resolution is 0.01% 10/18

Using Frequency Data to Calculate Duty-Cycle V stress 0 1 0 : NBTI : PBTI V dd 0 1 0 T CLK Stress Mode Measurement Mode 75 70 1.2V, 65nm LP, 20 C Actual Calculated Duty-Cycle Shift (%): t d = T CLK t d : Propagation delay T (2 ROSC ) T ROSC t d Measured 100 T 50 CLK period shift Use ROSC period degradation to calculate duty-cycle shift under the same amount of stress 65 60 55 t d =540ps T CLK =1.0ns 0 5 10 15 20 V t Shift (%) 11/18

65nm Test Chip Die Photo and Features 12/18

Hardware Results from Test Chips Duty-Cycle (%) 57 56 55 54 53 52 51 2.2V 2.2V 2.2V 2.0V 1.8V T CLK =1ns, t d =0.5ns 1.2V, 65nm LP 140 C 80 C 20 C 20 C 20 C Duty-Cycle (%) 1.2V, 65nm LP stressed @ 2.2V, 80 C 70 T CLK, t d : 0.5ns, 1ns 65 : 1ns, 1ns : 1ns, 0.5ns 60 55 50 10 3 10 5 10 1 Stress Time (s) 50 10 1 10 3 10 5 Stress Time (s) Duty-cycle increases with higher stress voltage and temperature Duty-cycle shift is inversely proportional to T clk, and linear with t d 13/18

Occurrences (%) Statistical Data from Test Chips 1.2V, 65nm LP, Stressed @ 2.2V, 20 C 35 100s 1Ks 10Ks 30 25 20 15 10 5 0 51 52 53 54 55 56 57 58 Duty Cycle (%) Occurrences (%) 35 30 25 20 15 10 5 0 1.8V 1.2V, 65nm LP, Stressed 3.1hrs @ 20 C 2.0V 2.2V 51 52 53 54 55 56 57 58 Duty Cycle (%) Duty-cycle distribution with the sample size of 80 are measured Duty-cycle distribution spreads out as the mean value increases with a higher stress voltage and longer stress time 14/18

SRAM Array Configuration CLKG Add<n> Predecoder Word Driver WL<m> 256 Clock gate Enable CLK 128 Bank0 Col. Ckt Bank2 RowDec Ctr RowDec CLKG Bank1 Col. Ckt Bank3 BL WL PRE YSEL X256 BLB SA OUT Read Path SAEN DOUT Clock cycle = random cycle Clock gating technique is used to turn off the clock when set in idle Four banks, 256X128 for each bank, f=2.0ghz 15/18

SRAM Timing Duty-Cycle Shift WL Enable Pre-decoder Decoder Driver CLK Clock Gater : NBTI : PBTI SRAM Ctrl Timing Gen. Paths PRE, SAEN, YSEL, etc. After stress Phase 1 Phase 0 Address Decoding WL Driving BL/BLB Discharging SA Sensing BL Precharging Data Latching Asymmetric BTI aging during idle mode affects the internal control cycles in the next active mode Operation cycle of phase 1 is extended, but phase 0 is shorter 16/18

Voltage (V) 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 Impact on SRAM Read-after-Write BL 65nm LP, 80 C, 512X256 SRAM Subarray CLK PREB BLB YSELB WL SAOUTB : Fresh : 20% V t Shift SAEN SAOUT DOUT 1.75n 2n 2.25n 2.5n 2.75n Time (s) Operation Duty-Cycle (%) 1.2V, 65nm LP stressed @ 2.2V, 140 C 55 50 45 40 WL PRE 750 745 740 735 730 35 725 CLK DOUT 30 720 10 1 10 3 10 5 10 7 Stress Time (s) Delay (ps) Narrower precharge phase Sense amplifier enable is delayed Clock-to-data delay worsens 17/18

Summary The odometer framework is utilized to measure the duty-cycle shift due to DC BTI aging Beat-frequency detection system is adopted for high measurement precision and short measurement time Simple calculation translates ROSC period shifts to dutycycle shift Experimental results are shown under different stress conditions The impact of the DC BTI aging on SRAM timing is studied for the first time SRAM read speed degrades due to the extended WL enable phase 18/18