Lecture 3 Biasing and Loading Single Stage FET Amplifiers The Building Blocks of Analog Circuits III In this lecture you will learn: Current biasing of circuits Current sources and sinks for CS, CG, and CD circuits A Poor Man s Current Source What if one wanted to bias a device with a current source? R D but one only had a voltage source? Solution: Use a large voltage source with a large resistor in series! I BIAS R R D Poor man s current source BIAS BIAS I R RD R
The Common Source Amplifier DD R R S v s BIAS v out Open circuit voltage gain: v i R A out d v gm ro R v v in in The Common Source Amplifier: Problems Open circuit voltage gain: v A out v gm ro R v in In saturation: I g D m GS knid nds To achieve large gain one needs: ) A large DC current bias in order to get a large g m ) A large value of the resistor R Both the above requirements cannot be met easily simultaneously: Not easy to realize large resistors in michips A large resistor R will limit the maximum value of the DC current bias (because the potential drop R can become large enough to put the FET in the linear region where g m and the gain will be small)
The Digital Logic Inverter: Problems DD Saturation IN TN Cutoff Linear TN IN To achieve fast switching one needs: ) A small resistor (because then the RC L charging time will be smaller when the output switches from to ) But A small resistor will require a very large current (to achieve a large potential drop across it) when the input is, and the is turned on, and the output need to be low or and this means more power dissipation When the input is, and the is turned on, there is constant static power dissipation The Common Source Amplifier with a Current Source DD R S What is needed is an ideal current source in the drain that can supply a large DC current and at the same time has a large small signal resistance v s BIAS v out The incremental (or differential or small signal) resistance looking into an ideal current source is infinite v A out v gmro vin An ideal current source, of course, does not exist But one can certainly do much better than using a resistor in the drain 3
The Common Source Amplifier with a Current Source: DC Biasing I D W IBIAS n Cox GS TN L n DS Suppose for BIAS the output was g m BIAS Suppose BIAS is changed to a smaller value BIAS BIAS = BIAS BIAS < The output can be obtained graphically, as shown DS The Common Source Amplifier with a Current Source: DC Biasing 4
The CS Amplifier with a Current Source: Small Signal Analysis i g Gate Drain i d v in v gs Source g m v gs Base g mb v bs v bs r o v out Open circuit voltage gain: A v v v out in g r m o Large Output resistance: Rout r o Large Large Signal Model of a Current Source Large signal circuit model The output resistance of the current source Ideal current source A current source A large signal model of a current source is large for a good current source and infinite for an ideal current source IBIAS Slope d d One can have any voltage at the at the output terminals of a good current source and the current delivered will remain mostly constant 5
Small Signal Model of a Current Source IBIAS Slope d d Large signal circuit model The output resistance of the current source Ideal current source IBIAS Small signal circuit model A current source Large Signal Model of a Current Sink Large signal circuit model The output resistance of the current sink Ideal current source A current sink A large signal model of a current source is large for a good current source and infinite for an ideal current source IBIAS Slope di d One can have any voltage at the at the output terminals of a good current sink and the current dinked will remain mostly constant 6
Small Signal Model of a Current Sink IBIAS Slope di d Large signal circuit model The output resistance of the current source Ideal current source IBIAS Small signal circuit model A current sink Loaded Common Source Amplifier DD A approximation to a current source B DD A load v s BIAS R S v out v s BIAS R S v out An ideal current source, of course, does not exist But one can certainly do much better than using a resistor in the drain Use a! 7
Current Sink: Current Sinks and Transistors Slope di d I I One can have any voltage at the at the output terminals of a good current sink and the current sinked will remain mostly constant Slope d go d ro B Characteristics in saturation resemble that of a nonideal current source! Current Sources: Current Sources and Transistors I I Slope d d One can have any voltage at the at the output terminals of a good current source and the current delivered will remain mostly constant Slope d g o d r o B Characteristics in saturation resemble that of a nonideal current source! 8
Loaded : Large Signal Analysis M M B BIAS DS DS ID ID ID DD DC value of the output voltage (Both FETs in saturation) DD Instead of the resistive load line, we now have the full vs DS curves of the The biasing voltages need to be selected carefully, otherwise one of the transistors can go into the linear region!! Loaded : Large Signal Analysis B M = M BIAS DS DS ID ID ID DD DC value of the output voltage ( in the linear region) DD Instead of the resistive load line, we now have the full vs DS curves of the PMOS The biasing voltages need to be selected carefully, otherwise one of the transistors can go into the linear region!! 9
Loaded : Large Signal Analysis M M Assuming the biasing is correct, both the FETs are in saturation Equate the drain current magnitudes of the two FETs Then the only unknown will be ; solve for it kn k ID GS TN n DS BIAS TN I D kp Equating: I D I k n D n I n p GS TP erify that the obtained value of does indeed result in both the transistors being in saturation p DS k B DD TP p p BIAS D TN n k B DD TP p DD DD Loaded : Transfer Curve M I: IN < TN M cutoff II: IN > TN & > IN TN & > B TP M saturation, M Linear M III: IN > TN & > IN TN & < B TP M saturation, M saturation I: IN > TN & < IN TN & < B TP M linear, M saturation II IN TN DD B TP III Increasing IN I B I III I II TN IN I
Loaded : Small Signal Analysis M i g Gate v gs g m vgs Drain r o i d M Source Looking into the drain end of the, what does one see? i g Gate Drain i d R S v s v in v gs Source g m v gs r o v out PMOS Loaded NMOS: Small Signal Analysis M Drain i d r o M Looking into the drain end of the, what does one see? i g Gate Drain i d R S v s v in v gs Source g m v gs r o v out
Loaded : Small Signal Analysis i g i d M M v in v gs g m v gs r o r o v out Open circuit voltage gain: Av v out vin g m r o r o Output resistance: R out r o r o Loaded : The Cascode Load DD DD load R D Better load B3 M3 B M B M v s BIAS R S M v out v s BIAS R S M v out This load has a larger resistance looking into it This topology is called the Cascode current load
Cascode PEFT Load: Small Signal Analysis load 3 i g3 Gate3 v gs3 g m 3vgs3 Drain3 i d 3 r o3 Source3 i g Gate Drain i d v gs g m v gs r o Source Cascode Load: Small Signal Analysis Drain3 i d 3 load 3 r o3 i g Gate Drain i d v gs g m v gs r o Source 3
Cascode Load: Small Signal Analysis i g Gate Drain i d load 3 v gs g m v gs r o Source r o3 Resistance looking into the current source is: g r g r r 3 ro ro3 gmroro 3 ro ro3 m o m o o Typically a good approximation Cascode Load: Small Signal Analysis load ro ro3 gmro 3 g r r m o o3 i d Resistance looking into the current source is: g r g r r 3 ro ro3 gmroro 3 ro ro3 m o m o o Typically a good approximation 4
Cascode Load: Small Signal Analysis i g i d load v in v gs g m v gs r o g r r m o o3 v out Open circuit voltage gain: v A out v vin Output resistance: r g r r 3 g r gm o m o o m o Typically a good approximation Rout g r r 3 r ro m o o o Typically a good approximation The Common Source Amplifier: General Topology IN IN is the most positive voltage in the circuit is the most negative voltage in the circuit Large input resistance Large output resistance Large voltage gain Large current gain 5
The Common Gate Amplifier: General Topology IN G G IN IBIAS Can have small input resistance Large output resistance Large voltage gain Small (unity) current gain The Common Drain Amplifier: General Topology IN IN Large input resistance Small output resistance Small (less than unity) voltage gain 6
ChipBased Current Sources and oltage Sources We have realized a decent load but How does one generate voltage levels on a chip for biasing?? Current and voltage biasing of circuits require transistor based current and voltage sources on a chip! What are the good figures of merit of chipbased voltage and current sources? 7