Fast Dynamic Parallel Data Interface for the NGD RF Driver

Transcription

1 Introduction The NGD series of Acousto-Optic RF Drivers are capable of fast dynamic control of frequency, output power level, and relative phase or delay (Channel #2 relative to Channel #1). The rear panel 68-pin MDR connectors are used for this dynamic control. This document defines the control signaling protocol and pin assignments. There are two MDR connectors, one for each independent channel. For MUX Option NGD units, only a single connector (Channel 1) is used to control both channels, which are simultaneously programmed through the single interface connection. Frequency Control The User must calculate a Frequency Tuning Word (FTW), given by the formula: FTW = F OUT F CLK 2 20 Eq. 1.0 where: FOUT = Desired RF frequency in MHz FCLK = 1,000MHz Equation 1.0 calculates the FTW in decimal format, which must be converted to a 20-bit binary word that is applied to the parallel interface using TTL logic levels. MSB (Most Significant Bit) = Pin #54. All inputs and outputs are TTL levels: VOH = 2.7V, VIH = 2.0V, VIL = 0.8V, VOL = 0.4V. Example: Desired frequency = 107.5MHz FTW = (107.5/1000) 2 20 = (0.1075) 1,048,576 = 112, = 112,722 Taking this integer value and converting to binary format: FTW = MSB LSB This binary word is applied to even-numbered Pins #2 20 and #38 54 as shown in the Table 1. 1 P a g e R e v i s i o n 3. 0 O c t o b e r

2 Table 1. Pin Assignments FTW Programming Pin Number Input / Output Assignment Even Pins #2 20 FTW[e]: Even bits 0 18 Even Pins #36 54 FTW[o]: Odd bits 1 19 Even Pins #22, 24 MUX[1,0] Mux Bits: Set to (1,1) Even Pin #26 Spare Input 4 Even Pins #56, 58 Spare Inputs 1, 3 Pin #28 Trigger Input Pin #60 Latch Input MUX Bits Pins #22 and 24 are, respectively, MUX bits [1,0] and serve to define the functionality of the Latch Input (Pin #60). The Latch Input pin is physically separated from the MUX and data pins to ensure robustness of the interface in electrically noisy environments. NOTE: When MUX bits [1,0] are set to 0,0 the Latch Input is disabled, and the NGD cannot be programmed. Table 2. MUX Bit Definitions Function Bit 1 Pin 22 Bit 0 Pin 24 Latch Disable / No Program 0 0 ACW Input Amplitude Program 1 0 PCW Input Phase Program 0 1 FTW Input Frequency Program P a g e R e v i s i o n 3. 0 O c t o b e r

3 Amplitude Control The NGD uses a 14-bit amplitude control word (ACW), which provides 42dB of control range, defined as follows: Amplitude Control Word (ACW): (minimum power) (maximum power) 0x0000 to 0x3FFF (hex equivalent) Code 0x0000 will cause complete RF blanking, with >55dB of RF extinction or blanking under nominal conditions. Note that the ACW translates direct to voltage, and the equivalent RF power scales as the square of voltage. MSB (Most Significant Bit) = Pin #48. Table 3. Pin Assignments ACW Programming Pin Number Input / Output Assignment Even Pins #2 14 ACW[e]: Even bits 0 12 Even Pins #36 48 ACW[o]: Odd bits 1 13 Even Pins #22, 24 MUX[1,0] Mux Bits: Set to (1,0) Even Pin #26 Spare Input 4 Even Pins #56, 58 Spare Inputs 1, 3 Pin #28 Trigger Input Pin #60 Latch Input The NGD utilizes internal Amplitude and Phase Compensation Arrays, which are stored in non-volatile memory. The ACW is used in conjunction with the Amplitude Compensation Array to deliver a specified amount of RF power at a specific frequency depending on the end-use application. In this context, maximum power or 0x3FFF, will provide 100% of the compensated power as defined in the Array. Reducing the ACW by 50%, to 0x1FFF from 0x3FFF, will reduce the voltage amplitude by 50%, and the RF power by 75%, or reduced by 6dB. These are guidelines, as actual delivered power performance will depend on a number of variables. 3 P a g e R e v i s i o n 3. 0 O c t o b e r

4 Phase Control The NGD uses a 9-bit Phase Control Word (PCW), which provides about 1.4 of resolution over the range of 0.0 to 360 of total phase control range, defined in the table below. Offset binary format, or excess-k representation is used with K = 256. The PCW is calculated by: PCW = INT ( Example: Desired phase shift = 101 Phase ) then converting to binary Eq. 2.0 PCW = (101 x 256)/360 = = 72 (rounded to the nearest integer) Conversion to Offset Binary: PCW = = 328 = (b) = 0x148 (hex) Decimal Phase( ) Offset Binary Hex Decimal FD FE FF 511 Note: The MSB (connected to Pin #10) is always set to 1 for positive phase angles. Do not set this Pin to 0. 4 P a g e R e v i s i o n 3. 0 O c t o b e r

5 Note that Phase Control is only possible when the RF frequency is the same for both output channels. A programmed phase shift of zero degrees does not provide an observed phase of zero between the two RF outputs, as there may be a residual phase shift due to RF path length differences. MSB (Most Significant Bit) = Pin #10. NGD units equipped with the MUX Option require only one cable connection to the Channel 1 rear panel MDR interface, which controls both channels simultaneously. The NGD features a Phase Compensation Array that stores pre-set phase values in non-volatile memory. Using the PCW to program a phase shift will numerically add the programmed phase value to the value stored in the Array (if populated previously). If no PCW is programmed, the NGD will otherwise use the phase value stored in the Array. Table 4. Pin Assignments PCW Programming Pin Number Input / Output Assignment Even Pins #2 8 PCW[e]: Even bits 0 6 Even Pins #36 42, 10 PCW[o]: Odd bits 1 7, MSB Even Pins #22, 24 MUX[1,0] Mux Bits: Set to (0,1) Even Pin #26 Spare Input 4 Even Pins #56, 58 Spare Inputs 1, 3 Pin #28 Trigger Input Pin #60 Latch Input 5 P a g e R e v i s i o n 3. 0 O c t o b e r

6 Dynamic Control Sequence and Timing: 25MHz Parameter Update Rate Frequency Control The NGD can be dynamically controlled to change frequency, amplitude, or phase, or any combination or sequence of these attributes. The basic timing sequence for changing frequency is shown below, for a parameter update rate of 25MHz. t CW FTW[19,0] FTW1 FTW2 LATCH t H t SU MUX[1,0] 1,1 0,0 1,1 0,0 Table 5. Timing Constraints for 25MHz Parameter Update Rate Parameter Symbol Minimum Typical Maximum Control Word Hold Time tcw N/A Latch Set-Up Time tsu Latch Hold Time th Note: MUX bits should be returned to [0,0] at end of Latch signal to prevent inadvertent parameter setting. 6 P a g e R e v i s i o n 3. 0 O c t o b e r

7 Frequency, Amplitude, and Phase Control Example: 25MHz Parameter Update Rate In this example, the NGD is commanded with a FTW, PCW, and ACW to effect changes in all three attributes. The timing constraints are as given above in Table 6. Note that the NGD will maintain a previously programmed attribute until the attribute is programmed with a new value. FTW[19,0] PCW[8,0] ACW[13,0] t CW FTW PCW ACW LATCH t H t SU MUX[1,0] 1,1 0,1 1,0 0,0 Table 6. Timing Constraints for 25MHz Parameter Update Rate Parameter Symbol Minimum Typical Maximum Control Word Hold Time tcw Note 1 Latch Set-Up Time tsu Latch Hold Time th Note 1 Note 1: Note 2: Note 3: To achieve a 25MHz update rate, tcw should be limited to a maximum of 40, and th should be limited to a maximum of 20. If these limits are exceeded, the update rate will be less than 25MHz. The Latch signal is essentially a 25MHz clock signal for the duration of the programming. MUX bits should be returned to [0,0] at end of last Latch signal to prevent inadvertent parameter setting. 7 P a g e R e v i s i o n 3. 0 O c t o b e r

8 Single Attribute Timing: 25MHz Parameter Update Rate This timing diagram illustrates a single attribute programming example, in this case amplitude. t CW LATCH t H t SU MUX[1,0] 1,0 0,0 Table 7. Timing Constraints for 25MHz Parameter Update Rate Parameter Symbol Minimum Typical Maximum Control Word Hold Time tcw N/A Latch Set-Up Time tsu Latch Hold Time th Note: MUX bits should be returned to [0,0] at end of Latch signal to prevent inadvertent parameter setting. 8 P a g e R e v i s i o n 3. 0 O c t o b e r

9 List of Possible Dynamic Control Options The NGD can be dynamically controlled using the control words in any order or possible sequence. Single commands are also possible. The NGD will hold the last programmed value of any particular attribute until reprogrammed. FTW Only FTW and ACW FTW, ACW, PCW ACW Only PCW Only ACW and PCW FTW and PCW Updates frequency only Updates frequency and amplitude Updates frequency, amplitude, phase Updates amplitude only Updates phase only Updates amplitude and phase Updates frequency and phase Latency Performance Latency is defined as the delay through the system from Latch assertion to the output attribute change. Frequency Update: Amplitude Update: Phase Update: 185 typ. 185 typ. 185 typ. For example, the delay from Latch assertion on a FTW update until the output of the new programmed frequency at the SMA RF output connector will typically be 185. When multiple attributes are programmed, each latency will be independent and initiated from the assertion of a specific Latch as defined through the MUX bits. 9 P a g e R e v i s i o n 3. 0 O c t o b e r

10 Figure 1 MDR Connector Standard Pin Assignments NOTE: This is included for reference only 10 P a g e R e v i s i o n 3. 0 O c t o b e r