Design of the circuit for FSK modulation based on AD9910. Yongjun 1,2

Transcription

1 Applied Mechanics and Materials Online: ISSN: , Vols , pp doi: / Trans Tech Publications, Switzerland Design of the circuit for FSK modulation based on AD9910 LI Jun 1,2,a, Tan qiulin 1, 2, b, YU Haiyang 1, c, Zhou Zhen 1,2, LI Jinming 2,CUI Yongjun 1,2 1 National Key laboratory for Electronic Measurement Technology, North University of China, Taiyuan ; 2 Key Laboratory of Instrumentation Science & Dynamic Measurement of Ministry of Education, North University of China, Taiyuan ; a lijunnuc@163.com, b taiyuannuc@163.com, c wsljljsw@163.com Key word: AD9910; Single-chip microprocessor; Frequency-shift keying ;Modulation Abstract: On the basis of the analysis of the AD9910,the Paper design a circuit for Frequency-shift keying (FSK) modulation. This circuit is controlled by a single-chip microprocessor MSP430F149, and can be used to generate a controllable FSK modulation signal. It can flexibly change the frequency of signal by programming the Micro Control Unit (MCU). This paper introduced the FSK modulation hardware circuit and software realization in this way. The signal is viewed by Oscillograph. Experiments show that this design is simple and highly applicable. Introduction The Frequency-shift keying transmits digital information by using Frequency changed carrier. It is a digital modulation technology which used the feature that digital signal discretely values to keying carrier frequency with the information. FSK is a modulation mode which was early used in the transmission of information, its advantages is: it is easily to achieve, it has good performance in the field of anti-noise and anti attenuation. FSK has been widely used in low-speed data transmission [1]. Direct Digital Synthesizer which is one of the key to achieve the full Digital technology is widely used in the field of telecommunications and electronic instrument now. A DDS chip mainly includes frequency control registers, high-speed phase accumulator and sine calculator. Frequency control register can load and memory the frequency control code by serial or parallel manner; And the phase accumulator accumulates phase according to the frequency control code in each clock cycle and gets a phase; the sine calculator calculates the digital sine wave amplitude through the phase. Compared with the traditional frequency synthesizer, DDS has the advantages which is lower cost, lower power consumption, higher resolution and faster transition etc. this paper introduced a FSK modulation by using the with the chip named AD9910 which is produced by ADI company [2]. 1 Design of the entire system The modulation system which is controlled by MCU is made up of PC, single-chip microcomputer chip, Interface circuit and DDS chip. The structure of system is shown in figure 1. The MCU receives baseband signal from PC, programs the internal control register of AD9910 via the serial I/O port. After that the MCU chooses the pins which are connected with AD9910 to playback the programmed internal profiles. Through the above steps the FSK modulation is completed. Fig 1 The structure of system All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-21/02/16,07:03:49)

2 Applied Mechanics and Materials Vols Design of the hardware circuit The AD9910 is a direct digital synthesizer (DDS) featuring an integrated 14-bit DAC and supporting sample rates up to 1 GSPS. The AD9910 employs an advanced, proprietary DDS technology that provides a significant reduction in power consumption without sacrificing performance. The AD9910 supports the use of profiles, which consist of a group of eight registers containing pertinent operating parameters for a particular operating mode. Profiles enable rapid switching between parameter sets. Profile parameters are programmed via the serial I/O port. Once programmed, a specific profile is activated by means of three external pins. A particular profile is activated by providing the appropriate logic levels to the profile control pins. 2.1 Design of the power circuit The AD9910 features multiple power supplies, and their power consumption varies with its configuration. The recommendations here are four groups of power supplies: 3.3 V digital, 3.3 V analog, 1.8 V digital, and 1.8 V analog. 2.2 The interface circuit between MSP430F149 and AD9910 This paper introduced the method which using MSP430F149 as the controller of the DDS chip. The MCU programs the internal register of AD9910, and choices the profiles. The AD9910 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats. The interface allows read/write access to all registers that configure the AD9910. In this paper, the serial port is used. Fig 2 The interface circuit between MSP430F149 and AD9910 The CS pin, SCLK pin, SDIO pin are the serial I/O port. The CS pin is an active low input that allows more than one device on the same serial communications line. The SDO and SDIO pins go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip select can be tied low in systems that maintain control of SCLK is reactivated low. The SCLK pin is used to synchronize data to and from the AD9910 and to run the internal state machines. Data is always written into the AD9910 on the SDIO pin. However, this pin can be used as a bidirectional data line. Bit 1 of CFR1 Register controls the configuration of this pin. When Bit 1 of CFR1 Register is 0, the SDIO pin is configured as bidirectional. The I/O_UPDATE initiates the transfer of written data from the I/O port buffer to active registers. I/O_UPDATE is active on the rising edge, and its pulse width must be greater than one SYNC_CLK period.when MASTER_RESET is low, all memory elements are cleared. PROFILE [2:0] are Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the current contents of all I/O buffers to the corresponding registers [4].

3 2666 Information Technology for Manufacturing Systems II 2.3 Clock input The AD9910 supports a number of options for producing the internal SYSCLK signal (that is, the DAC sample clock) via the REF_CLK/REF_CLK input pins. The REF_CLK input can be driven directly from a differential or single-ended source, or it can accept a crystal connected across the two input pins. There is also an internal phase-locked loop (PLL) multiplier that can be independently enabled. When using a crystal at the REF_CLK/REF_CLKinput, the resonant frequency should be approximately 25 MHz. Figure 3 shows the recommended circuit configuration. The internal oscillator works with fundamental mode crystals only. Crystal operation is enabled by a Logic 1 (1.8V logic required) on the XTAL_SEL pin. Fig 3 Crystal Connection Diagram DDS reference signal output of the system determine the accuracy and stability, the output signal in order to ensure accuracy and stability, in this system uses a temperature compensated crystal oscillator MHZ TX2110 as the DDS reference signal source, temperature compensated crystal does not change with temperature change, and the precision and stability is very high anti-jamming is better, so that the whole system output frequency accuracy and stability. 3. Design of the software of system The MCU is programmed to control the DDS chip. The MCU programs the internal registers of AD9910, then choice the profile through the pins. Figure 4 shows the Software flowchart. Fig 4 Software flowchart

4 Applied Mechanics and Materials Vols Serial programming The AD9910 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. There are two phases to a serial communications cycle. The first is the instruction phase to write the instruction byte into the AD9910. The instruction byte contains the address of the register to be accessed and defines whether the upcoming data transfer is a write or read operation. For a write cycle, Phase 2 represents the data transfer between the serial port controllers to the serial port buffer. The number of bytes transferred is a function of the register being accessed. For example, when accessing the Control Function Register 2, Phase 2 requires that four bytes be transferred. Each bit of data is registered on each corresponding rising edge of SCLK. The serial port controller expects that all bytes of the register be accessed; otherwise, the serial port controller is put out of sequence for the next communication cycle [5]. The AD9910 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by Bit 0 in Control Function Register 1 (0x00). The default format is MSB first. If LSB first is active, all data, including the instruction byte, must follow LSB-first convention. Figure 5 provides a basic example of the timing relationships between the various control signals of the serial I/O port. Use the same amplitude of signal to measure, we can get microstructure s frequency response curve. Fig 5 Serial Port Write Timing, Clock Stall Low The CS pin, SCLK pin, SDIO pin are the serial I/O port. The CS pin is an active low input that allows more than one device on the same serial communications line. The SDO and SDIO pins go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip select can be tied low in systems that maintain control of SCLK is reactivated low. The SCLK pin is used to synchronize data to and from the AD9910 and to run the internal state machines. Data is always written into the AD9910 on the SDIO pin. However, this pin can be used as a bidirectional data line. Bit 1 of CFR1 Register controls the configuration of this pin. When Bit 1 of CFR1 Register is 0, the SDIO pin is configured as bidirectional. The I/O_UPDATE initiates the transfer of written data from the I/O port buffer to active registers. I/O_UPDATE is active on the rising edge, and its pulse width must be greater than one SYNC_CLK period. When MASTER_RESET is low, all memory elements are cleared. PROFILE [2:0] are Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the current contents of all I/O buffers to the corresponding registers. waveform. 3.2 MCU program the internal registers of AD9910 The serial I/O port registers span an address range of 0 to 23. This represents a total of 24 registers. However, two of these registers are unused, yielding a total of 22 available registers. The unused registers are Register 5 and Register 6, The number of bytes assigned to the registers varies. That is, the registers are not of uniform depth; each contains the number of bytes necessary for its

5 2668 Information Technology for Manufacturing Systems II particular function. Unless otherwise stated, programmed bits are not transferred to their internal destinations until the assertion of the I/O_UPDATE pin or a profile change. CFR1, CFR2, CFR3 and profile registers are programmed. Single tone profiles are in effect when CFR1 [31] = 0, CFR2 [19] = 0, and CFR2 [4] = 0. Sine output of the DDS is selected when CFR1 [16] =1 configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial programming mode when CFR1 [1] =1. CFR3[26:24] is programmed to Select the frequency band of the REFCLK PLL VCO. CFR3[26:24] is programmed to Select the charge pump current in the REFCLK PLL. CFR3[15:14] is programmed to set REFCLK input divider. REFCLK PLL enabled when CFR3[8] =1. CFR3[7:1] is programmed to Select the divide modulus of the REFCLK PLL feedback divider. The AD9910 supports the use of profiles, which consist of a group of eight registers containing pertinent operating parameters for a particular operating mode. Profiles enable rapid switching between parameter sets. Single Tone Registers should be programmed.bit 61to bit 48, this 14-bit number controls the DDS output amplitude. Bit 47to bit 32, this 16-bit number controls the DDS phase offset. Bit 31 to bit 0, this 32-bit number controls the DDS frequency. Each profile is independently accessible. Use the three external profile pins (PROFILE [2:0]) to select the desired profile. Eight profile registers are available so AD9910 can generate 8-FSK signal. 4 Result The circuit is correctly connected, and the MCU is correctly programmed. The MCU programs the profile0 and profile1 registers of AD9910, then use the three external profile pins (PROFILE [2:0]) to select one of the two profiles, then the AD9910 IOUT pin would output the 2-FSK signal which is shown in Figure 6.The signal which was watched by using oscillograph proves that this circuit can correct output 2-FSK modulation signal. Fig 6 2-FSK modulation signal 5 Conclusion This paper introduced the FSK modulation hardware circuit which used MSP430 microcontroller as controller to control AD9910 DDS. This circuit can generate 8-FSK modulation signal. It is more concise and can generate higher frequency modulation signal than other circuits. It can be widely applied in the field of communication. ACKNOWLEDGMENT This work was sponsored by Project supported by National Natural Science Foundation of China. About the author:

6 Applied Mechanics and Materials Vols Li jun, male, Han nationality, born in 1987, Qingdao, Shandong, North University of China Master; research: Circuits and Systems. Address: Taiyuan, Shanxi, North University of China Laboratory Room 1200 Main Building Room 1200; Postal Code: ; Mobile: ; References [1] LIU Xu - dong. DDS-based Sweep Frequency Source Design for Millimeter Wave Automotive Collision Avoidance Radars[J]. Telecommunication Engineering, 2010;4(4):50. [2] Zhang Maochun, L iu Kai. Design of Frequency Modulation Continuous Signal Generator Based on DDS[J]. GUIDANCE & FUZE. 2010;6(2):31. [3] Xu Xiaodong, Wang Xifeng, Shi Fang, Zhang Xinmin. The design and implementation of a fast DDS chip based wide-band,low-stray signal generator[j]. Radar & ECM, Dec.2007:4. [4] Wang Zheng,Fan Zhong-guo,Wang Xiao yuan. Design and Realization for FSK Circuit Based on DDS [J]. Science Technology and Engineering, 2009;6(12):9. [5] Fang Yan-jun,Sun Jun,Zhu Xiao-ping, FSK Modulator-Demodulator Based on MSP430[J]. Instmment Technique and Sensor, 2008;7.

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