Low-Kickback-Noise Preamplifier-Latched Comparators Designed for High-Speed & Accurate ADCs

Transcription

1 Original scientific paper Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 4 (2014), Low-Kickback-Noise Preamplifier-Latched Comparators Designed for High-Speed & Accurate ADCs Ali Baradaran Rezaeii, Obalit Shino & Tohid Moradi Department of Microelectronics Engineering, Urmia Graduate Institute Abstract: High-resolution high-speed comparators are one of e main cores in e implementation of e high-performance systems, such as ADCs. Two comparators are presented in is paper where bo of e structures are suitable for high-speed, low-noise and accurate applications. The comparators are designed, based on e positive feedback structure of two back-to-back inverters. An improved rail-to-rail folded cascode amplifier wi an active bias circuit is utilized for e first architecture, in which e structure of e comparator is rearranged appropriate to e running comparison phase. Distinguished by its novel data reception style, a new comparator is proposed in e next circuit. In is structure, e hot n-well concept is considered for e PMOS transistors of e positive feedback latch. Applying e inputs to e bulks of e mentioned PMOS devices, isolates e regenerative outputs from e input signals; hence, a sizable attenuation in e kickback noise value is resulted. Merging e reset, evaluation and latch sequences makes it possible to decrease e comparison duration. Bo of e proposed comparators of is paper benefits from is excellence, erefore an intensive increase is observed in eir comparison speed. In order to confirm e performance accuracy of e circuits in various terms, multiple simulations are performed in all process corners, using HSPICE (level49) wi a standard 0.35μm CMOS process and e power supply of 3.3V. VDD noise of 300mVp-p and alterations in temperature are also included in e simulation conditions. The simulation results confirm recognition of a differential input wi 2mV pick-to-pick amplitude at as high a clock frequency as 800MHz wi power consumption about 2.6mW for e first circuit and a 1mV differential input wi update rate of 1GHz and power consumption about 1.6mW for e low-noise structure of e second comparator. According to e layout pattern, an active area of 55μm 13μm and 24μm 15μm is occupied by e improved folded cascode comparator and e proposed novel structure respectively. Keywords: High Speed Comparator, Kickback Noise, High Speed ADC, High Resolution Comparator. Visokozmogljiva primerjalnika z nizkim povratnim vplivom na osnovi topologije predojačevalnik-zapah za hitre in natančne analogno-digitalne pretvornike (ADC) Izvleček: Visokoločljivi in hitri primerjalniki so osnova za izvedbo visokozmogljivih sistemov, kot so analogno-digitalni pretvorniki (ADC). V prispevku sta predstavljena dva primerjalnika, katerih struktura je primerna za hitre, nizkošumne in natančne aplikacije. Primerjalnika sta zasnovana na osnovi dveh povratno vezanih negatorjev. Pri prvem primerjalniku je uporabljen kaskodni ojačevalnik, pri katerem je struktura primerjalnika preurejena glede na tekočo fazo primerjanja. Pri drugem primerjalniku so vhodni signali priključeni na substrat tranzistorja prek diferencialnih tranzistorskih parov. S tem smo zmanjšali vpliv izhoda vezja in vrednost povratnega šuma. Predlagana vezja smo načrtali v 0.35 μm tehnologiji CMOS z napajalno napetostjo 3.3 V in, v postopku simulacije, preverili z uporabo programa HSPICE. Pri tem smo preverili vpliv napetostnih motenj v napajanju in spremembe temperature na delovanje primerjalnikov. Rezultati simulacij potrjujejo zaznavo diferencialne napetosti amplitude 2 mv pri frekvenci ure 800 MHz in porabo moči 2.6 mw za prvi primerjalnik in zaznavo diferencialne napetosti amplitude 1 mv pri frekvenci ure 1 GHz in porabo moči 1.6 mw za drugi primerjalnik. Površina vezja, ki jo zasedata primerjalnika, je 55μm 13μm in 24μm 15μm. Ključne besede: hitri primerjalnik, povratni šum, hitri analogno-digitalni pretvornik, visokoločljivi primerjalnik * Corresponding Auor s m.o.shino@urumi.ac.ir 312 MIDEM Society

2 1 Introduction Alough most of e parameters obtained from e nature by different sensors are analog by default, an analog to digital conversion process is required due to e vast improvements in e digital signal processing field. CMOS high-speed analog-to-digital converters (ADCs) are one of e best suited blocks for is purpose where some bottlenecks have to be solved. Precisely comparison of e analog input signal wi a reference value and extracting e digital output bit is a great challenge and seems to be e main bottleneck of e process; hence, a high-speed, high-resolution and low-power comparator is needed to keep e overall performance of e system in an acceptable level. The input voltage of e comparators changes continuously which leads to some variations in eir outputs at e input clock edges. Based on e comparison, e comparator outputs a High or Low signal. Depending on eir nature, functionality and inputs, comparators are classified into different types such as voltage or current comparators, continuous or discrete time comparators and so on. By anoer classification, ere are two different kinds of comparators: singlestage and multi-stage comparators, [2]. Studding ese two kinds, it can be understood at e multi-stage comparators have more power consumption, delay time and die size; however e single-stage ones usually have complicated switches which are required to be controlled accurately via additional controlling signals, [1,2]. Variety of e timing signals might increase e digital coupled noise to e analog section, also generation of ese controlling signals requires some extra hardware which again increases e die size and e power consumption of e system. Multi-stage comparators are usually made up of ree main stages; pre-amplifier, decision circuit (positive feedback or gain stage) and post-amplifier. The pre-amp stage amplifies e input signal to improve e comparison sensitivity rough increasing e minimum detectable input signal by which e comparator can make correct decisions. Meanwhile, it isolates e input of e comparator from e switching noise which is produced by e positive feedback stage like e clock feed rough and e kickback noise effect. The gain stage is used to determine which of e input signals is larger and e output buffer amplifies is information and produces a full-range digital data. In e single stage comparators, e ree important phases of e comparison, reset, evaluation and latch, are performed via a single block. During e reset phase, e previous data stored in e parasitic capacitors is usually removed using a reset switch at connects e differential output nodes to each oer. The second phase is evaluation in which e comparator begins to compare two inputs and decides wheer e outputs should be high or low. In e latch phase, e evaluated outputs are separated up to e digital levels. Each of ese phases need a certain timeframe, hence it can be concluded at e conversion speed is limited by e decision-making duration of e comparator. CMOS process variation is e main origin of e offset voltage introduced to e latched comparators, which extremely restricts eir comparison accuracy. Coupling a pre-amplifier stage before e output latch attenuates e input-referred offset voltage of e comparator, us an accurate preamplifier-latch topology is engendered, [6-8], making it possible to utilize e comparator for high-resolution purposes. Based on e folded cascode structure, a high-speed high-accuracy comparator wi preamplifier-latch topology is improved for high-resolution applications. Moreover, anoer comparator is proposed in which a novel meod is utilized for obtaining a high-resolution latched structure. Taking advantage of is circuit, bo high speed and high accuracy beside low die size and lessened power consumption is achieved. Rest of e paper is organized in 6 sections. In e next section latched comparators are discussed, e improved folded cascode structure is presented in Section 3, e proposed new comparator circuit is detailed in Section 4, a new readout circuit is presented in Section 5, Section 6 verifies e simulation results, and e final section delivers e conclusion and e comparisons wi similar works. 2 Latched Comparators The reshold voltage of an inverter (V ) is a boundary voltage at determines wheer e value of e received signal is High or Low. As depicted in Fig. 1, is voltage is arisen from shorting e input and e output of an inverter. Value of e V depends on e reshold voltages of NMOS and PMOS transistors (V n and V p, respectively). Threshold voltage for an inverter can be calculated according to (1) and (2). I dp = I dn (1) W L 1 µ nc 2 OX n 2 n ( V V ) ( 1+ V )= λ ( V V V ) + [ V V ] = µ 1 λ 1 W 2 nc OX dd p 2 L p ( ) dd (2) 313

3 Figure 1: A CMOS Inverter wi its Shortened Input and Output. Ignoring e channel leng modulation effect and applying e device sizes as µ n (W/L) n = µ p (W/L) p, (3) is obtained: V = ( V + V V ) dd n 2 p As it s clear, e value of V depends on V n and V p so it is affected by e process variations, us its value varies in different process corners. In TT, SS and FF corners V n is close to V p in value, so V V dd / 2 but due to inequality in e conductance of NMOS and PMOS devices, in FS and SF corners V is respectively a little bit greater or lower an V dd / 2. Fig. 2 illustrates two back-to-back inverters besides a reset switch. Variant fabrication process and asymmetrical doping generate two unequal reshold voltages for e inverters. While two output nodes (O 1 and O 2 ) are shorted by e reset switch, eir voltage is equal to a value between two reshold voltages. Following e reset phase, each inverter amplifies e difference between its relevant reshold voltage and is value; due to e regenerative nature of is structure, O 1 and O 2 reach e logic levels. Applying e input signal, e outputs have to be forced to be separated in desired direction. Because of e positive feedback nature of e system, one must reset e structure to clear e previous data, en evaluate e correct direction according to e inputs and finally ignite e regenerative latch. (3) Figure 2: Block Diagram and Circuitry of Two Back-to- Back CMOS Inverters Forming an Intense Positive Feedback Structure. 3 Proposed High-Speed Comparator Based on e described behavior of e latch block, a rail-to-rail folded cascode amplifier is modified using a positive feedback structure of two back-to-back inverters. Also an NMOS device is utilized as reset switch for removing e previously latched data from e output nodes. The structure is scheduled for performing e consecutive sequences of e comparison process (reset, evaluation and latch). The bias circuit is also an active block which alters e relevant biasing currents of e folded cascode in different operation modes. The proposed comparator structure besides its timing diagram is presented in Fig. 3. Four differential pairs (M 5 M 12 ) are in connection wi e cascode nodes of e amplifier. The analog input signals are applied to ese differential pairs. The mentioned back-to-back inverter structure is formed by (M 1 M 4 ). Two bias circuits are also observed in Fig. 3. The first section of e bias circuit (M 21 M 23 ) prepares e appropriate bias voltages for e current sources of e differential pairs. The next circuit is e active section of e bias block which provides e cascode devices (M 13 M 16 ) wi variable bias voltage, proportional to e running operation mode. Considering e timing diagram of Fig. 3, by rising edge of φ 1, two output nodes are shorted rough S 1. By e same time e infirm PMOS device M 25, enfeebles e positive feedback force of (M 1 M 4 ) which facilitates e data removal process. Unlike most of e latched comparators, in e proposed structure of Fig. 3 e reset and evaluation sequences are merged and can be performed simultaneously in separate nodes. While e reset phase is running at e regenerative outputs, e primary evaluation of e input signals is going on at e cascode nodes. 314

4 Figure 3: Improved High-Speed Comparator and its Timing Diagram. After e evaluation, when e voltage difference reaches e detectable range of e positive feedback latch, M 25 is replaced by M 26, at e rising edge of φ 2. So, e streng of e positive feedback is intensified again and e output voltages are separated up to e digital values. From anoer site of view, e evaluation phase has a separate timing schedule from reset and latch, making it possible to achieve bo high speed and accuracy. Kickback noise is a limiting factor for comparators accuracy [1, 4]. This kind of noise is mainly originated by e regenerative outputs of e positive feedback block. In e proposed comparator of Fig. 3 e current of e positive feedback inverters is limited by e cascode current sources (M 13 M 16 ), so rapid variations at e output nodes are avoided and hence e main source of kickback noise is limited. 4 Proposed Low Kickback Noise Comparator The next proposed comparator is illustrated in Fig. 4. Similar to e comparator of e previous section, is structure also consists of two back-to-back inverters forming an intense positive feedback. What makes e proposed circuit distinguished is its novel data reception style. The input signals are applied to e bulks of e transistors via two differential pairs. It is necessitous to reverse bias e drain-bulk diode of e transistors to insure eir proper work, is affair can be realized in different ways. As it is done in mostly all conventional circuits one can ignore e bulks of e transistors and connect em to VDD and GND respectively for PMOS and NMOS devices. All NMOS transistors on a single die have one common bulk terminal which is e substrate of e chip, it must be connected to e lowest voltage of e circuit (usually GND) to avoid e drain-bulk diode from turning on, so eir bulk nodes are not applicable in almost all cases, but in case of PMOS transistors it is not e same. Each PMOS device can be constructed in an individual n-well region so its bulk terminal is also an individual node and can be connected to desirable voltages. In is paper wi aid of e capacitors (C 1 - C 2 ) and eir relevant charging devices (M 9 - M 10 ), voltage level at e bulks of PMOS devices, M 2 and M 4, is kept near VDD insuring e reverse bias of eir drain-bulk diodes; also a floating state is established at ese bulk nodes which are evaluation nodes of e circuit. The utilized capacitors, C 1 and C 2, are selected as 100fF. The maximum error arisen for capacitors of is size is about 5% (± 2.5%), if eir layout pattern is implemented accurately. Wi such an error, one of e inputs will have a higher influence, which introduces new offset source to e system; hence, e difference of e capacitors appears as offset voltage at e inputs of e comparator. Applying e differential inputs alters e voltage level of e mentioned bulks against each oer. According to (4), variations in e source-bulk voltage of a transistor directly affects its reshold voltage and consequently e corresponding inverters reshold. Thus e comparison is done by steering e reshold voltages in opposite directions. 315

5 Figure 5: Timing Diagram for e Comparator of Fig.4. e output signals. The discussed circuit is pictured in Fig. 6. It is made up of a data latch and a pair of NMOS devices. The outputs of e proposed comparators are applied to e gates of e NMOS devices; bit+ and bitare e outputs of e readout circuit. Figure 4: Proposed Low Kickback Noise Comparator. V ( ( V + V ) V ) = V 0 + γ (4) SB φ φ Reset, evaluation and latch are ree required phases which are performed consecutively in sequential onestage comparators. This obligation affords delay to e process and limits e speed extremely. In e proposed structure, reset and evaluation sequences are performed simultaneously in separate nodes. The digital controlling signals are illustrated in e timing diagram of Fig. 5. Reset phase starts at e rising edge of φ 2, concurrently as φ 1 goes low, e capacitors C1 and C2 are approximately charged up to e VDD level; at e rising edge of φ 1, evaluation occurs in e bulk terminals of M 2 and M 4. In pursuit of e output reset, e evaluated data affects e regenerative latch; up to e next rising edge of φ 2, e positive feedback has e opportunity for separating e output voltages. In oer words, independence of e evaluation phase from reset and latch phases makes it possible to achieve bo high speed and accuracy. 5 Readout Circuit A simple readout circuit is utilized to hold e latched data. In absence of is circuit, e outputs of e comparator are set to a common mode voltage level after each reset phase and it lasts to reach e desired level once more. Implementing e readout circuit preserves e latched data of e regenerative nodes for one full clock cycle; in fact, it increases e validity period of Figure 6: Conventional Readout Circuit. Cascading e proposed comparator of Section 4 wi e readout circuit of Fig. 6 introduces additional capacitance to e output nodes of e comparator hampering e comparison process. As a solution two inverters are implemented as interface between e comparator and e readout circuit. Aiming to reduce e input capacitance of interface circuit, e first inverter of each side has a different structure from e well-known static inverters. The NMOS devices of e first inverters at bo sides of e interface circuit are connected to e comparator outputs but eir PMOS side is drived by a delayed version of e RESET signal named W. The idea is pictured in Fig. 7. Reviewing e function of is interface circuit for one side, at falling edge of W, e PMOS device M4 is turned ON for a short time period charging e node K+ and en goes OFF (pre-charge). If e output of e comparator is LOW, e NMOS device M3 will stay in cut-off region and cannot discharge e node K+ so it remains HIGH, but if e comparator output is HIGH, it makes e NMOS transistor to turn ON and discharge K+ (evaluation), hence e comparators output is inverted. K+ is inverted once more by a normal inverter producing e signal D+, is signal is en applied to e pro- 316

6 Figure 8: Layout of e Presented Comparators and Readout Circuit. Precession of e operation is confirmed for bo of e proposed structures. As illustrated in Fig. 9, e comparator of e Section 3 has e sufficiency of recognizing a 2mV differential input wi 800MHz update rate. On e oer hand, Fig. 10 confirms at a 1mV differential input at as high a clock frequency as 1GHz is simply sensible for e proposed comparator of Section 4. The measured power consumption of ese two structures is 2.6mW and 1.6mW respectively. Figure 7: Proposed Readout Circuit. posed readout circuit. Same story goes on for e next output of e comparator. By is mean, only a minimum size NMOS device is connected to out1 and out2, so e additional capacitance is dramatically reduced insuring e correct comparison process. 6 Simulation Results The main cores of e presented comparators beside e readout circuit of Fig. 7 are implemented in 0.35μm CMOS process. As illustrated in Fig. 8, an active area of 715μm 2 and 360μm 2 is occupied by e proposed comparators of Sections 3 and 4. In order to confirm e performance accuracy of e circuits in various terms, multiple simulations are performed in all process corners, using HSPICE (level49) wi a standard 0.35μm CMOS process and e power supply of 3.3V. Aiming to generate a none-ideal power supply, some sinusoidal voltage sources are utilized in series wi e VDD which leads to a noisy power supply. The simulation results indicate a 300mV p-p noise which is mounted on e VDD source. In order to examine e capability of erasing e previously latched data, a challenging simulation known as worst case comparison is performed in which e input voltage alters from a large amplitude to a small value in e opposite direction and viceversa. Figure 9: Simulation Results for Comparator of Fig. 3 Consisting e Reset 800 MHz, Differential Input, Comparator Outputs, Differential Output and Outputs of e Readout Circuit. In order to simulate e comparator of Fig. 4 wi imbalance capacitors, C 1 and C 2 are selected as 97.5fF and 102.5fF (wi ± 2.5% tolerance). A variable ramp source is applied to e comparator as offset voltage source. As depicted in Fig. 11, once e offset cancellation source (ramp voltage source) reaches around e 1.9mVolts, e tolerance of e capacitors is compensated and e improper operation of e comparator is corrected. The issue confirms at any mismatch in e 317

7 Figure 10: Simulation Results for Comparator of Fig. 4 Consisting e Reset 1 GHz, Differential Input, Comparator Outputs, Differential Output and Outputs of e Readout Circuit. Figure 12: Kickback Noise Simulation for Comparator of Fig. 3. capacitor values, appears as offset voltage at e inputs of e comparator, as well. Figure 11: Correcting e Operation of e Comparator of Fig. 4 via a Variable Ramp Source Applied as Offset Voltage Source when C 1 and C 2 are Utilized wi ± 2.5% Tolerance. The originated voltage spikes of e regenerative latch are not able to impress e ideal input voltage source; hence, a resistor string of 10KΩ is used at each end which makes it possible to measure e kickback noise level. According to Fig. 12 and Fig. 13, e maximum amplitude observed is about 1mV and 0.6mV respectively for e comparators presented in Sections 3 and 4. Figure 13: Kickback Noise Simulation for Comparator of Fig Conclusion A high performance comparator based on e preamplifier-latch topology was provided by improving e rail-to-rail folded cascode amplifier. Also a novel data reception style was utilized to engender a low-noise structure. Sufficiency of e comparators for highspeed, high-accuracy and low-power applications is confirmed by various simulation results. Table 1 sum- 318

8 marizes e performance of e proposed structures and Table 2 compares e proposed circuits wi earlier presented similar works. Table 1: Performance Summary Process Standard 0.35μm CMOS Process Supply Voltage 3.3Volts Power Supply Noise 300mVolts p-p Number of Stages Single Stage Improved High-Speed Comparator Proposed Low Kickback Noise Comparator Comparison Rate 800MHz 1GHz Resolution 2mVolts 1mVolts Kickback Noise Disturbance 1mVolts 0.6mVolts Power Consumption 2.6mW 1.6mW Area 55µm 13µm 24µm 15µm 3. Rezaeii, A.B. ; Hasseli, L. ; Moradi, T., A 125MS/s self-latch low-power comparator in 0.35μm CMOS process, 21st Iranian Conference on Electrical Engineering, ICEE S. Kazeminia, M. Mousazadeh, Kh. Hadidi and A. Khoei, High-speed low-power Single-Stage latched-comparator wi improved gain and kickback noise rejection, IEEE Asia Pacific Conference on Circuits and Systems, APCCAS Page(s): Y. L. Wong, M. H. Cohen and P. A. A Abshire, A 1.2- GHz comparator wi adaptable offset in 0.35-μm CMOS, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, vol. 55, No 9, OCTOBER 2008, pp M. B. Guermaz, L. Bouzerara, A. Slimane, M. T. Belaroussi, B. Lehouidj and R. Zirmi, High Speed Low Power CMOS Comparator for Pipeline ADCs, 25 International Conference on Microelectronics, IEEE, 2006 Table 2: Comparison Table [1] (2011) [4] (2010) [10] (2012) [11] (2014) [12] (2011) [13] (2013) Proposed Comp. of Fig. 3 Proposed Comp. of Fig. 4 Process 0.35 µm 0.35 µm 45 nm 0.18 µm 0.18 µm 0.18 µm 0.35 mm 0.35 mm No. Stages Comparison Rate (GS/s) Resolution (mv) Power Consumption uW 0.274uW (mw) Area (µm2) Kickback Disturbance (mv) References 1. A. Baradaranrezaeii, R. Abdollahi, Kh. Hadidi and A. Khoei, A 1GS/s low-power low-kickback noise comparator in CMOS process, 20 European Conference on Circuit Theory and Design, ECCTD Page(s): S. Kazeminia, O. Shino, E, Haghighi and Kh. Hadidi, Improved Single-Stage Kickback-Rejected Comparator for High Speed and Low Noise Flash ADCs, 21 European Conference on Circuit Theory and Design, ECCTD L. Picolli, A. Rossini, P. Malcovati, F. Maloberti, F. Borghetti and A. Baschirotto, A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors, IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, February B. Goll and H. Zimmermann, A 65nm CMOS comparator wi modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V, ISSCC2009, Pages: S. Sheikhaei, Sh. Mirabbasi, and A. Ivanov, A 0.35μm CMOS comparator circuit for High-Speed ADC applications, ISCAS 2005, Vol. 6, Pages:

9 10. M. J. Taghizadeh. Marvast, H. Sanusi and M. A. Mohd. Ali, A 4.1-bit, 20 GS/s comparator for high speed flash ADC in 45 nm CMOS technology, Journal of Microelectronics, Electronic Components and Materials, Vol. 42, No. 1 (2012), Pages: S. B. Mashhadi and R. Lotfi, Analysis and design of a low-voltage low-power double-tail comparator, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 22, No. 2, February 2014, Pages: Kh. Dabbagh. S., An improved low offset latch comparator for high-speed ADCs, Analog Integrated Circuits and Signal Processing, Vol. 66, Issue 2, February 2011, Pages: Z. Zhu, G. Yu, H. Wu, Y. Zhang and Y. Yang, A highspeed latched comparator wi low offset voltage and low dissipation, Analog Integrated Circuits and Signal Processing, Vol. 74, Issue 2, February 2013, Pages: Arrived: Accepted: