A Hybrid Method for Fault Location in EHV Multi-Terminal Circuits

Transcription

1 6th ATOAL POWER SYSTEMS COFERECE, 5th-7th DECEMBER, 754 A Hybrid Method for Fault Location in EHV Multi-Terinal Circuits B R K Vara, Research Scholar Departent of Electrical Engineering ational nstitute of Technology Warangal, ndia Prof.P V Raana Rao Abstract Protection of Extra High Voltage (EHV) ulti-terinal circuits in power systes is coplicated due to non-availability of easureents at the tap points. Locating a fault in such circuits is an iportant tas for post-fault repairs or identification of wea spots in the syste. This paper presents a new fault location schee for an EHV ultiterinal circuit. The proposed ethod utilizes synchronized voltages and currents of three phases fro all the ends of the circuit. Both transient high frequency and fundaental frequency coponents of the fault signals are used to detect and locate the fault. While the Wavelet Transfor is used to extract the features for fault detection and section identification, a Discrete Fourier Transfor () based approach is applied to estiate phasors for exactly locating fault with in the faulted section. The schee is tested on a siulated syste for various types of faults, fault locations, inception angles and fault resistances. Results indicate that the schee is reliable, fast and accurate. Keywords- Power Syste protection, Fault Location, Multi-terinal Circuits. E. TRODUCTO HV ulti-terinal circuits are fored due to the reasons of constraints on the right of way and econoy. Protection of such ulti-terinal circuits in power systes is coplicated due to the possibility of several sources feeding a fault and non-availability of easureents at the tap points. Ability to locate the fault accurately in a coplex power networ is an additional iportant feature of any odern power transission line protection schee. Several techniques have been developed earlier for accurate fault location in two-terinal lines [], [], [3], [4]. However, fault location in ulti-terinal lines is coplicated because of interediate infeed or outfeed and superiposed reflections of the fault signal fro the junction and fault points. n ultiterinal lines, any fault location technique involves two aspects - identifying the faulted section and locating fault within the faulted section. Reference [5] presented a fault locator ethod for three-terinal lines using un-synchronized phasors fro the three ends by neglecting shunt capacitance. An accurate fault locator for such lines is proposed in [6] considering shunt capacitance. A fault locator for a teed (three-terinal) circuit is proposed in [7] that uses synchronized voltage and current phasors fro only two terinals. Reference [8] describes a traveling wave based fault location algorith for three terinal lines using wavelet transfor. Recently another fault location ethod is proposed for three terinal lines with current differential relays [9]. A hybrid fault locator for three terinal lines is proposed in [] to locate fault, which uses either traveling waves or ipedance calculation depending on signal noise. n reference [], a fault location ethod for ulti-terinal lines is developed using synchronized voltage and current easureents at all ends. The fault location ethod is claied to be insensitive to CT errors as only voltage signals are used after identifying the faulted section. n this paper, a new fault location schee for ultiterinal circuits is presented which is based on the transient fault voltage and current signals fro all the ends. The ultiresolution analysis using wavelet transfor is applied to obtain the fault induced high frequency coponents of the easured voltage signals. A odal voltage signal is used to detect the fault and identify the faulted section of the ultiterinal circuit. The location of fault within the faulted section is identified by an accurate fault locator ethod using phasors. The fundaental voltage and current phasors are estiated using a Discrete Fourier Transfor based odified algorith which itigates the effects of exponentially decaying DC offsets. This ethod is tered as hybrid because it is based on processing both the transient high frequency as well as the fundaental frequency coponents of the fault signals. The S 5 KV GVA 7 KM KM T 8 KM KM T 6 KM S3 5 KV 5 GVA 5 KV GVA S4 Figure. EHV Multi-terinal Circuit S 5 KV 35 GVA

2 6th ATOAL POWER SYSTEMS COFERECE, 5th-7th DECEMBER, 755 schee is tested for different types of faults with varying fault incidence angles and fault resistances using a typical fourterinal circuit shown in Fig.. Results indicate that the proposed schee is reliable, fast and highly accurate. The proposed schee collects sapled data signals of all easured synchronized phase voltages and currents fro the four relaying ends S, S, S3 and S4 of the circuit shown in Fig. The synchronized voltage and current signals are obtained by using global positioning syste (GPS) based satellite counication systes installed at the relaying ends of the circuit. Fig. and Fig. 3 show typical voltage & current wavefors at all the ends during a line to ground fault in section S-T at 4 fro the source end. Current (A) Phase Voltage (V) x 6 Voltages at S x 5 Voltages at S x 6 Voltages at S x 6 Voltages at S Tie (s) Figure. Voltages for b-g fault in section S-T at 4 fro S x 4 Currents at S Currents at S Currents at S Currents at S Figure 3. Currents for b-g fault in section S-T at 4 fro S Section explains fault detection & section identification procedure. Section elaborates the fault location ethod and section V presents the siulation results.. FAULT DETECTO & SECTO DETFCATO As entioned earlier, the fault detection and section identification procedure uses high frequency content of transient fault voltage signals easured at the ends. This high frequency content is extracted fro the fault voltage signals by using Wavelet Transfor. Wavelet Transfor (WT) is a recent signal processing tool and is suitable for power syste transient studies lie power quality assessent, power syste protection etc. A. Wavelet Transfor Unlie Fourier Transfor (FT), which uses only sinusoid as basis function, the wavelet transfor uses several basis functions called other wavelets and variable sized windows for capturing both high frequency and low frequency coponents of the signal. Wavelet analysis of any signal begins with the selection of a suitable other wavelet and analysis is perfored using shifted and dilated versions of this wavelet. The WT for a discrete signal of length can be calculated in only operations where as the FT of the discrete signals, i.e. the FFT, requires ( log ) operations. The discrete wavelet transfor (DWT) of a digital signal is, nb a DWT(, ) = x( n) g () a n a where g(n) is the other wavelet and x(n) is the input signal, and the scaling and translation paraeters a and b are functions of integer paraeter. The DWT ipleentation is carried out using a pair of finite ipulse response filters called Quadrature Mirror Filters (QMF). This ipleentation is nown as the Multi-Resolution Analysis (MRA). n this paper, only first level wavelet decoposition is used to obtain the high frequency content of various voltage and current signals. The Bior. wavelet is selected as the other wavelet as it is found to be very effective for power syste fault transients []. B. Fault Detection and Section dentification Procedure When a fault occurs, the transient voltage and current signals in the faulted section contain predoinant high frequency coponents. The energy of these high frequency signals is used as an indicator of the fault occurrence. A quarter-cycle oving window processing is carried out for high speed detection of fault. A odal voltage signal for each end is fored with the three phase voltages of the corresponding relay end to identify the faulted section, using transforation V = V V + V () a b The above single odal signal covers all types of faults and eliinates the effects of utual coupling with adjacent circuits. These odal voltage signals are processed using DWT with bior. as the other wavelet to obtain the first level detail coefficients (D). These D coefficients c

3 6th ATOAL POWER SYSTEMS COFERECE, 5th-7th DECEMBER, 756 indicate the strength of the high frequency content. With these coefficients, a fault section energy index value (FSE) is obtained for each end by calculating the signal energy using the Frobenius nor. The first and last five detail coefficients are truncated while coputing the index to eliinate the edge effect. The index is defined as [ ] Fault Section Energy ndex, FSE = d() i i= where is the nuber of first level detail coefficients after truncation. A fault is detected whenever the FSE value of any end goes beyond a threshold. During noral operation, the value of the FSE is very sall and incase of any fault the FSE value of the faulted section drastically increases. This clearly discriinates between fault and non-fault situations. The faulted section is identified by a relative coparison of FSE values of the four ends. n the case of faults in sections having source ends, the FSE value of the faulted section will be uch higher than other values. But for faults in the iddle section (T-T), the index values of nearby sections (sections connected to a coon junction) do not differ appreciably.. FAULT LOCATO Once the fault is detected and section identified, the schee collects a full cycle of post-fault voltage and current signals of all phases fro the four relay ends. Then, using a based phasor estiation algorith, the fundaental voltage and current phasors are estiated for locating the fault. Using these phasors, a fault location procedure based on the technique proposed in [], is applied for accurately locating the fault within the faulted section. A. Phasor Estiation Traditionally, algorith is used for phasor estiation in power systes because of its siplicity in coputation copared to other ethods. However, this ethod is prone to errors when the signals contain proinent decaying DC offsets. n this paper, a recently proposed based odified phasor estiation ethod [3], which is able to reove the decaying DC coponent fro the fault signal wavefors and estiate the phasors with a high accuracy, is applied. The ethod is briefly reproduced here. Given a discrete current signal i(n) easured at the relay end, the fundaental frequency phasor of the current signal can be calculated by using = n= i( n). e π j n f the signal contains a decaying DC offset, the can be expressed as fund DC = +. (5) DC The is the error due to DC offset and can be obtained fro the even-saple-set and the odd-saple-set of (3) (4) the original signal i(n) using j π j π DC even odd = ( ).( + Ee ) /( Ee ) (6) π π Where E = B /( A. Sin( ) B. Cos( )) (7) even odd A = Re part of ( ) (8) even odd B =. part of ( ) (9) The accurate fundaental frequency phasor of the signal is given by fund DC = () B. Location of Faults with in the Faulted Section Figure 4. Two-terinal transission syste Reference [] proposed an accurate fault location technique using a odal transforation for two-terinal lines. The odal transforation using the theory of natural odes and atrix function theory decouples a three-phase networ in to three independent single-phase networs. These three networs correspond to an earth ode and two aerial odes. The technique is shown to be very effective and insensitive to different fault situations lie variations in fault type, location, incidence angles, source ipedances etc. n this procedure, the voltage & current phasors at the two relay ends of the faulted section are required for locating the fault. By this ethod, the fault distance x, as shown in Fig.4, fro the first end of the faulted section with length L can be obtained by using the following equations in which =for earth ode, and 3 for aerial odes. The quantities γ and Z o are the odal propagation constant and odal surge ipedance respectively. V s & s and V R & R are voltage and current phasors of the two ends of the faulted section. where x B = [tanh ( )]/ γ () A A = Z Cosh( γ L) R Sinh( γ L) VR + Z B S = Cos( γ L) V Z Sinh( γ L) x R L n this paper, the above procedure is extended to the ulti-terinal circuit shown in Fig.. After identifying the faulted section, the voltage and current phasors for the two ends of it are obtained by utilizing the phasor inforation of all relay ends. For exaple, if fault is in section S-T, the phasors at T are calculated fro the phasor inforation of S, S3 and S4 ends. Phasors at S are any way directly available. Siilarly, if fault is in section T-T, phasors at T R R V s s

4 6th ATOAL POWER SYSTEMS COFERECE, 5th-7th DECEMBER, 757 are calculated fro S & S3 phasors and phasors at T are calculated fro S & S4 phasors. V. SMULATO RESULTS The schee is evaluated using 5 V, 5 Hz transission syste whose line paraeters are R =.888 Ω/, R =. Ω/, L = 3.5 H/, L =.94 H/, C =.83 µf/ & C =. µf/. A sapling frequency of Hz is chosen to capture the high frequency content of voltage and current signals around the centre frequency of 75 Hz [4]. Adoption of such high sapling frequency avoids the use of anti-aliasing filter thus reducing soe delay [5]. At this sapling frequency, each quarter-cycle data window contains saples. The syste is odeled in MATLAB SiPowersystes environent. x 6 Modal voltage at S The networ shown in Fig. is siulated for various fault situations. Exhaustive siulations are carried out for different types of faults occurring in different sections at various locations within the circuit. For each type of fault at a particular location, the fault inception angle is widely varied to evaluate the perforance of the proposed schee. nfluence of fault resistance is also evaluated by considering a fault resistance value of 5 ohs. The perforance of the schee in detecting faults and section for various types of faults i.e. line-to-ground, lineto-line, double line-to-ground, three phase faults is evaluated. n all the cases studied, the schee is able to correctly detect the fault and identify the faulted section. The fault incidence angle is varied fro to 8 for all types of faults. Fig. 5 and Fig. 6 show the wavefors of odal voltage signals of four ends and the corresponding detail coefficients respectively for b-g fault in section S-T at 4 fro the source end. Voltage(v) x 6 Modal voltage at S x 6 Modal voltage at S x 6 Modal voltage at S4 FSE 6 x End S End S Figure 5. Modal voltages for b-g in fault section S-T at 4 fro S D coefficents 5 x 5 D coefficients of Modal voltage at bus x 5 D coefficients of Modal voltage at bus x 5 D coefficients of Modal voltage at bus x 5 D coefficients of Modal voltage at bus Figure 6. D coefficients for b-g fault in section S-T at 4 fro S Figure 7. FSE variation for b-g fault in section S-T at 4 fro S FSE 6 x End S End S Figure 8. FSE variation for a-b fault in section S-T at fro S

5 6th ATOAL POWER SYSTEMS COFERECE, 5th-7th DECEMBER, 758 n the case of faults in sections with source ends, it is observed fro siulation results that the faulted section FSE value is at least 5% higher than the values of the reaining sections with source ends. Also it is observed that, FSE values for relay ends far away fro faulted section are very sall copared to the value of the nearby end. This variation is due to the fact that the fault induced transients have to propagate through two junctions (T & T). This distinctive feature is used to correctly identify the faulted section in such cases. Fig. 7 and 8 show the variation of FSE values at the four ends with a b-g fault in section S-Tat 4 and an a-b fault in section S-T at respectively fro the source ends. FSE 4 x Figure 9. FSE variation for b-c-g fault in section T-T at 3 fro T 3.5 x End S End S4 End S Ens S4 connected to a coon junction) would be very sall or negligible. Therefore it is possible to segregate such a fault effectively. Fig. 9 and show the variation of FSE values at the four ends with a b-c-g fault at 3 and an a-b-c fault at 6 respectively in the section T-T. After identifying the fault section, the fault location is estiated by the accurate fault location ethod presented earlier. The location is accurately found for various types of faults with different incidence angles and fault resistances. Table shows the fault location results for various types of faults occurring in different sections of the circuit. n all the cases presented, the fault detection & section identification is correctly done by the schee. TABLE. FAULT LOCATO RESULTS Fault Actual Locatio n fro Estiated Location for inception angle source 9 Section Type end ( ) R f = Ω R f = 5 Ω R f = Ω R f = 5 Ω a-g S-T a-b a-b-g a-b-c b-g S-T b-c b-c-g a-b-c c-g S3-T c-a c-a-g a-b-c a-g S4-T a-b-g b-c a-b-c-g a-g b-g c-g a-b T-T b-c c-a a-b-g b-c-g c-a-g a-b-c FSE Figure. FSE variation for a-b-c fault in section T-T at 6 fro T For faults in the iddle section (T-T), the difference between FSE values of nearby sections (sections V. COCLUSOS This paper presents a new hybrid fault location schee for EHV ulti-terinal circuits. The fault voltage and current signals fro all ends are processed in the proposed schee. The high frequency coponents derived by wavelet transfor fro fault signals are used as discriinative features for detection and section identification. The single odal voltage signal used is very effective for correct and fast fault detection and section identification for all types of faults. Fault location is carried out accurately using phasors estiated with a based odified algorith. Siulation results indicate that the proposed schee is reliable, fast & accurate. Further investigations are necessary to exaine the applicability of the schee to a general ulti-terinal circuit.

6 6th ATOAL POWER SYSTEMS COFERECE, 5th-7th DECEMBER, 759 REFERECES [] Johns A.T and S.Jaali, Accurate Fault Location Technique for Power Transission Lines, EE Proceedings, Vol.37,Pt.Co.6, oveber 99 [] J.-A. Jiang,J.-Z.Yang, Y.-H.Lin, C.-W.Liu, and J.-C.Ma. An adaptive PMU based fault detection/location technique for transission lines, Part : Theory and algoriths, EEE Transactions on Power Delivery, Vol.5, pp , April. [3] J.-A. Jiang, Y.-H.Lin, J.-Z.Yang, T.-M.Too, and C.-W.Liu, An adaptive PMU based fault detection/location technique for transission lines, Part : PMU ipleentation and perforance evaluation, EEE Transactions on Power Delivery, Vol.5, pp 36-46,October. [4] S.Braha ans A.Girgis, Fault location on a transission line using synchronized voltage easureents, EEE Transactions on Power Delivery, Vol.9, o.4,pp 69-6,October 4. [5] A.A.Gigis, D.G.Hart, and W.L.Peterson, A new fault location technique for two-and three-terinal lines, EEE Transactions on Power Delivery, Vol.7, o.,pp 98-7,January99. [6] R.K.Aggarwal, D.V.Coury, A.T.Johns and A.Kala, A practical approach for acurate fault location on extra high voltage teed feeders, EEE Transactions on Power Delivery, Vol.8, o.3, pp ,july 993. [7] Ying-Hong Lin, Chih-wen Liu and Chi-shan Yu, A ew Fault Locator for Three-Terinal Transission Lines Using Two-Terinal Synchrinized Voltage and Current Phasors, EEE Transactions on Power Delivery, Vol.7,o.,pp , April. [8] Cansin Y.Evrenosoglu and Ali Abur, Travelling Wave Based Fault Location for Teed Circuits, EEE Transactions on Power Delivery, Vol.,, o.,pp 5-,April 5. [9] Jan zyowsi, Eugeniusz Rosolowsi et al, A Fault-Location ethod for Application With Current Differential Relays of Three-Terinal Lines EEE Transactions on Power Delivery, Vol.,, o.4,pp 99-7, October 7. [] M.da Silva, M.Olesovicz, and D.V.Coury. A hybrid fault locator for three-terinal lines based on wavelet transfors, Electric Power Syste Research, Elsevier, 78(8) [] Suuar M.Braha, Fault Location Schee for a Multi-Terinal Transission Line Using Synchronized Voltage Measureents, EEE Transactions on Power Delivery, Vol.,, o.,pp 35-33,April 5. [] Shail Abdul Gafoor, Raana Rao P.V., Wavelet based fault detection, classification, location in transission lines, proc in EEE international conference, PECon 6, Malaysia, oveber 6. [3] Sang-Hee Kang, Dong-Gyu Lee, Soon-Ryul a, Peter A. Crossley and Yong-Cheol Kang, Fourier Trnasfor-Based Modified Phasor Estiation Method une to the Effect of the DC Offsets, EEE Transactions on Power Delivery, Vol.4, o.3, July 9. [4] A.M.Carter,R.K.Aggarwal, A.T.Johns, and Z.Q.Bo, Coputer-aided design of a new nonunit protection schee for EHV teed circuits, EE Proc.-Gener.Trans. Distrib., Vol.43,o., pp 4-5,March 996 [5] Suuar M.Braha, Phillip L. De Leon, and Rajesh G. Kavasseri, nvestigating the Option of Reoving the Antialiasing Filter fro Digital Relays, EEE Transactions on Power Delivery, Vol. 4, o. 4, pp , October 9. [6] Arun G. Phade, Jaes S. Thorp Coputer Relaying for Power Systes Research Studies Press Ltd., England, 994. [7] A.T.Johns, J.R.Platts Digital Protection for Power Systes EE Power Series 5, 995.