[S3,S0] REF_SEL. PLL (Phase Locked Loop)
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- Randolf Charles
- 5 years ago
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1 ABX02 FEATURES Selectable multipliers (x2.5, x2.75, x3, x4.25, x5, x5.5, x5.75, x6, x6.25, x0, x, x.5, x2, x2.5). Crystal input range, 3MHz to 3MHz (see Selection Table for detailed acceptable input ranges). Maximum output frequency: 32.5MHz 2 CMOS outputs. Selectable output drive (Standard or High-Drive). Selectable REF_CLK output. 3.3V operation. Available in 4-Pin SOIC. DESCRIPTION PIN CONFIGURATION (Top View) VDD XIN XOUT S3^ S2^ DRIVE_SEL^ GND ABX ^: Internal pull-up. S0^ S^ REF_SEL^ CLK2/ REF_CLK VDD CLK GND The ABX02 is a highly flexible XO with selectable multipliers and two CMOS outputs (one of which can be selected to be REF_CLK). Thanks to Abracon s advanced Phase Locked Loop technology, it allows a wide choice of selectable multipliers that permits the user to achieve useful frequencies from standard low cost crystals. It accepts fundamental parallel resonant mode crystals from 3 to 3MHz, and is ideal to generate 56.25MHz from a standard 25MHz crystal. BLOCK DIAGRAM [S3,S0] REF_SEL XOUT XIN Oscillator Amplifier PLL (Phase Locked Loop) CLK2/REF_CLK CLK Esperanza., Rancho Santa Margarita, Ca Ph: Fax: /2/05 Page
2 FREQUENCY SELECTION TABLE ABX02 S3 S2 S S0 Xtal Min Xtal Max Reserved Reserved X X X X X X X X X X X X X X 6.25 Multiplier Note: Internal pull-ups default S3, S2, S, and S0 to when not connected PIN DESCRIPTIONS Name Pin # Type Description VDD, P Power Supply. XIN 2 I Crystal input. XOUT 3 I Crystal output. S3 4 I S2 5 I Multiplier selector pins. These pins have an internal pull-up that will default SEL to when not connected to GND. DRIVE_SEL 6 I Selector pin. If DRIVE_SEL is 0, outputs are at high drive. If or not connected, outputs are standard drive (internal pull-up). GND 7,8 P Ground. CLK 9 O CLK output is the output of the reference frequency (crystal) after multiplication through the Phase Locked Loop. CLK2/REF_CLK 0 O CLK2 or REF_CLK output (depending on REF_SEL). CLK2 is in phase and at the same frequency as CLK. REF_CLK provides the same output as the crystal reference. REF_SEL 2 I Selector pin. This pin if set to 0 selects REF_CLK on pin 0. If not connected, it defaults to (pin 0 = CLK2). Internal pull-up. S 3 I Multiplier selector pins. These pins have an internal pull-up that will default S0 4 I SEL to when not connected to GND Esperanza., Rancho Santa Margarita, Ca Ph: Fax: /2/05 Page 2
3 ELECTRICAL SPECIFICATIONS. Absolute Maximum Ratings ABX02 PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS C Ambient Operating Temperature* TA C Junction Temperature TJ 25 C Lead Temperature (soldering, 0s) 260 C ESD Protection, Human Body Model 2 kv Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications Parallel Fundamental Mode Crystal Resonator Frequency FXIN 3 3 MHz (see Selection Table) Crystal Loading Rating CL (xtal) At VCON =.65V 6 pf Recommended ESR RE AT cut 30 Ω 3. General Electrical Specifications Fout<30MHz 5 Supply Current, Dynamic 5 pf IDD 30MHz<Fout<00MHz 30 ma (with Loaded Outputs) load Fout >00MHz 40 Operating Voltage VDD V Short Circuit Current ±50 ma 4. AC Electrical Specifications 0.8V ~ 2.0V with 0 pf load.5 Output Clock Rise Time 0.3V ~ 3.0V with 5 pf load ns 2.0V ~ 0.8V with 0 pf load.5 Output Clock Fall Time 3.0V ~ 0.3V with 5pF load Output Clock Duty Cycle % Esperanza., Rancho Santa Margarita, Ca Ph: Fax: /2/05 Page 3
4 ABX02 5. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Max. Absolute Jitter, peak-to-peak Short term ps Max. Jitter, cycle to cycle 60 ps Phase Noise, relative to carrier, 25Mhz(x5) 00 Hz offset 05 dbc/hz Phase Noise, relative to carrier, 25Mhz(x5) khz offset 25 dbc/hz Phase Noise, relative to carrier, 25Mhz(x5) 0kHz offset 30 dbc/hz Phase Noise, relative to carrier, 25Mhz(x5) 00kHz offset 25 dbc/hz Esperanza., Rancho Santa Margarita, Ca Ph: Fax: /2/05 Page 4
5 ABX02 PACKAGE INFORMATION 4 PIN Narrow SOIC ( mm ) SOIC Symbol Min. Max. A A B C D E H L e.27 BSC A e B D C E H L A ORDERING INFORMATION For part ordering, please contact our Sales Department: Fremont Blvd., Fremont, CA 94538, USA Tel: (50) Fax: (50) PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range ABX02 S C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE S=SOIC Order Number Marking Package Option ABX02SC ABX02SC 6-Pin SOIC (Tube) ABX02SC-T ABX02SC 6-Pin SOIC (Tape & Reel) Abracon Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Abracon is believed to be accurate and reliable. However, Abracon makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: Abracon s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Abracon Corporation Esperanza., Rancho Santa Margarita, Ca Ph: Fax: /2/05 Page 5
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Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO)
ICS558A-02 LVHSTL TO CMOS CLOCK DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS558A-02 Description The ICS558A-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs
ICS OSCILLATOR, MULTIPLIER, AND BUFFER WITH 8 OUTPUTS. Description. Features (all) Features (specific) DATASHEET
DATASHEET ICS552-01 Description The ICS552-01 produces 8 low-skew copies of the multiple input clock or fundamental, parallel-mode crystal. Unlike other clock drivers, these parts do not require a separate
ICS542 CLOCK DIVIDER. Features. Description. Block Diagram DATASHEET. NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
DATASHEET ICS542 Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide
PI6C49X0208. High Performance 1:8 Multi-Voltage CMOS Buffer
Features 8 single-ended outputs Fanout Buffer Up to 200MHz output frequency Ultra low output additive jitter = 0.01ps (typ.) Selectable reference inputs support Xtal (10~50MHz), singleended and differential
ICS663 PLL BUILDING BLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET ICS663 Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled
PCS3P73U00/D. USB 2.0 Peak EMI reduction IC. General Features. Applications. Product Description. Block Diagram
USB 2.0 Peak EMI reduction IC General Features 1x Peak EMI Reduction IC Input frequency: 10MHz - 60MHz @ 2.5V 10MHz - 70MHz @ 3.3V Output frequency: 10MHz - 60MHz @ 2.5V 10MHz - 70MHz @ 3.3V Supply Voltage:
Programmable Low Voltage 1:10 LVDS Clock Driver ADN4670
Data Sheet Programmable Low Voltage 1:10 LVDS Clock Driver FEATURES FUNCTIONAL BLOCK DIAGRAM Low output skew
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features
DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO. Description. Features. Block Diagram DATASHEET
DATASHEET ICS722 Description The ICS722 is a low cost, low-jitter, high-performance 3.3 volt designed to replace expensive discrete s modules. The on-chip Voltage Controlled Crystal Oscillator accepts
ICS660 DIGITAL VIDEO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET ICS660 Description The ICS660 provides clock generation and conversion for clock rates commonly needed in digital video equipment, including rates for MPEG, NTSC, PAL, and HDTV. The ICS660 uses
ICS276 TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS276 Description The ICS276 field programmable VCXO clock synthesizer generates up to three high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
ICS High Performance Communication Buffer. Integrated Circuit Systems, Inc. General Description. Block Diagram.
Integrated Circuit Systems, Inc. ICS905 High Performance Communication Buffer General Description The ICS905 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology
SM Features. General Description. Applications. Block Diagram
ClockWorks 10GbE (156.25MHz, 312.5MHz), Ultra-Low Jitter, LVPECL Frequency Synthesizer General Description The is a member of the ClockWorks family of devices from Micrel and provides an extremely low-noise
Description. This Clock Multiplier is the most cost-effective way to Input crystal frequency of 5-40 MHz
PT7C4512 Features Description Zero ppm multiplication error This Clock Multiplier is the most cost-effective way to Input crystal frequency of 5-40 MHz generate a high quality, high frequency clock outputs
3.3V ZERO DELAY CLOCK BUFFER
3.3V ZERO DELAY CLOCK BUFFER IDT2309 FEATURES: Phase-Lock Loop Clock Distribution 10MHz to 1 operating frequency Distributes one clock input to one bank of five and one bankd of four outputs Separate output
ICS309 SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH. Description. Features. Block Diagram DATASHEET
DATASHEET ICS309 Description The ICS309 is a versatile serially-programmable, triple PLL with spread spectrum clock source. The ICS309 can generate any frequency from 250kHz to 200 MHz, and up to 6 different
Crystals Oscillators Real-Time-Clocks Filters Precision Timing Magnetics Engineered Solutions
Real-Time-Clocks Magnetics Engineered Solutions WWW.ABRACON.COM Introduction Purpose: Objectives: Content: Learning Time: Introduce the ABLNO series of Ultra Low Phase Noise, Fixed Frequency & VCXO s and
ICS LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER. Features. Description. Block Diagram INA INB SELA
BUFFER Description The ICS552-02 is a low skew, single-input to eightoutput clock buffer. The device offers a dual input with pin select for glitch-free switching between two clock sources. It is part