80V, 50mA OPERATIONAL AMPLIFIERS

Transcription

1 8V, 5mA OPERATIONAL AMPLIFIERS JULY 2 REVISED NOVEMBER 23 FEATURES WIDE POWER-SUPPLY RANGE: ±1V to ±4V HIGH OUTPUT LOAD DRIVE: 5mA Continuous WIDE OUTPUT VOLTAGE SWING: 1V to Rail FULLY PROTECTED: Thermal Shutdown Output Current-Limited WIDE OPERATING TEMPERATURE RANGE: 4 C TO +125 C PACKAGE OPTIONS: TO22-7 DDPACK-7 Surface-Mount APPLICATIONS PIEZOELECTRIC CELLS TEST EQUIPMENT AUDIO AMPLIFIERS TRANSDUCER DRIVERS SERVO DRIVERS DESCRIPTION The and are low-cost operational amplifiers with high-voltage (8V) and high-current capabilities (5mA). The is unity-gain stable and has a gain bandwidth product of 1.8MHz, whereas the is optimized for gains greater than 5 and has a 7.5MHz bandwidth. The and are internally protected against over-temperature conditions and current overloads. Power supplies in the range of ±1V to ±4V can be used. Unlike most other power op amps, the and have ensured specifications over the entire power-supply range. These laser-trimmed, monolithic integrated circuits provide excellent low-level accuracy along with wide output swing. Special design considerations assure that the product is easy to use and free from phase inversion problems often found in other amplifiers. The and are available in TO22-7 and DDPAK-7 options. They are specified for a junction temperature range of 4 C to +125 C. 7-Lead Straight-Formed TO-22 (TA) 7-Lead Stagger-Formed TO-22 (TA-1) 7-Lead DDPAK (FA) Surface-Mount V IN+ NC V+ Flag V IN V V O V IN+ NC V+ Flag V IN+ NC V+ Flag V IN V V O V IN V V O NOTE: Tabs are electrically connected to V supply. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2-23, Texas Instruments Incorporated

2 ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage, V+ to V... 8V Signal Input Terminals, Voltage (2)... (V ).5V to (V+) +.5V Current (2)... 5mA Output Short-Circuit... Continuous Operating Temperature C to +125 C Storage Temperature C to +15 C Junction Temperature C Lead Temperature (soldering 1s, TO-22)... 3 C (soldering 3s, DDPAK) C NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than.5v beyond the supply rails should be current limited to 5mA or less. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. 2, 453

3 ELECTRICAL CHARACTERISTICS: ; V S = ±1V to ±4V Boldface limits apply over the specified junction temperature range, T J = 4 C to +125 C. At T J = +25 C, R L = 3.8kΩ connected to ground, and V OUT = V, unless otherwise noted. TA, FA PARAMETER CONDITION MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage V OS V S = ±4V, V CM = V, I O = V ±1 ±3 mv over Temperature ±6 mv Drift dv OS /dt ±5 µv/ C vs Power Supply PSRR V S = ±1V to ±4V, V CM = V 5 3 µv/v over Temperature 45 µv/v INPUT BIAS CURRENT (1) Input Bias Current I B V S = ±4V, V CM = V ±7 ±1 pa Input Offset Current I OS V S = ±4V, V CM = V ±1 ±1 pa NOISE Input Voltage Noise Density e n f = 1kHz 21 nv/ Hz Current Noise Density i n f = 1kHz 9 fa/ Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range V CM (V ) + 5 (V+).5 V Common-Mode Rejection Ratio CMRR V S = ±4V, 35V < V CM < 39.5V db over Temperature V S = ±4V, 35V < V CM < 39.5V 76 db INPUT IMPEDANCE Differential Ω pf Common-Mode V S = ±4V, 35V < V CM < 39.5V Ω pf OPEN-LOOP GAIN Open-Loop Voltage Gain A OL I O = 1mA, V S + 2V < V O < +V S 2V db over Temperature I O = 1mA, V S + 2V < V O < +V S 2V 17 db I O = 5mA, V S + 4V < V O < +V S 4V db over Temperature I O = 5mA, V S + 5V < V O < +V S 5.5V 15 db FREQUENCY RESPONSE Gain-Bandwidth Product GBW V S = ±4V 1.8 MHz Slew Rate SR V S = ±4V +7.2 / 1 V/µs Settling Time:.1% V S = ±4V, G = +1, 1V Step, C L = 1pF 2 µs.1% V S = ±4V, G = +1, 1V Step, C L = 1pF 5 µs Overload Recovery Time V IN Gain = V S 1 µs Total Harmonic Distortion + Noise THD+N V S = ±4V, V O = 3Vp-p, G = 5.8 % f = 1kHz, R L = 2kΩ OUTPUT Voltage Output V OUT I O = 5mA (V ) + 4. (V+) 4 V over Temperature I O = 5mA (V ) + 5 (V+) 5.5 V Voltage Output I O = 1mA (V ) + 2 (V+) 2 V over Temperature I O = 1mA (V ) + 2 (V+) 2 V Output Current ±5 ma Short-Circuit Current I SC ±125 ma Capacitive Load Drive C LOAD See Typical Characteristic SHUTDOWN FLAG Thermal Shutdown Status Output Normal Operation V S = ±4V.1 1. µa Thermally Shutdown V S = ±4V µa Junction Temperature Shutdown +16 C Reset from Shutdown +145 C POWER SUPPLY Supply Voltage Range V S ±1 ±4 V Quiescent Current (per amplifier) I Q I O = ±5.5 ±6.5 ma over Temperature ±7.5 ma TEMPERATURE RANGE Specified Range (junction) T J C Operating Range (junction) T J C Storage Range (ambient) T A C Thermal Resistance θ JC TO2-7 3 C/W DDPAK-7 3 C/W NOTE: (1) All tests are high-speed tested at +25 C ambient temperature. Effective junction temperature is +25 C, unless otherwise noted., 453 3

4 ELECTRICAL CHARACTERISTICS: ; V S = ±1V to ±4V Boldface limits apply over the specified junction temperature range, T J = 4 C to +125 C. At T J = +25 C, R L = 3.8kΩ connected to ground, and V OUT = V, unless otherwise noted. TA, FA PARAMETER CONDITION MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage V OS V S = ±4V, V CM = V, I O = V ±1 ±3 mv over Temperature ±6 mv Drift dv OS /dt ±5 µv/ C vs Power Supply PSRR V S = ±1V to ±4V, V CM = V 5 3 µv/v over Temperature 45 µv/v INPUT BIAS CURRENT (1) Input Bias Current I B V S = ±4V, V CM = V ±7 ±1 pa Input Offset Current I OS V S = ±4V, V CM = V ±1 ±1 pa NOISE Input Voltage Noise Density e n f = 1kHz 21 nv/ Hz Current Noise Density i n f = 1kHz 9 fa/ Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range V CM (V ) + 5 (V+).5 V Common-Mode Rejection Ratio CMRR V S = ±4V, 35V < V CM < 39.5V db over Temperature V S = ±4V, 35V < V CM < 39.5V 76 db INPUT IMPEDANCE Differential Ω pf Common-Mode V S = ±4V, 35V < V CM < 39.5V Ω pf OPEN-LOOP GAIN Open-Loop Voltage Gain A OL I O = 1mA, V S + 2V < V O < +V S 2V db over Temperature I O = 1mA, V S + 2V < V O < +V S 2V 17 db I O = 5mA, V S + 4V < V O < +V S 4V db over Temperature I O = 5mA, V S + 5V < V O < +V S 5.5V 15 db FREQUENCY RESPONSE Gain-Bandwidth Product GBW V S = ±4V 7.5 MHz Slew Rate SR V S = ±4V +23 / 38 V/µs Settling Time:.1% V S = ±4V, G = +5, 1V Step, C L = 1pF 1 µs.1% V S = ±4V, G = +5, 1V Step, C L = 1pF 1.5 µs Overload Recovery Time V IN Gain = V S 1 µs Total Harmonic Distortion + Noise THD+N V S = ±4V, V O = 3Vp-p, G = 5.8 % f = 1kHz, R L = 2kΩ OUTPUT Voltage Output V OUT I O = 5mA (V ) + 4. (V+) 4 V over Temperature I O = 5mA (V ) + 5 (V+) 5.5 V Voltage Output I O = 1mA (V ) + 2 (V+) 2 V over Temperature I O = 1mA (V ) + 2 (V+) 2 V Output Current ±5 ma Short-Circuit Current I SC ±125 ma Capacitive Load Drive C LOAD See Typical Characteristic SHUTDOWN FLAG Thermal Shutdown Status Output Normal Operation V S = ±4V.1 1. µa Thermally Shutdown V S = ±4V µa Junction Temperature Shutdown +16 C Reset from Shutdown +145 C POWER SUPPLY Supply Voltage Range V S ±1 ±4 V Quiescent Current (per amplifier) I Q I O = ±5.5 ±6.5 ma over Temperature ±7.5 ma TEMPERATURE RANGE T J Specified Range (junction) T J C Operating Range (junction) T A C Storage Range (ambient) C Thermal Resistance θ JC TO2-7 3 C/W DDPAK-7 3 C/W NOTE: (1) All tests are high-speed tested at +25 C ambient temperature. Effective junction temperature is +25 C, unless otherwise noted. 4, 453

5 TYPICAL CHARACTERISTICS At T J = +25 C, V S = ±4V, and R L = 3.8kΩ, unless otherwise noted. All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. Gain (db) OPEN-LOOP GAIN AND PHASE vs FREQUENCY Gain k 1k 1k 1M 1M Frequency (Hz) Phase Phase ( ) Gain (db) OPEN-LOOP GAIN AND PHASE vs FREQUENCY Gain k 1k 1k 1M 1M Frequency (Hz) Phase Phase ( ) 12 COMMON-MODE REJECTION RATIO vs FREQUENCY 14 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 1 12 CMRR (db) PSRR (db) PSRR +PSRR k 1k 1k 1M 1M Frequency (Hz) k 1k 1k 1M 1M Frequency (Hz) Voltage Noise (nv/ Hz) Current Noise (fa/ Hz) 1 1 e n INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY i n THD+N (%) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY A V = +5 V O = 3Vp-p R L = 6Ω, 2kΩ 6Ω 2kΩ 2kΩ 6Ω k 1k 1k 1M Frequency (Hz) k 1k 1k Frequency (Hz), 453 5

6 TYPICAL CHARACTERISTICS (Cont.) At T J = +25 C, V S = ±4V, and R L = 3.8kΩ, unless otherwise noted. All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. 45 MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY (V+) OUTPUT VOLTAGE SWING vs OUTPUT CURRENT Maximum Output Voltage (Vp-p) Without Slew-Induced Distortion 1k 1k 1k 1M Output Voltage Swing (V) (V+) 2 (V+) 4 (V+) 6 (V ) 8 (V ) + 4 (V ) + 2 (V ) 55 C +85 C +25 C 55 C +25 C +85 C Frequency (Hz) Output Current (ma) 12 OPEN-LOOP GAIN, POWER-SUPPLY REJECTION RATIO, AND COMMON-MODE REJECTION RATIO vs TEMPERATURE 1 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs TEMPERATURE AOL, PSRR, and CMRR (db) AOL CMRR PSRR Current (pa) I B +I B I OS Temperature ( C) Temperature ( C) 16 QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE 1 GAIN BANDWIDTH PRODUCT vs TEMPERATURE Short-Circuit Current (ma) I SC I Q +I SC Quiescent Current (ma) Gain Bandwidth (MHz) Temperature ( C) Temperature ( C) 6, 453

7 TYPICAL CHARACTERISTICS (Cont.) At T J = +25 C, V S = ±4V, and R L = 3.8kΩ, unless otherwise noted. All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. 45 SLEW RATE vs TEMPERATURE 2 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs COMMON-MODE VOLTAGE Slew () Slew Rate (V/µs) 25 +Slew () Current (pa) 1 5 +I B I B I OS 15 +Slew () Slew () Temperature ( C) Common-Mode Voltage (V) 13 QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE 15 OFFSET VOLTAGE PRODUCTION DISTRIBUTION I SC Short-Circuit Current (ma) I SC I Q 6 Quiescent Current (ma) Percentage of Amplifiers (%) Temperature ( C) Offset Voltage (mv) 2 OFFSET VOLTAGE DRIFT DISTRIBUTION 1 SETTLING TIME vs CLOSED-LOOP GAIN 15 Amplifiers (%) 1 5 Settling Time (µs) 1.1%.1%.1%.1% Offset Voltage Drift (µv/ C) Gain (V/V), 453 7

8 TYPICAL CHARACTERISTICS (Cont.) At T J = +25 C, V S = ±4V, and R L = 3.8kΩ, unless otherwise noted. All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. 6 5 SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE LARGE-SIGNAL STEP RESPONSE (G = 1, C L = 1pF) Overshoot (%) G = 1 G = 2 G = 4 1V/div G = +1 1 G = 6 G = Load Capacitance 2.5µs/div LARGE-SIGNAL STEP RESPONSE (G = 5, C L = 1pF) SMALL-SIGNAL STEP RESPONSE (G = 1, C L = 1pF) 1V/div 2V/div 2.5µs/div 1µs/div SMALL-SIGNAL STEP RESPONSE (G = 5, C L = 1pF) SMALL-SIGNAL STEP RESPONSE (G = 1, C L = 1pF) 2V/div 2V/div 5ns/div 2.5µs/div 8, 453

9 APPLICATIONS INFORMATION Figure 1 shows the connected as a basic noninverting amplifier. The can be used in virtually any op amp configuration. The is designed for use in configurations with gains of 5 or greater. Power-supply terminals should be bypassed with.1µf capacitors, or greater, near the power-supply pins. Be sure that the capacitors are appropriately rated for the power-supply voltage used. The and can supply output currents up to 5mA with excellent performance. V IN R1 1µF +.1µF V+ G = 1+ R 2 R 1 R 2.1µF 1µF + Flag (optional) Z L V O CURRENT LIMIT The and are designed with internal current-limiting circuitry that limits the output current to approximately 125mA. The current limit varies slightly with increasing junction temperature and supply voltage, as shown in the Typical Characteristics. Current limit, in combination with the thermal protection circuitry, provides protection from most types of overload conditions including short-circuit to ground. THERMAL PROTECTION The and have thermal shutdown circuitry that protects the amplifier from damage caused by overload conditions. The thermal protection circuitry disables the output when the junction temperature reaches approximately 16 C, allowing the device to cool. When the junction temperature cools to approximately 14 C, the output circuitry is automatically re-enabled. The thermal shutdown function is not intended to replace proper heat sinking. Activation of the thermal shutdown circuitry is an indication of excessive power dissipation or an inadequate heat sink. Continuously running the amplifier into thermal shutdown can degrade reliability. The Thermal Shutdown Indicator (Flag) pin can be monitored to determine if shutdown is occurring. During normal operation, the current output from the flag pin is typically 5nA. During shutdown, the current output from the flag pin increases to 14µA (typical). This current output allows for easy interfacing to external logic. Figure 2 shows two examples implementing this function. V FIGURE 1. Basic Circuit Connections. V OUT V OUT HCT logic has relatively wellcontrolled logic level. A properly chosen resistor value can assure proper logic high level throughout the full range of flag output current. Flag 1µA to 165µA 19.1kΩ Logic Ground +5V HCT Interface to virtually any CMOS logic gate by choosing a resistor value that provides an assured logic high voltage with the minimum (1µA) flag current. 39kΩ Logic Ground +5V CMOS Interfacing with HCT Logic Interfacing with CMOS Logic FIGURE 2. Thermal Shutdown Indicator., 453 9

10 POWER SUPPLIES The and may be operated from power supplies of ±1V to ±4V, or a total of 8V with excellent performance. Most behavior remains unchanged throughout the full operating voltage range. Parameters that vary significantly with operating voltage are shown in the Typical Characteristics. For applications that do not require symmetrical output voltage swing, power-supply voltages do not need to be equal. The and can operate with as little as 2V between the supplies or with up to 8V between the supplies. For example, the positive supply could be set to 7V with the negative supply at 1V or vice-versa. The tabs of the DDPAK-7 and TO22 packages are electrically connected to the negative supply (V ), however, these connections should not be used to carry current. For best thermal performance, the tab should be soldered directly to the circuit board copper area (see Heat Sinking section). POWER DISSIPATION Internal power dissipation of these op amps can be quite large. All of the specifications for the and may change with junction temperature. If the device is not subjected to internal self-heating, the junction temperature will be the same as the ambient. However, in practical applications, the device will self-heat and the junction temperature will be significantly higher than ambient. The following calculation can be performed to establish junction temperature as a function of ambient temperature and the conditions of the application. Consider the in a circuit configuration where the load is 6Ω and the output voltage is 2V. The supplies are at ±4V and the ambient temperature (T A ) is 4 C. The θ JA for the package plus heat sink is 3 C/W. First, the quiescent heating of the op amp is as follows: P D(internal) = I Q V S = 6mA 8V = 48mW The output current (I O ) can be calculated: I O = V O /R L = 2V/6Ω = 33.33mA The power being dissipated (P D ) in the output transistor of the amplifier can be calculated: P D(output stage) = I O (V S V O ) = 33.3mA (4 2) = 667mW P D(total) = P D(internal) + P D(output stage) = 48mW + 667mW = 1147mW The resulting junction temperature can be calculated: T J = T A + P D θ JA T J = 4 C mW 3 C/W = 74.4 C Where, V O = output voltage V S = supply voltage I O = output current R L = load resistance T J = junction temperature ( C) T A = ambient temperature ( C) θ JA = junction-to-air thermal resistance ( C/W) To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is activated. Use worst-case load and signal conditions. For good reliability, the thermal protection should trigger more than +35 C above the maximum expected ambient condition of your application. This ensures a maximum junction temperature of +125 C at the maximum expected ambient condition. Operation from a single power supply (or unbalanced power supplies) can produce even larger power dissipation because a larger voltage can be impressed across the conducting output transistor. Consult Application Bulletin SBOA22 at for further information on how to calculate or measure power dissipation. Power dissipation can be minimized by using the lowest possible supply voltage. For example, with a 5mA load, the output will swing to within 5.V of the power-supply rails. Power supplies set to no more than 5.V above the maximum output voltage swing required by the application will minimize the power dissipation. SAFE OPERATING AREA The Safe Operating Area (SOA curves, Figure 3) shows the permissible range of voltage and current. The safe output current decreases as the voltage across the output transistor (V S V O ) increases. For further insight on SOA, consult Application Report SBOA22. Output short circuits are a very demanding case for SOA. A short-circuit to ground forces the full power-supply voltage (V+ or V ) across the conducting transistor and produces a I O (ma) θ is total thermal resistance including junction-to-case. SAFE OPERATING AREA +85 C, θ = C, θ = θ2 +25 C, θ = C, θθ = 3 This graph is for +125 C max operating temperature V S V O (V) FIGURE 3. DDPAK-7 and TO22-7 Safe Operating Area. 1, 453

11 typical output current of 125mA. With ±4V power supplies, this creates an internal dissipation of 1W. This far exceeds practical heat sinking and is not recommended. If operation in this region is unavoidable, use the part with a heat sink. HEAT SINKING Power dissipated in the or will cause the junction temperature to rise. For reliable operation, the junction temperature should be limited to +125 C. Many applications will require a heat sink to assure that the maximum operating junction temperature is not exceeded. The heat sink required depends on the power dissipated and on ambient conditions. For heat sinking purposes, the tab of the DDPAK is typically soldered directly to a circuit board copper area. Increasing the copper area improves heat dissipation. Figure 4 shows typical thermal resistance from junction-to-ambient as a function of copper area. Depending on conditions, additional heat sinking may be required. Aavid Thermal Products Inc. manufactures surface-mountable heat sinks designed specifically for use with these packages. Further information is available on Aavid s web site, CAPACITIVE LOADS The dynamic characteristics of the and have been optimized for commonly encountered gains, loads, and operating conditions. The combination of low closedloop gain and capacitive load will decrease the phase margin and may lead to gain peaking or oscillations. Figure 5 shows a circuit that preserves phase margin with capacitive load. Figure 6 shows the small-signal step response for the circuit in Figure 5. Consult Application Bulletin SBOA15, at, for more information. V I R G 5kΩ C S 1.8nF +4V 4V R F 5kΩ CF 27pF 1nF Thermal Resistance, JA ( C/W) θ THERMAL RESISTANCE vs CIRCUIT BOARD COPPER AREA FA, FA Surface-Mount Package 1oz. copper Copper Area (inches 2 ) FIGURE 5. Driving Large Capacitive Loads. 2mV/div SMALL-SIGNAL STEP RESPONSE (G = 1, C L = 1nF) Circuit Board Copper Area 2.5µs/div FIGURE 6. Small-Signal Step Response for Figure 5. FA, FA Surface-Mount Package FIGURE 4. DDPAK Thermal Resistance versus Circuit Board Copper Area.,

12 INCREASING OUTPUT CURRENT In those applications where the 5mA of output current is not sufficient to drive the desired load, output current can be increased by connecting two or more s or s in parallel, as shown in Figure 7. Amplifier A1 is the master amplifier and may be configured in virtually any op amp circuit. Amplifier A2, the slave, is configured as a unity gain buffer. Alternatively, external output transistors can be used to boost output current. The circuit in Figure 8 is capable of supplying output currents up to 1A. Alternatively, the OPA547, OPA548, and OPA549 series power op amps should be considered for high output current drive, along with programmable current limit and output disable capability. FIGURE 7. Parallel Amplifiers Increase Output Current Capability. V IN V IN R 1 R 2 MASTER SLAVE R S (1) 1Ω R S (1) 1Ω NOTE: (1) R S resistors minimize the circulating current that can flow between the two devices due to V OS errors. R 1 R 2 +4V 4V C F R 3 (1) 1Ω TIP29C R 4.2Ω R 4.2Ω TIP3C NOTE: (1) R 3 provides current limit and allows the amplifier to drive the load when the output is between.7v and.7v. R L LOAD V O INPUT PROTECTION The and feature internal clamp diodes to protect the inputs when voltages beyond the supply rails are encountered. However, input current should be limited to 5mA. In some cases, an external series resistor may be required. Many input signals are inherently current-limited, therefore, a limiting resistor may not be required. Please consider that a large series resistor, in conjunction with the input capacitance, can affect stability. USING THE IN LOW GAINS The is intended for applications with signal gains of 5 or greater, but it is possible to take advantage of its high slew rate in lower gains using an external compensation technique in an inverting configuration. This technique maintains low noise characteristics of the architecture at low frequencies. Depending on the application, a small increase in high-frequency noise may result. This technique shapes the loop gain for good stability while giving an easily controlled 2nd-order low-pass frequency response. Considering only the noise gain (noninverting signal gain) for the circuit of Figure 9, the low-frequency noise gain (NG 1 ) will be set by the resistor ratios, whereas the high-frequency noise gain (NG 2 ) will be set by the capacitor ratios. The capacitor values set both the transition frequencies and the high-frequency noise gain. If this noise gain, determined by NG 2 = 1 + C S /C F, is set to a value greater than the recommended minimum stable gain for the op amp and the noise gain pole, set by 1/R F C F, is placed correctly, a very well controlled, 2nd-order low-pass frequency response will result. To choose the values for both C S and C F, two parameters and only three equations need to be solved. First, the target for the high-frequency noise gain (NG 2 ) should be greater than the minimum stable gain for the. In the circuit in Figure 9, a target NG 2 of 1 is used. Second, the signal gain of 1 in Figure 1 sets the low-frequency noise gain to NG 1 = 1 + R F /R G (= 2 in this example). Using these two gains, knowing the Gain Bandwidth Product (GBP) for the (7.5MHz), and targeting a maximally flat 2nd-order, low-pass Butterworth frequency response (Q =.77), the key frequency in the compensation can be found. For the values in Figure 9, the f 3dB will be approximately 18kHz. This is less than that predicted by simply dividing the GBP by NG 1. The compensation network controls the bandwidth to a lower value while providing good slew rate at the output and an exceptional distortion performance due to increased loop gain at frequencies below NG 1 Z. The capacitor values in Figure 1 are calculated for NG 1 = 2 and NG 2 = 1 with no adjustment for parasitics. Actual circuit values can be optimized by checking the smallsignal step response with actual load conditions. See Figure 9 for the small-signal step response of this, G = 1 circuit with a 1pF load. It is well-behaved with no tendency to oscillate. If C S and C F were removed, the circuit would be unstable. FIGURE 8. External Output Transistors Boost Output Current Up to 1 Amp. 12, 453

13 +4V SMALL-SIGNAL STEP RESPONSE (G = 1, C L = 1pF) V OUT V IN R G 5kΩ R F 5kΩ 2mV/div C S 1.8nF C F 2pF 4V NG 1 = 1 + R F /R G = 2 NG 2 = 1 + C S /C F = 1 2.5µs/div FIGURE 9. Compensation of the for G = 1. FIGURE 1. Small-Signal Step Response for Figure 9.,

14 PACKAGE OPTION ADDENDUM 24-Aug-218 PACKAGING INFORMATION Orderable Device Status FA/5 ACTIVE DDPAK/ TO-263 FAKTWT ACTIVE DDPAK/ TO-263 FAKTWTG3 ACTIVE DDPAK/ TO-263 (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) KTW 7 5 Green (RoHS & no Sb/Br) KTW 7 25 Green (RoHS & no Sb/Br) KTW 7 25 Green (RoHS & no Sb/Br) TA LIFEBUY TO-22 KC 7 5 Green (RoHS & no Sb/Br) TA-1 LIFEBUY TO-22 KVT 7 5 Green (RoHS & no Sb/Br) TA-1G3 LIFEBUY TO-22 KVT 7 5 Green (RoHS & no Sb/Br) TAG3 LIFEBUY TO-22 KC 7 5 Green (RoHS & no Sb/Br) FAKTWT ACTIVE DDPAK/ TO-263 KTW 7 25 Green (RoHS & no Sb/Br) TA ACTIVE TO-22 KC 7 5 Green (RoHS & no Sb/Br) TA-1 ACTIVE TO-22 KVT 7 5 Green (RoHS & no Sb/Br) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking (4/5) CU SN Level-3-245C-168 HR -4 to 125 F CU SN Level-3-245C-168 HR -4 to 125 F CU SN Level-3-245C-168 HR -4 to 125 F CU SN N / A for Pkg Type -4 to 125 T CU SN N / A for Pkg Type -4 to 125 T CU SN N / A for Pkg Type -4 to 125 T CU SN N / A for Pkg Type -4 to 125 T CU SN Level-3-245C-168 HR -4 to 125 F CU SN N / A for Pkg Type -4 to 125 T CU SN N / A for Pkg Type -4 to 125 T Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 1 RoHS substances, including the requirement that RoHS substance do not exceed.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS79B low halogen requirements of <=1ppm threshold. Antimony trioxide based flame retardants must also meet the <=1ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

15 PACKAGE OPTION ADDENDUM 24-Aug-218 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

16 PACKAGE MATERIALS INFORMATION 21-Nov-216 TAPE AND REEL INFORMATION *All dimensions are nominal Device FA/5 FAKTWT FAKTWT Package Type DDPAK/ TO-263 DDPAK/ TO-263 DDPAK/ TO-263 Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A (mm) B (mm) K (mm) P1 (mm) W (mm) Pin1 Quadrant KTW Q2 KTW Q2 KTW Q2 Pack Materials-Page 1

17 PACKAGE MATERIALS INFORMATION 21-Nov-216 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) FA/5 DDPAK/TO-263 KTW FAKTWT DDPAK/TO-263 KTW FAKTWT DDPAK/TO-263 KTW Pack Materials-Page 2

18 MECHANICAL DATA MPSF15 AUGUST 21 KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT.625 (1,587).585 (1,485) H.41 (1,41).385 (9,78).33 (7,7).297 (7,54) A.55 (1,4).45 (1,14).6 B.64 (1,63).56 (1,42).34 (7,72).296 (7,52).3 (7,62).252 (6,4).37 (9,4).187 (4,75) H.33 (8,38).65 (15,37).595 (15,11) A.179 (4,55) C.12 (,35). (,).19 (,48).14 (2,64).96 (2,44) H.17 (,43) C F.5 (1,27).34 (,86).22 (,57) C.26 (,66).14 (,36) ~3.1 (,25) M B A M C M.183 (4,65).17 (4,32) /A 8/1 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Lead width and height dimensions apply to the plated lead. D. Leads are not allowed above the Datum B. E. Stand off height is measured from lead tip with reference to Datum B. F. Lead width dimension does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum dimension by more than.3. G. Cross hatch indicates exposed metal surface. H. Falls within JEDEC MO 169 with the exception of the dimensions indicated. POST OFFICE BOX DALLAS, TEXAS 75265

19

20 MECHANICAL DATA MSOT1 OCTOBER 1994 KC (R-PSFM-T7) PLASTIC FLANGE-MOUNT PACKAGE.42 (1,67).38 (9,65).156 (3,96).146 (3,71).113 (2,87).13 (2,62) DIA.185 (4,7).175 (4,46).55 (1,4).45 (1,14).147 (3,73).137 (3,48).335 (8,51).325 (8,25) 1.2 (25,91) 1. (25,4) (3,18) (see Note C).3 (,76).26 (,66).1 (,25) M.5 (1,27).3 (7,62).25 (,64).12 (,3).122 (3,1).12 (2,59) 44251/ B 1/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Lead dimensions are not controlled within this area. D. All lead dimensions apply before solder dip. E. The center lead is in electrical contact with the mounting tab. POST OFFICE BOX DALLAS, TEXAS

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