AN-1536 APPLICATION NOTE

Transcription

1 AN- APPLICATION NOTE One Technology Way P.O. Box Norwood, MA -, U.S.A. Tel:.. Fax:.. ADuM Gate Driver Performance Driving APTMCAMCTAG SiC Power Switches by Martin Murnane INTRODUCTION In solar photovoltaics (PV) and energy storage applications, there is a trend towards increased power density, along with the ever present need of improved efficiency. A solution to this problem comes in the form of silicon carbide (SiC) power devices. SiC devices are wide band-gap devices that can operate at an increased voltage of > V dc and tend to have a low drain source impedance (RDSON). SiC devices also fill the need for reduced conduction and, therefore, increased efficiency. SiC devices can also exhibit fast switching speeds of > khz with low parasitic capacitance and associated charge during switching. However, disadvantages include a requirement for higher common-mode transient immunity (CMTI) greater than kv/μs required for gate drivers. Another disadvantage is that higher switching across the drain source of the SiC can lead to ringing at the gate of the device. These disadvantages can cause problems when driving higher voltage SiC devices, where significant power density improvement can be achieved by their implementation. One combination of gate driver and SiC that can solve these problems is the ADuM and the Microsemi APTMCAMCTAG module. The ADuM gate driver is a single-channel device with a typical drive capability of A source and sink at a V operating voltage (VDD to VSS). It has a minimum CMTI of kv/μs. The APTMCAMCTAG power module is a half bridge SiC device with a V collector emitter voltage rating, RDSON of mω, and a continuous current capability of A. Its gate source voltage (VGS) rating is V to + V. Figure. ADuM Gate Drive Module - Rev. Page of

2 AN- TABLE OF CONTENTS Introduction... Revision History... Test Setup... Electrical Setup... Test Results... No Load Testing... Application Note Load Testing... High Current Testing... PWM Delay... Schematic... Conclusion... REVISION HISTORY / Revision : Initial Version Rev. Page of

3 Application Note TEST SETUP ELECTRICAL SETUP The system test circuit setup is shown in Figure. A dc voltage is applied to the inputs across the full half bridge, where a decoupling capacitor of µf is added to the input stage. The output stage is an inductor capacitor (LC) filter stage of µh and µf, filtering the output into the load, R, of Ω to Ω. Table shows a list of the test setup power components. A physical setup is shown in Figure, and Table details the setup equipment used for testing. Figure. System Test Circuit Setup Table. Test Setup Power Components Equipment Value U V to V C μf L μh C μf R Ω to Ω AN- - Table. Setup Equipment Used for Testing Equipment Manufacturer Type Oscilloscope Keysight DSO-X T DC Supply Delta Elektronika SM -AR- (two in serial) Gate Driver Board Watt&Well ADUM-WW-MS- SN Waveform Generator Agilent A Current Probe Hioki Passive Voltage Probe Keysight NA MHz Passive High Voltage Probe Elditest GE MHz HV+ L C R HV+ Figure. Physical Setup - Rev. Page of

4 AN- Application Note TEST RESULTS NO LOAD TESTING Table. No Load Testing Figure Assignments Test VHV (V) Switching Frequency, fsw (khz) Duty Cycle (%) IIN (A) Figures. Figure and Figure. Figure and Figure. Figure and Figure VHV is the differential voltage between HV+ and HV. IIN is the input current through U. Table. No Load Testing Temperature Summary Test VHV (V) fsw (khz) Ambient Temperature ( C) Heatsink Temperature ( C) DC-to-DC Power Supply Temperature, High-Side ( C) DC-to-DC Power Supply Temperature, Low-Side ( C) Gate Driver Temperature, High-Side ( C) Gate Driver Temperature, Low-Side ( C) In the latest revision of ADuM, some changes include: a capacitor of. nf was added on the gates of the power metaloxide semiconductor field effect transistors (MOSFETs), Q, and Q. CG decoupling capacitors of nf have been added to VHV. Table and Table summarize of the results observed, and Figure through Figure show the proof of results. Test and Test were carried out at V, respectively, at khz and khz switching frequencies, whereas Test was carried out at V at a switching frequency of khz. Y Y CH V CH.V CH.V - Figure. VHV = V, fsw = khz, No Load, Turn On Y Y CH.V CH.V CH V Figure. VHV = V, fsw = khz, No Load, Turn Off - Rev. Page of

5 Application Note AN- Y Y Y Y CH V CH.V CH.V - CH V CH.V CH.V - Figure. VHV = V, fsw = khz, No Load, Turn On Figure. VHV = V, fsw = khz, No Load, Turn On Y Y Y Y CH V CH.V CH.V - CH V CH.V CH.V - Figure. VHV = V, fsw = khz, No Load, Turn Off Figure. VHV = V, fsw = khz, No Load, Turn Off Rev. Page of

6 AN- Application Note LOAD TESTING Table. Load Testing Test VHV (V) fsw (khz) Duty Cycle (%) IOUT (A) VOUT (V) POUT (W) IIN (A) Figures.. Figure and Figure.. Figure and Figure... Figure and Figure.. Figure and Figure IOUT is the output current in Load Resistor R. VOUT is the output voltage across R. POUT is the output power (IOUT VOUT). IIN is the input current through U. Board configuration is similar to the test setup of the No Load Testing section. Table is a summary of the results observed for load testing, and Figure through Figure show the proof of results. Output voltage (VOUT) was measured as the voltage across R. The test results show some Miller feedback on VGS, but VGS remains at the V level at the gate of the SiC. At V, some ringing is seen on VDS, but it is < V of the input dc voltage. This design shows how the ADuM can drive SiC MOSFETs with clean performance. CH.V A CH.V CH V Figure. VHV = V, fsw = khz, POUT = W, Turn On - CH.V CH.V A CH.V Figure. VHV = V, fsw = khz, POUT = W, Turn On - CH.V A CH.V CH V Figure. VHV = V, fsw = khz, POUT = W, Turn Off - CH.V CH.V A CH.V Figure. VHV = V, fsw = khz, POUT = W, Turn Off - Rev. Page of

7 Application Note AN- CH.V A CH.V CH V Figure. VHV = V, fsw = khz, POUT =. W, Turn On - CH.V A CH mv CH V Figure. VHV = V, fsw = khz, POUT = W, Turn On - CH.V A CH.V CH V Figure. VHV = V, fsw = khz, POUT =. W, Turn Off - CH.V CH mv CH V Figure. VHV = V, fsw = khz, POUT = W, Turn Off - Rev. Page of

8 AN- Application Note HIGH CURRENT TESTING Table. High Current Testing Test VHV (V) fsw (khz) Duty Cycle (%) IOUT (A) VOUT (V) PIN (W) IIN (A) Figures.. Figure and Figure... Figure and Figure. Figure and Figure Duty cycle high side. IOUT is the output current in Load Resistor R. VOUT is the output voltage across R. PIN is the input power (IIN VHV) IIN is the input current through U. Board configuration is similar to the test setup of the No Load Testing section. A Regatron power supply was used in this test. Table is a summary of the results observed for high current testing, and Figure through Figure show the proof of results. VOUT was measured as the voltage across R. CH.A CH.V A CH.V CH V Figure. VHV = V, fsw = khz, Output Current (IOUT) =. A, Turn On - CH.A CH.V CH.V CH V Figure. VHV = V, fsw = khz, Output Current (IOUT) =. A, Turn On - CH.A CH.V A CH.V CH V Figure. VHV = V, fsw = khz, Output Current (IOUT) =. A, Turn Off - CH.A CH.V A CH.V CH V Figure. VHV = V, fsw = khz, Output Current (IOUT) =. A, Turn Off - Rev. Page of

9 Application Note AN- PWM DELAY The ADuM input and output PWM measures the delay between the two signals. The measures have been made directly on the input and output pins of the ADuM. The delay is to. ns. CH.A CH V CH.V A CH.V Figure. VHV = V, fsw = khz, Output Current (IOUT) =. A Pulse- Width Modulation (PWM) Delay, Turn On - CH.A CH.V X X CH.V A CH.V Figure. Delay Between Input and Output PWM, Turn On - CH.A CH V CH.V A CH.V Figure. VHV = V, fsw = khz, Output Current (IOUT) =. A, Turn Off - Y CH.A CH V X X Y CH.V A CH.V Figure. Delay Between Input and Output PWM, Turn Off - Rev. Page of

10 AN- Application Note SCHEMATIC PRIMARY Phase J LV D NHW--F U LTEMSE#PBF VIN BST EN/UV SY SW INTVcc TR/SS PG RT FB +V C u -ISO-H-REC -ISO-H SOURCE-H -ISO-H U TP P Vcc MCVHCGDFTG PWM_H R Gnd R R C D R k CG (NP) FDLL k p C C CG (NP) p n U TP MCVHCGDFTG P Vcc R PWM_L R Vcc U MVHCGDFTG C R R R CG (NP) D k k FDLL p C C C CG (NP) p.ns deadtime n n F F M M M M Gnd C C n n R +V Vcc U MVHCGDFTG C n PM.// BLK LV = V ± V PWM_L PWM_H V C u C u HTSW---G-D JA M_SS M_SS JB JC JD JE JF V JG JH JI JJ JK JL M_SS M_SS C n READY_HS RESET_HS READY_LS RESET_LS V R k M_SS M_SS V C C R R M_SS M_SS FAULT_HS FAULT_LS C n L u R k R k C CG (NP) p +V C u TP R m C CTCB u TP R k LED SML-LTT U LTHMSE C u C u R k C u R U TP LTHMSE TP R k -ISO-L P/P : turns AWG S : turns AWG L D VS-BQTRPBF SWA P S +V S P SWB D VS-BQTRPBF HV_RTN C BND : transformer u add kapton tape under the core Phase R Vcc Gnd U MCVHCGDFTG R Vcc U MCVHCGDFTG R i i i i i V in R k R k UVLO SY OVLO/DC RDC RT ILIM/SS RBIAS SWA SWB D VS-BQTRPBF D VS-BQTRPBF u D VS-BQTRPBF D VS-BQTRPBF GN D C u L -ISO-H-REC C C u R C n -ISO-H D BZXCLTG U SCHDN LTCS-#PBF OUT +V C u R SOURCE-H -ISO-H IN NTC NTC R R C UVLO =.V OVLO = disable fsw = khz tss = us Ilim = disable R R R k C n R R k C u BND : transformer add kapton tape under the core U L P P Vin+ DC/DC Vout+ +V Com -V Vout- Vin- RPD P/P : turns AWG S : turns AWG S S -ISO-H -ISO-H C C +V-ISO-H C R n D k D u D D VS-BQTRPBF R D n R C STTHU R R VS-BQTRPBF k U -ISO-H CG (NP) BZXCVLTG STTHU k k VSS VSS -ISO-H p Vi+ GATE_SENSE Vi- VOUT_ON -ISO-H READY_HS R READY VDD -ISO-H FAULT_HS FAULT VOUT_OFF RESET_HS R RESET -ISO-H VDD DESAT R C R VSS VSS -ISO-H TP CG (NP) R R C ADUMBRWZ R n +V-ISO-H -ISO-H R R TP C R n k n SOURCE-H -ISO-L R C TP C C C R R TP n k u n R SOURCE-L R n R R R R k k U R R +V-ISO-L VSS VSS -ISO-L Vi+ GATE_SENSE +V-ISO-L Vi- VOUT_ON READY_LS R R READY VDD -ISO-L FAULT_LS k D FAULT VOUT_OFF RESET_LS D D STTHU RESET -ISO-L VS-BQTRPBF R VDD DESAT R C C VSS VSS -ISO-L CG (NP) D R CG (NP) VS-BQTRPBF D k n ADUMBRWZ BZXCVLTG C STTHU p -ISO-L -ISO-L -ISO-L -ISO-L HV_RTN n Vout+ +V Com -V Vout- U Vin+ DC/DC Vin- RPD -ISO-L-REC C u C u R k C u R SOURCE-L -ISO-L -ISO-H k V in UVLO SY OVLO/DC RDC RT ILIM/SS RBIAS -ISO-L-REC L D u VS-BQTRPBF C C u D VS-BQTRPBF -ISO-L -ISO-L R D C BZXCLTG n R U OUT C SCHDN +V u GN D R k C R R R R R k k n LTCS-#PBF Stud M J HV Q D NTC NTC Q NTC G CR NTC E DS MP J Q Stud M G CR E S APTMCAMCTAG HV_RTN J Stud M F F SOURCE-L -ISO-L k UVLO =.V OVLO = disable fsw = khz tss = us Ilim = disable C MKP n C MKP n C CG (NP) n C CG (NP) n HV/ i HV/ i HV/ i C C CG (NP) CG (NP) n n C CG (NP) n C CG (NP) n IN CLASS NAME: HV/ CLASS NAME: HV/ CLASS NAME: HV/ - Figure. ADuM Gate Drive Board Schematic Rev. Page of

11 Application Note COLUSION The ADuM gate driver has the current drive capability, the correct power supply range, and a strong CMTI capability of > kv/µs to deliver clean performance when driving SiC MOSFETs. AN- The test results provide data showing a solution is available for isolated power supply, high voltage gate drivers driving SiC. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN--/() Rev. Page of