Performance Analysis of Inverter using Domino Logic

Transcription

1 Performance Analysis of Inverter using Domino Logic AdarshRana M.E Scholar, Electronics& Communication Department NITTTR, Sector-26,Chandigarh, India RajeshMehra Associate Professor, Electronics& Communication Department NITTTR,Sector-26,Chandigarh,India Abstract-In this paper an inverter circuit has been designed and simulated using domino logic on 65nm and 90nm technology. The domino logic circuit is the canonical precharged logic gate circuit. The Precharged circuits offer both low area and power. Domino CMOS has the advantage of higher integration density and lower power dissipation. The domino logic based inverter has been designed and simulated using DSCH and microwind CAD tools. For basic logic And gate, the performance of developed inverter has been compared with conventional inverter in terms of Area andspeed.the results show that And gate using domino logic based inverter has consumed 50% less Area and 20% less power as compared to that using conventional inverter. Both logic circuits have been designed and compared on 65nm and 90nm technology. Keywords- Cmos Inverter, Domino logic,dynamic logic,power consumption,surface area. I. INTRODUCTION In Dynamic logic, problem arises when cascading one gate to the next. The precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state.the "precharge" of the second gate cannot be restored until the next clock cycle, so there is no recovery from this error. [1] Thus to cascade dynamic logic gates, one solution is Domino Logic, which inserts an ordinary static inverter between stages.while using domino logic we are using apfet (Since one of the objective ofusing Dynamic Logic is to avoid pfets where possible, due to their low speed), the two reasons it works well are, First, there is no fanout to multiple pfets. The dynamic gate connectsto exactly one inverter, so the gate is still very fast.sincein Dynamic Logic gates the inverter connects to only nfets,it too is very fast. Secondly the size of pfet in an inverter can be made smaller than in some types of logic gates. [2] Dynamic logic is widely used in high performance microprocessors and is attractive for high speed circuits. II. DOMINO LOGIC A Dynamic logic works on in two phases,first to pre charge the storage node,then to selectively discharge it, called Evaluation phase, The load capacitance of this gate becomes charged. During the evaluation phase, CLK is kept high. Domino logic is a CMOS based evaluation of the dynamic logic techniques which are based on the either PMOS or NMOS transistors.it allows a rail-to-rail logic swing.the purpose of this development was to speed up the circuits. The outputs of dynamic gate connect to one inverter, in domino logic. In domino logic, cascade structure consisting of several stages, the evaluation of each stage ripples the next stage evaluation, similar to a domino falling one after the other[4]. Once fallen, the node states cannot return to 1 (until the next clk cycle), just as dominos, once fallen, cannot stand up. Thus thestructure is termed as domino CMOS logic. In contrast to other 1

2 solutions to the cascade problem, Domino logic is the most popular dynamic logic.thesedynamic cicuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits.from speed point of view Domino logic runs times faster than static CMOS logic because dynamic gates present much lower input capacitance for the same output current and a lower switching threshold.functioning of Domino circuits are very similar to the clocked CMOScircuit.In domino logic,to precharge and evaluate a cascaded set of dynamic logic blocks a single clock is used. As is shown in Figure.1 this Domino logic circuitry incorporates a static CMOS buffer into each logic gate. During the precharge phase or cycle,the CLK=0,consequently all output nodes all (A') of the dynamic gates are precharged to high, through the PMOS transistor T1, and thus the outputs (A) of the corresponding inverter buffers are precharged to low. Since all transistors of subsequent dynamic gates are fed from such buffers, these will be turned off during the precharge phase. Fig 1. A Domino logic circuit Next is the evaluation phase or cycle, during which either,node A' are discharged through NMOS transistor T2 or they remain high,according to the realized function. Thus the outputs A of the buffer either reaches high or remain low, respectively.as shown in fig.2,in Domino logic the transition of nodes A is always from low to high and is rippled through the logic from primary inputs to the primary outputs.gates evaluate sequentially but precharge in parallel.thus evaluation is more critical than precharge.each domino gate triggers next one,like a string of dominos toppling over.since there are cascaded logic blocks,the evaluation of a stage causes the next stage to evaluate and proceed so on.there is no restriction on number of logic stagesbe cascaded, provided that they can be evaluated within the evaluate phase of the clock. Thus thedomino logic design precharged by clock presents applications with high performance in terms ofreduced area requirements and as well as reduced power dissipation. 2

3 Fig.2 Precharge and Evaluate in Domino logic be cascaded, provided that they can be evaluated within the evaluate phase of the clock. Thus the Domino logic design precharged by clock presents applications with high performance in terms of reduced area requirements and as well as reduced power dissipation. III.PROPOSED APPROACH In this paper we design and compare basic inverter and domino logic inverter and also design and compare their application in AND logic by basic and domino logic itself. In this work, we tried to show a design methodology to design domino logic circuits; as well as experimental results validating this methodology. After designing each block of the gates of CMOS and DOMINO we will show the comparison between AND gate implementation by CMOS and DOMINO technologies on 90nm and 65nm scale foundary and try to distinguish that how the DOMINO logic circuits designs are low power and high speedcircuits,and require less area than CMOS designs, we perform all the experimental designing and simulation using DSCH and microwind CAD tools. The Inverter of CMOS logic consist of one pmos transistor and one nmos transistor. when the input A is 0, the NMOS transistor is OFF and PMOS transistor is ON. Thus the output is pulled up to 1 because it is connected to VDD but not to GND. Conversely, when A is 1, the NMOS transistor is ON,the PMOS is OFF and the output is pulled down to 0. This is summarized in the truth table. Table 1:- Inverter truth table INPUT A OUTPUT NOT A On simulation through DSCH we get Fig.3 showing the Schematic diagram of CMOS Inverter,and Fig.4 showing Waveform for CMOS Inverter, similarly Fig.5 showing Schematic diagram of Domino Inverter and Fig.6 showing Waveform for Domino Inverter. 3

4 Fig.3 Schematic diag of CMOS Inveter Fig.4 Waveform of CMOS Inverter Fig.5 Schematic of Domino Inverter CMOS AND Gate The truth table of AND gate is summarized in 4

5 TABLE:-2 Two input AND Gate truth table A B A.B The AND gate can be defined as an electronic circuit that gives a high output 1, only if all its inputs arehigh. The AND operation is represented by a dot (.) A.B.Here in Fig.7 and Fig.8,we present the Schematic and Waveform of CMOS AND Gate respectively. Fig.6 Waveform of Domino Inverter Fig.7 Schematic of CMOS AND Gate Fig.8 Waveform of CMOS AND Gate 5

6 Domino AND Gate Fig.9 Schematic of Domino AND Gate Fig.10 Waveform of Domino AND IV. SIMULATION RESULT The layout and simulation have been performed on Microwind and DSCH for CMOS AND & Domino AND Gate.First the schematics& Waveforms are drawn using DSCH.Then a Verilog file is generated indsch which is then compiled in Microwind tool to generate the layout and to estimate layout area. Simulations are done using BSIM4 MODEL.BSIM ie,berkeley Shortchannel IGFET Model [5] refers to family of MOSEFT transistor models for integrated circuit design. Fig 11. Flow Graph for Layout Area and other parameter estimation. 6

7 Basic inverter layout and Analog Simulation Domino inverter layout and Analog Simulation CMOS AND Gate layout and Analog Simulation On 90nm 7

8 On 65nm Domino AND Gate layout and Analog Simulation On 90nm On 65nm 8

9 Table 3. power and layout comparison of CMOS AND Gate and Domino AND Gate Parameter Cmos AND Domino AND 90nm 65nm 90nm 65n m Area(μm 2 ) Power(mw) V.CONCLUSION In this work an attempt has been made to simulate And gate. Domino circuits have offered an improved performance results. On comparing the power consumption and layout area of cmos and & domino and method. The domino and is more effective in reducing power consumption as well as layout area.the result is simulated with microwind software and DSCH,and compare at different technology of 90nm and 65nm. Thus we conclude that the power and area performance of Domino Logic is far better than CMOS logic. The number of gates of n type also provides faster response in Domino logic. VI. REFERENCES 1]Knepper. "SC571 VLSI Design Principles," Chapter 5: Dynamic Logic Circuits 2] Abdel-Hafeez and Ranjan. Single Rail Domino Logic For Four-Phase Clocking Scheme. 3]Rakhi R. Agrawal and S.A.Ladhake, Systematic Design of High-Speed and Low-Power Domino Logic International Journal of Advanced Research in Computer Science and Software Engineering, Volume 2,pp ,March ]R.K. Brayton, R. L. Rudell, and A. L. Sangiovanni-Vincentelli,-MIS: A Multiple-LeveLogic Optimization System, in IEEE Trans.on Computer Aided Design, pp ,vol. 6, No. 6, [5] Sheu, Scharfetter, Ko, and Jeng (August 1987). "BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors". IEEE Journal of Solid State Circuits. SC-22: [6]Vojin G. Oklobdzija and Robert K. Montoye, Design-Performance Trade-Offs in CMOS-Domino Logic, In IEEE Journal of Solid-State Circuits, Volume sc-21, No. 2. 9