MP2259 1A, 16V, 1.4MHz Step-Down Converter

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1 The Future of Analog IC Technology DESCRIPTION The MP9 is a monolithic integrated stepdown switch mode converter with an internal power MOSFET. It achieves A continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. The MP9 requires a minimum number of readily available standard external components. The MP9 is available in TSOT- and SOT- packages. FEATURES MP9 A, V,.MHz Step-Down Converter A Output Current 0.Ω Internal Power MOSFET Switch Stable with Low ESR Output Ceramic Capacitors Up to 9% Efficiency 0.μA Shutdown Mode Fixed.MHz Frequency Thermal Shutdown Cycle-by-Cycle Over Current Protection Wide.V to V Operating Input Range Output Adjustable from 0.8V to V Available in TSOT- and SOT- Packages APPLICATIONS Hand Disk Drive xdsl Modems Cable Set-Top Box For MPS green status, please visit MPS website under Quality Assurance MPS and The Future of Analog IC Technology are Registered Trademarks of Monolithic Power Systems, Inc. ICAL APPLICATION V V OFF ON MP9 CB 0nF D A EFFICICY (%) Efficiency vs Load Current VOUT = V VOUT =.V V = V LOAD CURRT (ma) MP9-EC0 MP9 Rev

2 ORDERG FORMATION Part Number Package Top Marking Temperature MP9DJ* TSOT- J9 0 C to 8 C Part Number Package Top Marking Temperature MP9DT** SOT- K 0 C to 8 C * For Tape & Reel, add suffix Z (eg. MP9DJ Z); For RoHS compliant packaging, add suffix LF. (eg. MP9DJ LF Z) * * For Tape & Reel, add suffix Z (eg. MP9DT Z); For RoHS compliant packaging, add suffix LF (eg. MP9DT LF Z) PACKAGE REFERCE TOP VIEW TOP VIEW MP9_PD0_TSOT MP9_PD0_SOT TSOT- ABSOLUTE MAXIMUM RATGS () Supply Voltage V... 0V... V V BS... V All Other Pins... 0.V to V Continuous Power Dissipation (T A = C) () TSOT W SOT W Junction Temperature...0 C Lead Temperature...0 C Storage Temperature... C to 0 C Recommended Operating Conditions () Supply Voltage V...V to V Output Voltage to V Maximum Junction Temp. (T J )... C SOT- Thermal Resistance () θ JA θ JC TSOT C/W SOT C/W Notes: ) Exceeding these ratings may damage the device. ) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction-toambient thermal resistance θ JA, and the ambient temperature T A. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX)=(T J (MAX)- T A )/ θ JA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. ) The device is not guaranteed to function outside of its operating conditions. ) Measured on JESD-7 -layer PCB. MP9 Rev

3 ELECTRICAL CHARACTERISTICS V = V, T A = C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Feedback Voltage V.V V V V Feedback Current I V = 0.8V 0 na V = V µa Switch-On Resistance R DS(ON) 0. Ω Switch Leakage V = 0V, = 0V 0 μa Current Limit ().8 A Oscillator Frequency f V = 0.V. MHz Fold-back Frequency V = 0V 0 KHz Maximum Duty Cycle V = 0.V 8 % Minimum On-Time t ON 00 ns Under Voltage Lockout Threshold Rising..8. V Under Voltage Lockout Threshold Hysteresis 00 mv Input Low Voltage 0. V En Input High Voltage. V Input Current V = V 7 V = 0V - Supply Current (Shutdown) V = 0V 0. μa Supply Current (Quiescent) V = V, V = V.0 ma Thermal Shutdown 0 C Note: ) Slope compensation changes current limit above 0% duty cycle. μa P FUNCTIONS Pin # Name Description Bootstrap. This capacitor is needed to drive the power switch s gate above the supply voltage. It is connected between and BS pins to form a floating supply across the power switch driver. Ground. This pin is the voltage reference for the regulated output voltage. For this reason care must be taken in its layout. This node should be placed outside of the D to C ground path to prevent switching current spikes from inducing voltage noise into the part. Feedback. An external resistor divider from the output to, tapped to the pin sets the output voltage. To prevent current limit run away during a short circuit fault condition the frequency foldback comparator lowers the oscillator frequency when the voltage is below 0mV. On/Off Control Input. Pull above.v to turn the device on. Supply Voltage. The MP9 operates from a.v to V unregulated input. C is needed to prevent large voltage spikes from appearing at the input. Switch Output. MP9 Rev

4 ICAL PERFORMANCE CHARACTERISTICS V = V, =.V, L =.7µH, C = 0µF, C = µf, T A = ºC, unless otherwise noted. CURRT LIMIT (A) Current Limit vs Duty Cycle DUTY CYCLE (%) AC Coupled 0mV/div. OAD 0mV/div. 00mA/div. Steady State Test I OUT = 0.A 00ns/div. Short Circuit Entry Short Circuit Recovery Start-up through Enable No Load V V/div. V/div. V/div. V/div. 00mA/div. Start-up through Enable I OUT = A Resistive Load Shut-down through Enable No Load Shut-down through Enable I OUT = A Resistive Load V V/div. V V/div. V/div. V V/div. V/div. V/div. MP9 Rev

5 OPERATION The MP9 is a current mode buck regulator. with EA output voltage proportional to the peak inductor current. At the beginning of a cycle, M is off. The EA output voltage is higher than the current sense amplifier output, and the current comparator s output is low. The rising edge of the.mhz CLK signal sets the RS Flip-Flop. Its output turns on M then connects the pin and inductor to the input supply. The increasing inductor current is sensed and amplified by the Current Sense Amplifier. Ramp compensation is summed to Current Sense Amplifier output and compared to the Error Amplifier output by the PWM Comparator. When the sum of the Current Sense Amplifier output and the Slope Compensation signal exceeds the EA output voltage, the RS Flip- Flop is reset and M is turned off. The external Schottky rectifier diode (D) conducts the inductor current. If the sum of the Current Sense Amplifier output and the Slope Compensation signal does not exceed the EA output for a whole cycle, then the falling edge of the CLK resets the Flip-Flop. The output of the Error Amplifier integrates the voltage difference between the feedback and the 0.8V bandgap reference. The polarity is such that a pin voltage lower than 0.8V increases the EA output voltage. Since the EA output voltage is proportional to the peak inductor current, an increase in its voltage increases current delivered to the output. x0 CURRT SSE AMPLIFIER -- REGULATOR REGULATOR OSCILLATOR.MHz pf -- CURRT LIMIT COMPARATOR S R R Q DRIVER M REFERCE 7pF EA -- ERROR AMPLIFIER -- PWM COMPARATOR MP9_F0_BD0 Figure Functional Block Diagram MP9 Rev

6 APPLICATION FORMATION Setting the Output Voltage The external resistor divider is used to set the output voltage (see the schematic on front page). The feedback resistor R also sets the feedback loop bandwidth with the internal compensation capacitor (see Figure ). R can be determined by: R = R 0.8V Table Resistor Selection for Common Output Voltages (V) R (kω) R (kω) (%).9 (%). 9.9 (%).7 (%). 9.9 (%). (%) 9.9 (%) 9. (%) Selecting the Inductor A µh to 0µH inductor is recommended for most applications. For highest efficiency, the inductor s DC resistance should be less than 00mΩ. For most designs, the required inductance value can be derived from the following equation: V L = V OUT (V ΔI L V f OUT OSC Where Δ is the inductor ripple current. Choose an inductor with a rating current higher than the maximum load current. The maximum inductor peak current can be calculated from: ΔIL IL(MAX) = ILOAD Under light load conditions below 00mA, a larger inductance is recommended for improved efficiency. Selecting the Input Capacitor The input capacitor (C) reduces the surge current drawn from the input and the switching noise from the device. The input capacitor impedance at the switching frequency should be less than the input source impedance to prevent high frequency switching current from passing through the input. Ceramic capacitors ) with XR or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a.7µf capacitor is sufficient. Selecting the Output Capacitor The output capacitor (C) keeps output voltage ripple small and ensures loop stability. The output capacitor impedance should be low at the switching frequency. Ceramic capacitors with XR or X7R dielectrics are recommended for their low ESR characteristics. A 0µF~ µf capacitor is good for most applications. PCB Layout Guide PCB layout is very important to achieve stable operation. Please follow these guidelines and take Figure for references. ) Keep the path of switching current short and minimize the loop area formed by Input cap, high-side MOSFET and schottky diode. ) Keep the connection of schottky diode between pin and input power ground as short and wide as possible. ) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. ) Route away from sensitive analog areas such as. ) Connect,, and especially respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. For single layer, do not solder exposed pad of the IC. MP9 Rev

7 R R S C R L P C D C Figure PCB Layout External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator, the applicable conditions of external diode are: =V or.v; and VOUT Duty cycle is high: D= >% V In these cases, an external diode is recommended from the output of the voltage regulator to pin, as shown in Fig. MP9 External Diode 8 C L COUT V or.v Figure Add Optional External Bootstrap Diode to Enhance Efficiency The recommended external diode is 8, and the cap is 0.~µF. MP9 Rev

8 PACKAGE FORMATION TSOT BSC.0 See Note 7 EXAMPLE TOP MARK P AAAA TOP VIEW RECOMMDED LAND PATTERN MAX BSC SEATG PLANE SEE DETAIL "A" FRONT VIEW SIDE VIEW NOTE: GAUGE PLANE 0. BSC 0 o -8 o DETAIL 揂 ) ALL DIMSIONS ARE MILLIMETERS. ) PACKAGE LGTH DOES NOT CLUDE MOLD FLASH, PROTRUSION OR GATE BURR. ) PACKAGE WIDTH DOES NOT CLUDE TERLEAD FLASH OR PROTRUSION. ) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMG) SHALL BE 0.0 MILLIMETERS MAX. ) DRAWG CONFORMS TO JEDEC MO-9, VARIATION AB. ) DRAWG IS NOT TO SCALE. 7) P IS LOWER LEFT P WH READG TOP MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK) MP9 Rev

9 SOT BSC See Note 7 EXAMPLE TOP MARK P AAAA TOP VIEW RECOMMDED LAND PATTERN MAX BSC SEATG PLANE SEE DETAIL "A" FRONT VIEW SIDE VIEW NOTE: GAUGE PLANE 0. BSC 0 o -8 o DETAIL 揂 ) ALL DIMSIONS ARE MILLIMETERS. ) PACKAGE LGTH DOES NOT CLUDE MOLD FLASH, PROTRUSION OR GATE BURR. ) PACKAGE WIDTH DOES NOT CLUDE TERLEAD FLASH OR PROTRUSION. ) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMG) SHALL BE 0.0 MILLIMETERS MAX. ) DRAWG CONFORMS TO JEDEC MO-9, VARIATION AB. ) DRAWG IS NOT TO SCALE. 7) P IS LOWER LEFT P WH READG TOP MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK) NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP9 Rev