Features. Applications VDDQ VCC HSD EN LSD VREF COMP SUD50N02-06P GND. MIC5163 as a DDR3 Memory Termination Device for 3.

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1 Dual Regulator Controller for DDR3 GDDR3/4/5 Memory Termination General Description The is a dual regulator controller designed specifically for low voltage memory termination applications such as DDR3 and GDDR3/4/5. The offers a simple, low cost JEDEC compliant solution for terminating high-speed, low-voltage digital buses. The controls two external N-Channel MOSFETs to form two separate regulators. It operates by switching between either the high-side MOSFET or the low-side MOSFET, depending on whether the current is being sourced to the load or being sinked by the regulator. Designed to provide a universal solution for memory termination regardless of input voltage, output voltage, or load current; the desired output voltage can be externally programmed by forcing the reference voltage. The operates from an input voltage as low as.75v up to 6V, with a second bias supply input required for operation. The is available in a tiny MSOP- package with an operating junction temperature range of 4 C to +5 C. Data sheets and support documentation can be found on Micrel s web site at: Features.75V to 6V input supply voltage Memory termination for: DDR3, GDDR3/4/5 Tracking programmable output Logic controlled enable input Wide bandwidth Minimal external components required Tiny MSOP- package 4 C < T J < +5 C Applications Desktop Computers Servers Notebook computers Workstations Typical Application V DDQ =.V U V CC = 5V VDDQ VCC HSD SUD5N-6P V TT =.6V µf µf µf V pf LSD VREF COMP FB SUD5N-6P pf µf µf as a DDR3 Memory Termination Device for 3.5A application Micrel Inc. 8 Fortune Drive San Jose, CA 953 USA tel + (48) fax + (48) April 9 M A

2 Ordering Information Part Number Temperature Range Package Lead Finish YMM 4 to +5 C -Pin MSOP Pb-Free Note: MSOP is a Green RoHs compliant package. Lead finish is NiPdAu. Mold compound is halogen free. Pin Configuration VCC NC 9 HD VDDQ 3 8 LD VREF 4 7 COMP 5 6 FB -Pin MSOP (MM) Pin Description Pin Number Pin Name Pin Function VCC Bias Supply (Input): Apply a voltage between +3V and +6V to this input for internal bias to the controller Enable (Input): CMOS compatible input. Logic high = enable, logic low = shutdown 3 VDDQ Input Supply Voltage 4 VREF Reference output equal to half of VDDQ 5 Ground 6 FB Feedback input to the internal error amplifier 7 COMP Compensation (Output): Connect a capacitor to feedback pin for compensation of the internal control loop 8 LD Low-side drive: Connects to the Gate of the external low-side MOSFET 9 HD High-side drive: Connects to the Gate of the external high-side MOSFET NC Not internally connected April 9 M A

3 Absolute Maximum Ratings () Supply Voltage (V CC )....3V to +7V Supply Voltage (V DDQ )....3V to +7V Enable Input Voltage (V )....3V to +7V Lead Temperature (soldering, sec.) C Storage Temperature (T S ) C to +5 C EDS Rating (3)...+kV Operating Ratings () Supply Voltage (V CC )... +3V to +6V Supply Voltage (V DDQ ) V to +6V Enable Input Voltage (V )... V to Junction Temperature (T J )... 4 C to +5 C Junction Thermal Resistance MSOP (θ JA ) C/W MSOP (θ JC ) C/W Electrical Characteristics (4) V DDQ =.35V; T A = 5 C, bold values indicate 4 C T J +5 C, unless noted. Parameter Condition Min Typ Max Units V REF Voltage Accuracy -%.5V DDQ +% V V TT Voltage Accuracy (Note 5) Sourcing; ma to 3A -5 - Supply Current (I DDQ ) Sinking; -ma to -3A -5 - V =.V (controller ON) No Load Supply Current (I CC ) No Load.5 5 I CC Shutdown Current (Note 6) V =.V (controller OFF) 45 9 na Start-up Time (Note 7) V CC = 5V external bias; V = V CC Enable Input Enable Input Threshold Regulator Enable. V Regulator Shutdown.3 V Enable Hysteresis 35 mv Enable Pin Input Current Driver High Side Gate Drive Voltage Low Side Gate Drive Voltage V IL <.V (controller shutdown). µa V IH >.V (controller enable) 5.75 µa High Side MOSFET Fully ON V High Side MOSFET Fully OFF.3. V Low Side MOSFET Fully ON V Low Side MOSFET Fully OFF.3. Notes:. Exceeding the absolute maximum rating may damage the device.. The device is not guaranteed to function outside its operating rating. 3. Devices are ESD sensitive. Handling precautions recommended. Human body model,.5kω in series with pf. 4. Specification for packaged product only. 5. The V TT voltage accuracy is measured as a delta voltage from the reference output (V TT - V REF ). 6. Shutdown current is measured only on the V CC pin. The V DDQ pin will always draw a minimum amount of current when voltage is applied. mv mv mv mv µa µa ma ma µs µs April 9 3 M A

4 7. Start-up time is defined as the amount of time from = V CC to HSD = 9% of V CC Test Circuit V DDQ =.75-.5V VDDQ HD SUD5N-6P V TT =.5*V DDQ V CC = 5V µf µf 47pF VCC COMP FB LD VREF pf C OUT = 3*56µF k Figure. Test Circuit April 9 4 M A

5 Typical Characteristics IDDQ CURRT (µa) ICC CURRT (µa) HD PROP DELAY (µs) TH ON (V) V IN =.75V IDDQ Current vs. Temperature =.35V =6V =.5V TEMPERATURE ( C) ICC Current vs. Input Voltage -4 C Room Temp 5 C INPUT VOLTAGE (V) =6V -4 - HD Prop Delay vs. Temperature =.75V =.35V =.5V TEMPERATURE ( C) TH ON vs. Input Voltage -4 C Room Temp 5 C INPUT VOLTAGE (V) VTT-VREF (V) IDDQ CURRT (µa) ICC SHUTDOWN CURRT (µa) HD PROP DELAY (µs) IDDQ Current vs. Input Voltage 8-4 C 6 4 Room Temp C INPUT VOLTAGE (V) =.75V. =.35V ICC Shutdown Current vs. Temperature =6V =.5V TEMPERATURE ( C) HD Prop Delay vs. Input Voltage C Room Temp C INPUT VOLTAGE (V) VTT-VREF vs. Temperature 3A.A -3A -.A TEMPERATURE ( C) VTT-VREF (V) ICC CURRT (µa) ICC SHUTDOWN CURRT (µa) ICC Current vs. Temperature =6V =.5V =.35V =.75V TEMPERATURE ( C) ICC Shutdown Current vs. Input Voltage 5 C -4 C.5 Room Temp INPUT VOLTAGE (V) TH ON (V) TH ON vs. Temperature =6V =.5V =.75V =.35V TEMPERATURE ( C) VTT-VREF vs. =6V =.35V =.75V =.5V LOAD (A) April 9 5 M A

6 Functional Characteristics April 9 6 M A

7 Functional Characteristics (continued) April 9 7 M A

8 Functional Diagram VDDQ VCC R A HD VREF R -A LD Shutdown FB COMP Figure. Block Diagram April 9 8 M A

9 Functional Description The is a high performance linear controller, utilizing scalable N-Channel MOSFETs to provide JEDEC compliant bus termination. Termination is achieved by dividing down the V DDQ voltage by a half, providing the reference (V REF ) voltage. The controls two external N-Channel MOSFETs to form two separate regulators. It operates by switching between either the high-side MOSFET or the low-side MOSFET, depending on whether the current is being sourced to the load or being sinked by the regulator. V DDQ The V DDQ pin on the provides the source current through the high side N-Channel and the reference voltage to the device. The can operate at V DDQ input voltages as low as.75v. A bypass capacitance will increase performance by improving the source impedance at higher frequencies. V TT V TT is the actual termination point. V TT is regulated to V REF. Due to high speed signaling, the load current seen by V TT is constantly changing. To maintain adequate large signal transient response, Oscons and ceramics are recommended on V TT. The Oscon capacitors provide bulk charge storage while the smaller ceramic capacitors provide current during the fast edges of the bus transition. V REF Two resistors dividing down the V DDQ voltage provide V REF. The resistors are valued at around 7kΩ. A minimum capacitor value of pf from V REF to ground is mandatory. V CC V CC supplies the internal circuitry of the and provides the drive voltage to enhance the external N- Channel MOSFETs. A small μf capacitor is recommended for bypassing the V CC pin. Feedback and Compensation The feedback provides the path for the error amplifier to regulate the V TT. An external resistor must be placed between the feedback and V TT. Feedback resistor values should not exceed kω and compensation capacitors should not be less than 4pF. Enable The features an active high enable input. In the off mode state, leakage currents are reduced to microamperes. The enable input has thresholds compatible with TTL/CMOS for simple logic interfacing. The enable pin can be tied directly to V DDQ or V CC for functionality. April 9 9 M A

10 Application Information Synchronous Dynamic Random Access Memory (SDRAM) has continually evolved over the years to keep up with ever-increasing computing needs. The latest addition to SDRAM technology is DDR3 SDRAM. DDR3 SDRAM is the third generation of the DDR SDRAM family and offers improved power savings, higher data bandwidth and enhanced signal quality with multiple ondie termination (ODT) selection. In DDR3 SDRAM the values of the ODT are based on the value of an external resistor. In addition to using this external resistor for setting the ODT value, it is also used for calibrating the ODT value so that it maintains its resistance value to within a % tolerance. To improve signal integrity and support higher frequency operations, the JEDEC committee defined a fly-by termination scheme used with the clocks, the command bus and address bus signals. The fly-by topology reduces simultaneous switching noise (SSN) by deliberately causing flight-time skew between the data and strobes at every DRAM as the clock, address and command signals traverse the DIMM. The DDR3 SDRAM uses a programmable impedance output buffer. Currently, there are two drive strength settings, 34Ω and 4Ω. The 4Ω drive strength setting is currently a reserved specification defined by JEDEC, but available on the DDR3 SDRAM. Driver Receiver FPGA VREF=.75V 3 Trace Length VREF=.75V DDR3 DIMM DDR3 Component RS Driver Receiver on DDR3, the is also capable of providing bus terminations for DDR, DDR and GDDR3/4/5. V DDQ The V DDQ pin on the provides the source current through the high side N-Channel and the reference voltage to the device. The can operate at V DDQ voltages as low as.75v. Due to the possibility of large transient currents being sourced from this line, significant bypass capacitance will increase performance by improving the source impedance at higher frequencies. Since the reference is simply V DDQ /, perturbations on the V DDQ will also appear at half the amplitude on the reference. For this reason, low ESR capacitors such as ceramics or Oscons are recommended on V DDQ. V TT V TT is the actual termination point. V TT is regulated to V REF. Due to high speed signaling, the load current seen by V TT is constantly changing. To maintain adequate large signal transient response, Oscons and ceramics are recommended on V TT. The proper combination and placement of the Oscon and ceramic capacitors is important to reduce both ESR and ESL such that highcurrent high-speed transients do not exceed the dynamic voltage tolerance requirement of V TT. The Oscon capacitors provide bulk charge storage while the smaller ceramic capacitors provide current during the fast edges of the bus transition. Using several smaller ceramic capacitors distributed near the termination resistors is typically important to reduce the effects of PCB trace inductance. Driver Receiver FPGA VREF=.75V 3 Trace Length VREF=.75V DDR3 DIMM DDR3 Component Figure 3. Dynamic OCT between Stratix III/IV FPGA Devices RS Driver Receiver The is a high performance linear controller that utilizes scalable N-Channel MOSFETs to provide JEDEC compliant bus termination. Termination is achieved by dividing down the V DDQ voltage by half to provide the reference (V REF ) voltage. An internal error amplifier compares the termination voltage (V TT ) and V REF, controlling two external N-Channel MOSFETs to sink and/or source current to maintain a termination voltage (V TT ) equal to V REF. The N-Channels receive their enhancement voltage from a separate V CC pin on the device. Although the general discussion is focused V REF Two resistors dividing down the V DDQ voltage provide V REF (Figure 5). The resistors are valued at around 7kΩ. A minimum capacitor value of pf from V REF to ground is required to remove high frequency signals reflected from the source. Large capacitance values (>5pF) should be avoided. Values greater than 5pF slow down V REF and detract from the reference voltage s ability to track V DDQ during high speed load transients. V DDQ =.V µf µf V CC = 5V µf V pf U VDDQ VCC HSD LSD VREF COMP pf FB SUD5N-6P µf V TT =.6V µf Figure 4. as a DDR3 Memory Termination Device for 7A Application April 9 M A

11 VREF pf VDDQ Figure 5. V DDQ Divided Down to Provide V REF V REF can also be manipulated for different applications. A separate voltage source can be used to externally set the reference point, bypassing the divider network. Also, external resistors can be added from V REF -to-ground or V REF -to-v DDQ to shift the reference point up or down. V CC V CC supplies the internal circuitry of the and provides the drive voltage to enhance the external N- Channel MOSFETs. A small μf capacitor is recommended for bypassing the V CC pin. The minimum V CC voltage should be a gate-source voltage above V TT without exceeding 6V. For example, on an DDR3 compliant terminator, V DDQ equals.5v and V TT equals.75v. If the N-Channel MOSFET selected requires a gate source voltage of.5v, V CC should be a minimum of 3.5V Feedback and Compensation The feedback provides the path for the error amplifier to regulate V TT. An external resistor must be placed between the feedback and V TT. This allows the error amplifier to be correctly externally compensated. For most applications, a 5Ω resistor is recommended. The COMP pin on the is the output of the internal error amplifier. By placing a capacitor and resistor between the COMP pin and the feedback pin, this coupled with the feedback resistor, places an external pole and zero on the error amplifier. With a 5Ω feedback resistor, a minimum pf capacitor is recommended for a 3.5A peak termination circuit. An increase in the load will require additional N-Channel MOSFETs and/or increase in output capacitance may require feedback and/or compensation capacitor values to be changed to maintain stability. Feedback resistor values should not exceed kω and compensation capacitors should not be less than 4pF. Enable The features an active high enable input. In the off mode state, leakage currents are reduced to microamperes. The enable input has thresholds compatible with TTL/CMOS for simple logic interfacing. The enable pin can be tied directly to V DDQ or V CC for functionality. Do not float the enable pin. Floating this pin causes the enable to be in an indeterminate state. Input Capacitance Although the does not require an input capacitor for stability, using one greatly improves device performance. Due to the high-speed nature of the, low ESR capacitors such as Oscon and ceramics are recommended for bypassing the input. The recommended value of capacitance will depend greatly on the proximity to the bulk capacitance. Although a μf ceramic capacitor will suffice for most applications, input capacitance may need to be increased in cases where the termination circuit is greater than -inch away from the bulk capacitance. Output Capacitance Large, low ESR capacitors are recommended for the output (V TT ) of the. Although low ESR capacitors are not required for stability, they are recommended to reduce the effects of high-speed current transients on V TT. The change in voltage during the transient condition will be the effect of the peak current multiplied by the output capacitor s ESR. For that reason, Oscon type capacitors and ceramic are excellent choices for this application. Oscon capacitors have extremely low ESR and a large capacitance-to-size ratio. Ceramic capacitors are also well suited to termination due to their low ESR. These capacitors should have a dielectric rating of X5R or X7R. Y5V and Z5U type capacitors are not recommended, due to their poor performance at high frequencies and over temperature. The minimum recommended capacitance for a 3.5A peak circuit is μf. Output capacitance can be increased to achieve greater transient performance. MOSFET Selection The utilizes external N-Channel MOSFETs to sink and source current. MOSFET selection will settle to two main categories: size and gate threshold (V GS ). MOSFET Power Requirements One of the most important factors is to determine the amount of power the MOSFET is going to be required to dissipate. Power dissipation in a DDR3 circuit will be identical for both the high side and low side MOSFETs. Since the supply voltage is divided by half to supply V TT, both MOSFETs have the same voltage dropped across them. They are also required to be able to sink and source the same amount of current (for either all s or all s). This equates to each side being able to dissipate the same amount of power. Power dissipation calculation for the high-side MOSFET is as follows: April 9 M A

12 P D = (V DDQ V TT ) I_SOURCE Where I_source is the average source current. Power dissipation for the low-side MOSFET is as follows: P D = V TT I_SINK Where I_sink is the average sink current. In a typical 3.5A peak DDR3 circuit, power considerations for MOSFET selection would occur as follows. P D = (V DDQ V TT ) I_SOURCE P D = (.5V.75V).75A P D =.35 W This typical DDR3 application would require both highside and low-side N-Channel MOSFETs to be able to handle.35 Watts each. In applications where there is excessive power dissipation, multiple N-Channel MOSFETs may be placed in parallel. These MOSFETs will share current, distributing power dissipation across each device. The maximum MOSFET die (junction) temperature limits maximum power dissipation. The ability of the device to dissipate heat away from the junction is specified by the junction-to-ambient (θ JA ) thermal resistance. This is the sum of junction-to-case (θ JC ) thermal resistance, caseto-sink (θ CS ) thermal resistance and sink-to-ambient (θ SA ) thermal resistance; θ JA = θ JC + θ CS + θ SA In our example of a 3.5A peak DDR3 termination circuit, we have selected a D-pack N-Channel MOSFET that has a maximum junction temperature of 5 C. The device has a junction-to-case thermal resistance of.5 C/W. Our application has a maximum ambient temperature of 6 C. The required junction-to-ambient thermal resistance can be calculated as follows: TJ TA θ JA = PD Where T J is the maximum junction temperature, T A is the maximum ambient temperature and P D is the power dissipation. In our example: θ θ JA JA TJ T = P D A 5 C 6 C =.35W θ JA = C W This shows that our total thermal resistance must be better than C/W. Since the total thermal resistance is a combination of all the individual thermal resistances, the amount of heat sink required can be calculated as follows: θ SA = θ JA (θ JC + θ CS ) In our example: θ SA = θ JA (θ JC + θ CS ) θ θ C C C = W W W SA 5 SA = C W In most cases, case-to-sink thermal resistance can be assumed to be about.5 C/W. The DDR3 termination circuit for our example, using D- pack N-Channel MOSFETs (one high side and one on the low side) will require at least a 43 C/W heat sink per MOSFET. This may be accomplished with an external heat sink or even just the copper area that the MOSFET is soldered to. In some cases, airflow may also be required to reduce thermal resistance. MOSFET Gate Threshold N-Channel MOSFETs require an enhancement voltage greater than its source voltage. Typical N-Channel MOSFETs have a gate-source threshold (V GS ) of.8v and higher. Since the source of the high side N-Channel is connected to V TT, the V CC pin requires a voltage equal to or greater than the V GS voltage. For example, our DDR3 termination circuit has a V TT voltage of.75v. For an N-Channel that has a V GS rating of.5v, the V CC voltage can be as low as 3.5V. With an N-Channel that has a 4.5V V GS, the minimum V CC required is 5.5V. Although these N-Channels are driven below their full enhancement threshold, it is recommended that the V CC voltage has enough margin to be able to fully enhance the MOSFETs for large signal transient response. In addition, low gate thresholds MOSFETs are recommended to reduce the V CC requirements. April 9 M A

13 Micrel, Inc. Design Example J J8 VIN N7E Q J ShDn R5 K J3 DLY J4 RC C nf, 5V J5 POR 3 C3 nf, 5V TP5 3 4 C - nf, 5V R4 47.5K VIN J CIN SW uf, L µh, 7Ainductor C - µf, C - µf, TP PVin PVin PVin PVin 3 SVin 4 U Dly Comp 5 95_3L_5x5YML RC FB 6 9 POR CF 7 8 C7 - pf, 5V PVin SGnd 8 PVin 3 3 SW 3 SW 9 SW 8 SW 7 6 SW SW SW SW C5 TP µf, 4 C6-39pF, 5V R3 - K 3 C4 R PVin C8-39pF, 5V C4 µf, C9 47µF VDDQ TP J3 VIN TP3 TP4 C 47µF + C3 7µF.5V P C µf J4 V C3 C µf µf U VCC HSD 4 VREF C3 pf VDDQ 3 R4 LSD TP -YMM 7 Comp 6 FB SUD5N-6 3 Q 9 Q 8 SUD5N-6 R3 C7 C4 - pf R R K + C6 µf TP3 C3 µf TP4 J VTT J6 C3 - µf, P As a DDR3 Memory Termination Device for 3.5A Application Bill of Materials Item Part Number Manufacturer Description Qty. GRMBR6J6ME39L Murata () 4 C, C, C3, C4 CX5RJ6K TDK () µf,, X5R, 85 or 856D6MATA AVX (3) or GRM88R6J6ME47D Murata () C5 C68X5RJ6K TDK () µf,, X5R, 63 or 636D6MATA AVX (3) or C6 VJ63Y39KXXMB Vishay Vitramon (4) 39pF, 5V, X7R, 63 C68CGH39J TDK () or C7 VJ63YKXAAT Vishay Vitramon (4) pf, 5V, 63 ceramic cap C8 VJ63Y39KXAAT Vishay Vitramon (4) 39pF, 5V, 63 ceramic cap 47 µf,, 6 GRM3CR6J476ME9L Murata () C9, C C36X5RJ476M TDK () or 66D476MATA AVX (3) or C, C3 VJ63YKXXMB Vishay Vitramon (4) nf, 5V, 63 ceramic cap C VJ63Y3KXXMB Vishay Vitramon (4) nf, 5V, 63 ceramic cap C 63ZD5KATA AVX (3) µf, V 63 ceramic cap GRM88R6A5K Murata () or C3 C4 VJ63AKXXAT Vishay (4) pf, 5V, 63 ceramic cap 633AJATA AVX (3) or VJ63AKXXAT Vishay (4) pf, 5V, 63 ceramic cap 633CJATA AVX (3) or C6 NOSD7M6R8 AVX (3) µf,, 7374 Tent C7 N.U. 63 ceramic cap April 9 3 M A

14 Item Part Number Manufacturer Description Qty. C3, C3, C 86D7MAT AVX (3) µf,, 8 ceramic cap 3 C3 SEPC7M Sanyo (5) 7µF,.5V Oscon Cap CIN 597D8X6R3RT Vishay (4) µf,, R-case L CEP5HNP-R-MC Sumida (6) µh, 7A inductor Q N7E(SOT-3) Vishay (4) Signal MOSFET-SOT-36 Q, Q SUD5N-6P Vishay (4) Low VGS(th) N-Channel -V (D-S) R CRCW63FRT Vishay Dale (4) 5Ω (63 size), % R CRCW63698FRT Vishay Dale (4) 698Ω (63 size), % R3 CRCW63FRT Vishay Dale (4) K, (63 size), % R4 CRCW63475FRT Vishay Dale (4) 47.5K, (63 size), % R5 CRCW633FRT Vishay Dale (4) K (63 size), % R CRCW855RFKTA Vishay Dale (4) 5Ω (85 size), % R, R4 CRCW63KFKTA Vishay Dale (4) K (63 size), % R3 NU 63 U MIC95YML Micrel (7) Buck Regulator U YMM Micrel (7) Dual Regulator Controller for DDR3 Notes:. Murata: TDK: 3. AVX: 4. Vishay: 5. Sanyo: 6. Sumida: 7. Micrel, Inc.: April 9 4 M A

15 Package Information -Pin MSOP (MM) MICREL, INC. 8 FORTUNE DRIVE SAN JOSE, CA 953 USA TEL + (48) FAX + (48) 474- WEB The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. 9 Micrel, Incorporated. April 9 5 M A