id6309 Li+ Charger Protection IC with Integrated PMOS General Description Features

Transcription

1 Li+ Charger Protection IC with Integrated PMOS General Description Features The id6309 provides complete Li+ charger protection Input Over-Voltage Protection against input over-voltage, input over-current, and Input Over-Current Protection battery over-voltage. When any of the monitored Battery Over-Voltage Protection parameters are over the threshold, the IC removes the High Immunity of False Triggering power from the charging system by turning off an High Accuracy Protection Threshold internal switch. All protections also have deglitch time Thermal Shutdown Protection against false triggering due to current transients or A Built-In P-MOSFET voltage spike. Available in a TDFN2x2-8 Package The id6309 integrates a power PMOS with body Lead Free and Green Devices Available diode leakage protection to replace the external (RoHS Compliant) PMOS and Schottky diode for the charger function of cell phone s PMIC. When CHRIN drops below V BAT +20mV, the internal detector will activate the leakage protection mechanism to prevent leakage current from battery back to CHRIN. The id6309 provides complete Li+ charger protections and saves external PMOS and Schottky diode for the charger function of cell phone s PMIC. The above feature and small package make id6309 an ideal part for cell phone application. Applications Mobile Phones Ordering Information Apr Rev 0.7

2 Typical Application Circuit Absolute Maximum Ratings Recommended Operating Conditions ACIN Input Voltage V ACIN 30V ACIN Input Voltage V ACIN 4.5V to 5.5V CHRIN Voltage V CHRIN 7V Output Current I OUT 0~700mA GATDRV Voltage V GATDRV 7V Junction Temperature Range -40 C to 125 C VBAT Voltage V BAT 7V Ambient Operating Temperature -40 C to 85 C OUT Voltage V OUT 7V OUT Output Current I OUT 1.5A Power Dissipation, P T A =25 C TDFN W Thermal Resistance, θja TDFN-8 80 C/W Lead Temperature 260 C Storage Temperature -65 C to 150 C ESD Susceptibility HBM (Human Body Mode) 2kV MM (Machine Mode) 200V Compliance to IEC (Level 4) ± 8kV (Contact Discharge) ± 15kV (Air Discharge) Pin Configurations (Top View) TDFN-8L Apr Rev 0.7

3 Pin Function Pin No. Pin Name I/O Pin Function 1 ACIN I 2 ACIN I 3 GND Ground Terminal. id6309 Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1μF (minimum) ceramic capacitor. 4 VBAT I Battery Voltage Sense Input. Connect this pin to pack positive terminal through a resistor. 5 GATDRV I Internal P-MOSFET Gate Input. 6 CHRIN O 7 OUT O 8 OUT O CHRIN Output Pin. This pin provides supply voltage to the PMIC input. Bypass to GND with a 1μF (minimum) ceramic capacitor. Output Pins. These pins provide supply source current in series with a resistor to battery. EP Exposed Thermal Pad. Must be electrically connected to the GND pin. Function Block Diagram Apr Rev 0.7

4 Electrical Characteristics (Unless otherwise specified, these specifications apply over V ACIN =5V, V BAT =3.8V and T A = -40 ~ 85 C. Typical values are at T A =25 C.) Parameter Symbol Test Condition Min Typ Max Units ACIN INPUT CURRENT AND POWER-ON-RESET (POR) ACIN Supply Current I ACIN I OUT =0A, I CHRIN =0A μa ACIN POR Threshold V ACIN V ACIN rising V ACIN POR Hysteresis mv ACIN Power-On Blanking Time T B(ACIN) 8 ms INTERNAL SWITCH ON RESISTANCE ACIN to OUT On Resistance I OUT =0.7A 0.5 Ω CHRIN Discharge On Resistance 500 Ω INPUT OVER-VOLTAGE PROTECTION (OVP) Input OVP Threshold V OVP V ACIN rising id6309a id6309b Input OVP Hysteresis 300 mv Input OVP Propagation Delay 1 μs Input OVP Recovery Time T ON(OVP) 8 ms OVER CURRENT PROTECTION (OCP) OCP Threshold I OCP 1.3 A OCP Blanking Time T B(OCP) 176 μs OCP Recovery Time T ON(OCP) 64 ms BATTERY OVER VOLTAGE PROTECTION Battery OVP Threshold V BOVP V BAT rising V Battery OVP Hysteresis 270 mv VBAT Pin Leakage Current I VBAT V BAT = 4.4V 20 na Battery OVP Blanking Time T B(BOVP) 176 μs INTERNAL P-MOSFET (CHRIN, OUT AND GATDRV PINS) V CHRIN -V BAT Lockout Threshold V CHRIN from low to high, P-MOSFET is controlled by GATDRV 150 V CHRIN from high to low, P-MOSFET is off 20 mv OUT Input Current V CHRIN =0V, V OUT =4.2V, GATDRV=GND 1 μa GATDRV Leakage Current V ACIN =V CHRIN = V OUT =5V, V GATDRV =0V 1 μa OUT Leakage Current V ACIN =V CHRIN = V GATDRV =5V, V OUT =0V 1 μa P-MOSFET Input Capacitance 200 pf GATDRV Input Resistance 15 Ω OVER-TEMPERATURE PROTECTION (OTP) Over-Temperature Threshold T OTP T J rising 160 C Over-Temperature Hysteresis 40 C V Apr Rev 0.7

5 Typical Operation Characteristics (V ACIN = 5.0V, V BAT = 3.8V, C ACIN = 1μF (X5R ceramics), C CHRIN = 1μF (X5R ceramics), R BAT = 200kΩ (SMD Type), R OUT = 0.2Ω (SMD Type), T A = 25.) ACIN OVP vs. Temperature OCP vs. Temperature ACIN OVP Threshold (V) Increasing Decreasing OCP Threshold (A) Junction Temperature ( ) Junction Temperature ( ) Battery OVP vs. Temperature ACIN to OUT Resistance vs. Temperature Battery OVP Threshold (V) Increasing Decreasing ACIN to OUT Resistance RDS(ON) (Ω) I OUT = 500mA Junction Temperature ( ) Junction Temperature ( ) ACIN Supply Current vs. Temperature ACIN POR vs. Temperature ACIN Supply Current (μa) ACIN POR Threshold (V) Increasing Dncreasing Junction Temperature ( ) Junction Temperature ( ) Apr Rev 0.7

6 Operating Waveforms (V ACIN = 5.0V, V BAT = 3.8V, C ACIN = 1μF (X5R ceramics), C CHRIN = 1μF (X5R ceramics), R BAT = 200kΩ (SMD Type), R OUT = 0.2Ω (SMD Type), T A = 25.) Normal Power On OVP at Power On V ACIN (DC) (5.00V/Div) V ACIN (DC) (10.0V/Div) V OUT (DC) I OUT (DC) (200mA/Div) V GATDRV = V CHRIN V OUT (DC) V ACIN = 0 to 12V, V GATDRV = V CHRIN Time (2.00ms/Div) Time (2.00ms/Div) ACIN Over-Voltage Protection Recovery from Input OVP V ACIN (DC) V ACIN (DC) (5.00V/Div) (5.00V/Div) V ACIN =5V to 12V V ACIN =12V to 5V Time (20.0μs/Div) Time (10.0ms/Div) Battery Over-Voltage Protection Battery Over-Voltage Protection V BAT (DC) (1.00V/Div) V BAT (DC) (1.00V/Div) V BAT = 3.6V to 4.4V to 3.6V V BAT = 3.6V to 4.4V Time (100ms/Div) Time (400μs/Div) Apr Rev 0.7

7 Over-Current Protection Over-Current Protection V ACIN (DC) (5.00V/Div) V OUT (DC) (5.00V/Div) (5.00V/Div) V OUT (DC) I OUT (DC) (1.00A/Div) V BAT = V GATDRV = 0V, R OUT = 2.5Ω I OUT (DC) (1.00A/Div) V BAT = V GATDRV = 0V, R OUT = 10Ω to 2.4Ω Time (200ms/Div) Time (100μs/Div) Apr Rev 0.7

8 Function Description ACIN Power-On-Reset (POR) The id6309 has a built-in power-on-reset circuit to keep the output shutting off until internal circuitry is operating properly. The POR circuit has hysteresis and a deglitch feature so that it will typically ignore undershoot transients on the input. When input voltage exceeds the POR threshold and after 8ms blanking time, the output voltage starts a soft-start to reduce the inrush current. ACIN Over-Voltage Protection (OVP) The input voltage is monitored by the internal OVP circuit. When the input voltage rises above the input OVP threshold, the internal FET will be turned off within 1ms to protect connected system on OUT pin. When the input voltage returns below the input OVP threshold minus the hysteresis, the FET is turned on again after 8ms recovery time. The input OVP circuit has a 300mV hysteresis and a recovery time of T ON(OVP) to provide noise immunity against transient conditions. Over-Current Protection (OCP) The output current is monitored by the internal OCP circuit. When the output current reaches the OCP threshold, the device limits the output current at OCP threshold level. If the OCP condition continues for a blanking time of T B(OCP), the internal power FET is turned off. After the recovery time of T ON(OCP), the FET will be turned on again. The id6309 has a built-in counter. When the total count of OCP fault reaches 16, the FET is turned off permanently, requiring a V ACIN POR again to restart. Battery Over-Voltage Protection The id6309 monitors the VBAT pin voltage for battery over-voltage protection. The battery OVP threshold is internally set to 4.35V. When the VBAT pin voltage exceeds the battery OVP threshold for a blanking time of T B(BOVP), the internal power FET is turned off. When the VBAT voltage returns below the battery OVP threshold minus the hysteresis, the FET is turned on again. The id6309 has a built-in counter. When the total count of battery OVP fault reaches 16, the FET is turned off permanently, requiring a V ACIN POR again to restart. Over-Temperature Protection When the junction temperature exceeds 160 C., the internal thermal sense circuit turns off the power FET and allows the device to cool down. When the device s junction temperature cools by 40 C., the internal thermal sense circuit will enable the device, resulting in a pulsed output during continuous thermal protection. Thermal protection is designed to protect the IC in the event of over temperature conditions. For normal operation, the junction temperature cannot exceed T J =+125 C.. Internal P-MOSFET The id6309 integrates a P-channel MOSFET with the body diode reverse protection to replace the external PMOSFET and Schottky diode for cell phone s PMIC. The body diode reverse protection prevents a reverse current flowing from the battery back to CHRIN pin. During power-on, when CHRIN voltage rises above the VBAT voltage by more than 150mV, the body diode of the P- channel MOSFET is forward biased from OUT to CHRIN, and PMOSFET is controlled by the external GATDRV voltage. When the CHRIN voltage drops below V BAT +20mV, the body diode of the P-channel MOSFET is forward biased from CHRIN to OUT and P-channel MOSFET is turned off. When any of input OVP, OCP, battery OVP, is detected, the internal P-channel MOSFET is also turned off. Thermal Considerations For continuous operation, do not exceed the maximum operation junction temperature 125 C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junctions to ambient. The maximum power dissipation can be calculated by following formula: P D ( MAX ) = ( T T ) J ( MAX ) θ JA A Apr Rev 0.7

9 Where T J(MAX) is the maximum operation junction temperature 125 C, T A is the ambient temperature and the θ JA is the junction to ambient thermal resistance. For recommended operating conditions specification of id6309 where T J(MAX) is the maximum junction temperature of the die (125 C) and T A is the maximum ambient temperature. The junction to ambient thermal resistance θ JA is layout dependent. For TDFN-8L packages, the thermal resistance θ JA is 80 C/W on the standard JEDEC 51-7 four-layers thermal test board. The maximum power dissipation at T A = 25 C can be calculated by following formula: P D(MAX) = (125 C 25 C) / (80 C/W) = 1.25W for TDFN-8L packages. The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θ JA. For id6309 packages, the Figure 1 of de-rating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. Maximum Power Dissipation Power Dissipation (W) Ambient Temperature ( C) Figure 1: Maximum Power Dissipation Layout Considerations In some failure modes, a high voltage may be applied to the device. Make sure the clearance constraint of the PCB layout must satisfy the design rule for high voltage. The exposed pad of the TDFN2x2-8 performs the function of channeling heat away. It is recommended that connect the exposed pad to a large copper ground plane on the backside of the circuit board through several thermal vias to improve heat dissipation. The input and output capacitors should be placed close to the IC. The high current traces like input trace and output trace must be wide and short. ACIN trace must be + Battery The ACIN capacitors wide and short. should be close to the IC. 0.2Ω CACIN ACIN ACIN GND EP OUT OUT CHRIN OUT trace must be wide and short. CCHRIN RBAT VBAT 4 5 GATDRV The CHRIN capacitors should be close to the IC. Exposed thermal pad must be electrically connected to GND pin. It's recommended that connect the exposed pad to a large copper ground plane on the backside of the circuit board through several thermal vias to improve heat dissipation. Apr Rev 0.7

10 Figure 1. OVP Timing Diagram Figure 2. OCP Timing Diagram Apr Rev 0.7

11 Figure 3. Battery OVP Timing Diagram Apr Rev 0.7

12 Packaging TDFN-8L(2X2) SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCH MIN NOM MAX MIN NOM MAX A A A REF REF --- b D D BSC BSC --- E E BSC BSC --- e BSC BSC --- L Apr Rev 0.7

13 Footprint TDFN-8L(2X2) Footprint Dimension (mm) Package Number of PIN Tolerance P A B C D Sx Sy M TDFN-8L 2x ±0.030 Apr Rev 0.7