AVS / DVS and Margining Circuits for Vishay Power ICs SiC40X Series SMPS Regulators

Transcription

1 VISHAY SILICONIX ICs by Ronald Vinsant ABSTRACT There are many applications that require that a voltage rail within a system be capable of being adjusted by a digital or analog control signal. These circuits may only need to do a margining function in a test mode, vary the output voltage from the regulator by only a small amount to optimize specific performance parameters, or perhaps the voltage must be widely scalable to allow for the use of different sensors in an industrial application. This application note will show a number of different solutions to these design challenges by utilizing the Vishay SiC0X series of synchronous buck regulators. A key aspect of this design is the COT architecture of this family of products, which allows adaptability of the control system to the different operating points of the regulator without any iterative compensation design. A spreadsheet tool and simulation schematic will be introduced that enable the user to quickly derive a solution with knowledge of only a few required parameters. Confirmation of the validity of these two tools will be shown by use of the SiC0DB, SiC0DB, and SiC0DB reference board, with the addition of only two resistors, a capacitor, and a user-supplied voltage source. This source could be an existing rail with an analog switch, a GPIO or PWM on an FPGA or processor, or a DAC. SiC0X DESCRIPTION The SiC0A/B, SiC0A/B, and SiC0A/B are advanced stand-alone synchronous buck regulators, featuring integrated power MOSFETs, a bootstrap switch, and a programmable LDO in space-saving PowerPAK MLP55-L pin packages. The SiC0A/B, SiC0A/B, and SiC0A/B are capable of operating with all ceramic solutions and switching frequencies up to MHz. The programmable frequency, synchronous operation, and selectable power-save feature allow operation at high efficiency across the full range of load current. See THE REFERENCE BOARD This reference board allows the end user to evaluate the SiC0A/B, SiC0A/B, and SiC0A/B for their features and all functionalities. It can also be a reference design for a user's application. See CALCULATION TOOLS The designer can start their design by using the reference board mentioned above. If the reference board does not meet the goals of the designer s application, then a design tool is available online at Once a regulator design has been chosen, there is an Excel tool, an AVS calculator, located at This tool allows the designer to add to the existing regulator circuit adjustability of the output voltage through an external signal from a DAC or other voltage source. In addition, this spreadsheet has some programmer s tools to make the writing of software to drive the DAC easier. Revision: 8-Jul-6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

2 8 HOW IT WORKS Theory To describe the theory of operation, a design from Vishay s AVS calculator tool has been chosen that extends to the boundaries of operation of the SiC0X family of regulators (Fig. ). The yellow cells indicate the only parameters required from a user to generate a design. Details of the calculator will be covered later in this application note. Step : V REF Calculate and (R above) I RBOT (A) SiCXX max. SiCXX min. Determine DAC gain (DAC V / output V) (ratio) Determine zero current point for (V DAC = V REF ) Calculate Calculate Step : DAC max. Input DAC parameters DAC bits (number) DAC LSB DAC LSB adjust in SiCXX Total count (theoretical number of voltage steps from DAC) (number) Fig. - Calculation Results for Theory of Operation Fig. shows a schematic of the reference board. The area circled in black is where a signal will be injected to alter the output voltage. R5, R5, and C8 have been added to the original schematic. In all the simulations below, the op-amps that are used are very close to ideal, thus the calculations are very exacting B V IN B V IN_ P V DD P8 V IN P V IN_ C 50 μf C6.7 μf + V DD P EN_PSV C0 68 μf + C7 open C0 68 μf + C C8 0.uF + R 00K R 00K C 0. μf R 57.6K R 0K C7 0 nf R5 K6 V IN C 0.0 μf R6 V DD SOFT 00K 0 7 FBL5 C nf 6 V IN V IN FBL 567 P P U SiC0// Fig. - Reference Board Schematic (Modified) The circled area in Fig. provides a simplified view of DC operation. P6 ENL V IN V IN V IN V DD ENL P ENL 8 EN/PSV P NC 0 P P NC P P 0 A 5 A A BST SOFT EN_PSV C5 0. μf R 0R V o BST R7 5 LX LXBST LX LX LXS 0R 8 I 7 LIM FB 6 PGD TON t ON R0 6.8K lxbst LX I LIM FB R8 PGD R 00 C6 0. μf 0K C0 68 pf P7 P GOOD V DD 5 R5 R C6 560 pf R5 0K J5 probe test pin L R * / / Revision: 8-Jul-6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT C R 00 C C 0. μf P Step_I_Sense C5 R C R0 P LDTRG + C6 Q Si8BDY C7 + C8 + R5 00K C7 0. μf C μf C5 open C μf R0 5.K R 5.K C μf C μf R5 C8 P0 P5 VCTL P V O_ R5 B B V o V O_ V DAC input

3 DAC simulation V DC :.8600 V I DC : 7. μa Probe (pin 0) 5 DC simulation of SC0A 8 I DC : -0 pa R I DC : -0 pa Probe 6 Ω Probe R Ω FB, (pin ) Probe 5 V V V A, pins, 0, 5 I DC : 7. μa Probe R 50 Ω I DC : 6 V V REF in SC0A V 6 V Fig. - Operation at Zero Current Point In Fig. it can be observed that the SiC0X control loop will maintain the reference voltage, V, at FB, pin under normal operation. It can be assumed then that the current in R,, will always be 7 μa. It can be further observed using Kirchhoff s Current Law that the sum of the currents at node from and must be equal to the current in. The case shown in Fig. is the zero current point from the calculator in Fig., where the voltage at probe, node 8 is equal to the voltage at probe, node. At this operating point, all current to has to be supplied by. The DAC has no effect on. Thus: = 0.6 x ( + R0/R) + V RIPPLE / (see SiC0X datasheets for further information). Now let s examine lowering the voltage at probe, V DAC. DAC simulation V DC :.7500 V I DC :.7 μa Probe (pin 0) 5 DC simulation of SC0A V 0.57 V V V 8 V DC : mv I DC : -. μa R I DC : -. μa R Ω Probe 6 Ω Probe Probe55 I DC : 7. μa A, pins, 0, 5 Fig. - Operation at V DAC Lower than V REF Revision: 8-Jul-6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT Probe R 50 Ω FB, (pin ) I DC : 6 V V REF in SC0A V 6 V

4 As the DAC voltage is changed below the reference voltage (V REF at node 6 in Fig. ), the current through, R, goes negative. To make up for current being drawn out of node, the output voltage has had to rise so that there is more current from to make up for the current drawn out through, as can be observed in probes,, and. Notice that the voltage across, R, is still, thus the current in R is constant at 7 μa. The next step is to raise the voltage at probe, V DAC. DAC simulation V DC : mv I DC : -.58 μa Probe (pin 0) 5 DC simulation of SC0A 8 V DC :.7 V I DC : μa R I DC : μa Probe 6 Ω Probe R Ω FB, (pin ) Probe 5 V.68 V V V A, pins, 0, 5 I DC : 7. μa V V in SC0A REF 6 I DC : Probe V 6 V R 50 Ω Fig. 5 - Operation at V DAC Higher than V REF Fig. 5 simulates a rise in the DAC voltage above V REF, node 6, and the current through, R, has gone positive. To make up for this current being forced into node, the output voltage has had to fall so that current has to be pulled out of node through to make up for the current being sourced through, as can be observed in probes,, and. Notice that the voltage across, R, is still, thus the current is constant at 7 μa. In this case from the SiC0X is actually below V REF, V. CONTROL LIMITS OF There is a sacrifice in performance that is made though when goes too far below V REF and the current from becomes positive; as this current forces lower, the effective open loop gain of the regulator declines. Put simply, the output voltage regulation gets worse. This is due to the inability of the SiC0X control system to work close to a zero duty cycle and its circuitry to operate near to or at zero volts. The values shown in the circuit in Fig. 5 were used in the reference board in Fig., which was constructed and tested for output voltage regulation at three operating points: 5 V (Fig. 6), 0.5 V, and the zero current point of. V with a fixed V input to demonstrate this point. Revision: 8-Jul-6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

5 SiC0X Output Load Current (A) dv = mv di =.5 A Loadline =. mω Fig. 6-5 V Output Load Regulation SiC0X Output Load Current (A) dv = mv di =.5 A Loadline =. mω.00.8 Fig V Output Load Regulation dv = 5. mv di =.5 A Loadline =. mω SiC0X Output Fig V Output Load Regulation Revision: 8-Jul-6 5 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT Load Current (A)

6 There is no difference in the regulation of the 5 V and. V outputs, but the 0.5 V output regulation is substantially worse, as expected. Practical limits for wide output range designs are from.5 V to 5 V for reasonable output regulation. See circuit as an example. Key point: Optimal performance occurs with at levels from.5 V to 5 V. ADDITIONAL DESIGN CONSIDERATIONS Besides the obvious error terms of resistor and V REF tolerance (see How to Obtain Exacting Resistor Values ), there are a number of other issues that can affect the output voltage tolerance. Let s look at the boundary conditions of the control system. DAC simulation V DC :.80 V I DC : 5.5 μa (pin 0) 5 Probe DC simulation of SC0A 8 V DC : 57.8 mv I DC : -7. μa Probe R 6 Ω I DC : -7. μa Probe R Ω FB (pin ) Probe 5 V 0 V V V A, pins, 0, 5 I DC : 7. μa V in SC0A REF 6 I DC : Probe V V 6 V R 50 Ω Fig. - DAC Limitation at Zero Volt Output If V DAC is brought to zero volts, as in Fig., V DAC, probe is at 57.8 mv, not zero. That is due to the inability of most DACs to actually get to zero volts, even rail-to-rail designs. Key point: these designs are based on an ideal voltage source. Allowances may need to be made for deviations from the ideal. Revision: 8-Jul-6 6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

7 DAC simulation V DC :. V I DC : 58.8 μa (pin 0) 5 DC simulation of SC0A Probe V 0 V V V 8 V5 V DC : -667 nv I DC : -. μa R R Ω Probe 6 Ω Probe Probe 5 I DC : -. μa A, pins, 0, 5 I DC : 7. μa 6 I DC : Probe V V V in SC0A 6 V REF R 50 Ω FB (pin ) Fig. 0 - Addition of Negative Rail to DAC Buffer In Fig. 0 a negative voltage, V5, is added to the DAC circuit and now the output of the DAC simulation at node 8 actually goes to zero volts and the regulator output voltage matches that of the calculator spreadsheet. A DAC with a buffer can have a negative supply to allow V DAC to go to zero. Key point: watch for non-linearity in the DAC (voltage source), both at the lower and upper ends of its output range. DAC simulation V DC : 5.0 V I DC : 5.68 μa Probe (pin 0) 5 DC simulation of SC0A V 0 V V V 8 V5 V DC : -667 nv I DC : -. μa Probe R 6 Ω I DC : -. μa A, pins, 0, 5 Probe V DC : mv I DC : 7. μa R Ω R 50 Ω Fig. - Simulation Showing Effect of Input Bias Currents Revision: 8-Jul-6 7 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT Probe FB (pin ) Probe5 I DC :.0 ua R 500 kω 6 V V REF in SC0A V 6 V

8 If there is an input current required on the FB, (pin ), then this current will subtract from, R. In the simulation in Fig., R, a 500 k resistor, was added from FB, (pin ) to ground. This requires that an additional. μa be supplied by so the output voltage, observed at probe, rises by mv to add the required current to keep node at. Key point: watch for input offset currents. DAC simulation V DC : 8.0 mv I DC : μa Probe (pin 0) 5 DC simulation of SC0A 0.0 V to 0 V 500 khz V6 V.6 V V V 8 V5 V DC :.7 V I DC : μa R I DC : μa R Ω Probe 6 Ω Probe Probe 5 A, pins, 0, 5 V DC : mv I DC : 7.5 μa V V in SC0A REF 6 I DC : -. pa Probe V 6 V R 50 Ω FB (pin ) 7 Fig. - Effect on Setting Due to Influence of Ripple Referring to Fig., let us look at the effects of ripple on. Since most switching regulators have some output ripple, one has to consider that this is a noise component whose average value can affect the feedback of the regulator. Referring back to Fig. 5, it can be seen that when we set the DAC voltage in our simulation of this design to.68 V (shown as.7 V at probe ), we get an output of mv. If we then add a 0 mv peak-to-peak 500 khz ripple to the output and R (as shown in Fig. ) is removed so that the offset current will not influence the result, we can observe the effect of the injected ripple signal. The output voltage has dropped about mv, demonstrating that ripple and noise can affect also. In an actual application where the bandwidth of the control loop is less than the op-amps in the simulation model, the effect will be greater; typical values are 5 mv to 0 mv. CALCULATOR The calculator requires that users know five different parameters:. V REF.. SiC0X output voltage range (the minimum voltage and the maximum voltage). The maximum output voltage of the DAC 5. The number of DAC bits All other parameters are calculated for users. There is a section that is useful for programmers that allows the translation of DAC counts in decimal and hex format to and V DAC. Revision: 8-Jul-6 8 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

9 EXAMPLE DESIGNS Circuit : AVS Design This is a circuit that would be useful to most AVS and margining applications that are in the V region. Fig. shows the results from the spreadsheet design tool. Step : Calculate and V REF (R above) I RBOT (A) SiCXX max SiCXX min.. Determine DAC gain (DAC V / output V) (ratio) Determine zero current point for (V DAC = V REF ) Calculated Calculated / Step : Input DAC or voltage source parameters DAC max. DAC bits (number) DAC LSB DAC LSB adjust in SiCXX Total count (theoretical number of voltage steps) (number) Fig. - Design Tool Calculations for Circuit DAC simulation V DC : 87 mv I DC : 77. μa DC simulation of SC0A (test point P0) V.5 V V 5 V 7 V5 V DC :.50 V I DC :.5 μa 8 Probe R00 8 Ω I DC :.5 μa Probe 5 Probe R0 850 Ω I DC : 7 μa Probe R 50 Ω I DC : -8 na FB pin Probe 5 V6 0 V 6 V V REF in SC0A V V A, pins, 0, 5 Fig. - Simulation Schematic (Refer to Fig. for Actual Schematic) Revision: 8-Jul-6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

10 Shaping Response Fig. shows how has been cut in half so that there are two resistors, R5 and R5, allowing a capacitor to be added in between them. This capacitor will shape the response of to a transition command from the V DAC. If the response time, t r, is set at five time constants so it is close to 0 μs, this will result in the best response time of the regulator. This time can be determined from: t r = /(f sw x 0.) and t r = (R total ) x C8 x 5, where: R total = R5 R5 for f sw = 500 khz, then: /(0. x ) = 0 x 0-6 s, or 0 μs. Divide by five and something close to 5 μs is required. Since R5 has been set equal to R5, then R5 R5 = 0.5 x R5 or k. Thus: k x 70 pf = 5.6 μs x 5 is 8. μs. 70 pf was chosen as it is a standard value. In a simulator it looks like this, where the reference values (R5, C8, and R5) refer to Fig. : V 0 V to.50 V 0.5 ms to 0 ms / R5 kω C8 70 pf / R5 kω V V DAC 0 V REF These are the simulation results. Fig. 5 - Transient Simulation Circuit.6. Transient analysis V() (0.08,.5000).7 Voltage V() V() (0.0000, ) Time (ms) Fig. 6 - Transient Step Simulation Result (Note: V and V Refer to the Voltages at the Nodes and, not to the Sources V and V) Revision: 8-Jul-6 0 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

11 Here is what the output voltage transition of the regulator looks like (showing a 0 % to 0 % rise time): Fig. 7 - Transition at no Load Referring to Fig., channel is a regulator at P0 (yellow) with V offset, channel is V DAC, and channel is the LX node at J5. Conditions are no load on, V input. Here is the same transition but with a 6 A load (all scope settings the same as Fig. 7): Fig. 8 - Transition at 6 A Load Key point: loading does not substantially affect the transition speed. Revision: 8-Jul-6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

12 Transient Response of Circuit Again, referring to Fig., let us look at how the COT architecture of the SiC0X results in a fast response to both load and V DAC commands. Fig. - Increasing Transient Load with Static DAC Setting Fig. 0 - Load Release with Static DAC Setting Whenever two parameters change at one time, there might be unwanted effects. Let us look at what happens when both and load current are changed together. Revision: 8-Jul-6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

13 Fig. - Increasing Load from A to 6 A, Increase from 0.5 V to.05 V Driven by a DAC Let us examine the extremes; where V DAC is driven from a function generator so that the V DAC transition is 0 ns. Fig. - I OUT Changes from 6 A to A while is Adjusted from. V to 0.6 V Revision: 8-Jul-6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

14 Fig. - I OUT Changes from 6 A to A while is Adjusted from 0.6 V to. V Fig. - I OUT Changes from A to 6 A while is Adjusted from. V to 0.6 V Revision: 8-Jul-6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

15 Fig. 5 - I OUT Changes from A to 6 A while is Adjusted from 0.6 V to.0 V Excellent transient performance is observed even under the worst case conditions due to the COT architecture of the SiC0A. DC Load Regulation of Circuit SiC0X Output dv = mv di = 6.0 A Loadline = 68 μω Load Current (A) Fig V Load Regulation 5 6 Revision: 8-Jul-6 5 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT 7

16 dv = mv di = 6.0 A Loadline = 500 μω SiC0X Output Load Current (A) Fig V Load Regulation Circuit : Using a Tri-State Buffer for a Voltage Margining Circuit With a slight modification to circuit, a tri-state buffer can be used in place of the DAC as a three-output voltage source; is selected by the state of the buffer. For purposes of the calculator, the buffer is a 0 bit DAC. Step : Calculate and V REF 0.6 Determine DAC gain (DAC V / output V) Determine zero current point for (V DAC = V REF ) (R Calculated Calculated above) I RBOT SiCXX SiCXX min. / (A) max. (ratio) Step : Input DAC or voltage source parameters DAC max. DAC bits (number) DAC LSB DAC LSB adjust in SiCXX Total count (theoretical number of voltage steps) (number) Fig. 8 - Tri-State Voltage Margining Circuit Calculation Result If the buffer s output is active and is set to logic low, then there will be a. V output. If it is set at logic high, there will be a. V output. If at tri-state (not active), the will be at the zero current point, or.0 V output. Any tri-state output could be used from an ASIC, FPGA, etc. Revision: 8-Jul-6 6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

17 Here are the simulations: Tri-state simulation V CC.8 V V DC :.0 V I DC : 7. μa Probe R0 6 Ω (P0) DC simulation of SC0A U NC7SZ6_V V 0 V.8 V 0.5 ms ms I DC :.00 na R5 Probe Ω Ω Probe Probe 5 A, pins, 0, 5 V DC : 5 mv I DC :. na R5 V DC : 5. mv C I DC : 7. μa 0 pf V DC : 5. mv 7 I DC : -7.0 pa Probe V V R V in SC0A 6 V REF 50 Ω FB pin Fig. - Tri-State Example with U at Tri-State Tri-state simulation V CC.8 V V CC U NC7SZ6_V V DC : 8. μv I DC : -8. μa R5 Probe R0 7 I DC : -7. pa Probe V V R V in SC0A 6 V REF Fig. 0 - Tri-State Example with Tri-State not Active and Logic Output at Zero Volts Revision: 8-Jul-6 7 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT 6 Ω Probe Ω Ω Probe Probe 5 A, pins, 0, 5 R5 I DC : -8. μa C I DC : 7. μa 0 pf V DC :.00 V I DC : 5.8 μa 50 Ω (P0) FB pin DC simulation of SC0A

18 Tri-state simulation V CC.8 V V CC U NC7SZ6_V V DC :.00 V I DC :. μa R5 R5 I DC :. μa Probe R0 6 Ω (P0) FB pin Probe Ω Ω Probe Probe 5 C I DC : 7. μa 0 pf V DC : mv I DC : μa DC simulation of SC0A 7 I DC : -7. pa Probe V V R V in SC0A 6 V REF 50 Ω A, pins, 0, 5 Fig. - Tri-State Example with Tri-State not Active and Logic Output at V In Fig. the simulation shows a of V rather than the 0. V designed for. This is due to an artifact of the simulation, as the model for the buffer assumes a V power rail as opposed to the intended.8 V rail. Circuit : Wide Range Output This is a wide range output example. It would be useful for a designer that needs to set the rail for output buffers at different voltages such as.5 V,.8 V,.5 V,. V, and 5 V. Step : Calculate and V REF (R above) I RBOT (A) SiCXX max. SiCXX min. Determine DAC gain (DAC V / output V) (ratio) Determine zero current point for (V DAC = V REF ) Calculated Calculated / Step : DAC max. Input DAC or voltage source parameters DAC bits (number) DAC LSB DAC LSB adjust in SiCXX Total count (theoretical number of voltage steps from DAC) (number) Fig. - Circuit Calculator Result Revision: 8-Jul-6 8 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

19 DAC simulation V DC :.500 V I DC : 6.6 μa Probe R0 85 Ω (P0) DC simulation of SC0A 6 V.5 V V V V5 V DC :.50 V I DC : 0.7 μa 8 R5 R5 I DC : 0.7 μa FB pin Probe 0 7 Ω 0 7 Ω Probe Probe 5 C I DC : 7. μa 000 pf 7 I DC : -7. pa Probe V V R V in SC0A 6 V REF 50 Ω A, pins, 0, 5 Fig. -.5 V to 5.5 V Simulation The calculator can be used to determine what the register settings are for the DAC. In this case, a 0-bit DAC allows a.7 mv per LSB adjustment of. Using the programmer s tool, the desired values can be entered and the proper register values can be determined: Convert regulator output voltage to DAC count Regulator Count.5 7 Hex E 5 Fig. - Determining Register Settings for the DAC Using the same circuit as above, a power rail for a bridge-based sensor can also be set up. In this case bits would be added to the DAC based on calibration needs. Input DAC or voltage source parameters DAC bits (number) DAC LSB DAC LSB adjust in SiCXX Total count (theoretical number of voltage steps from DAC) (number) Fig. 5 - More DAC Bits Yields Increased Resolution in Adjustability In this circuit regulation is.80 V at 0 A and.5 V at 6 A; 5.0 V at 0 A and 5.88 V at 6 A. Revision: 8-Jul-6 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

20 How to Obtain Exacting Resistor Values In each of these designs it is critical that the resistor values for,, and be quite precise. The ohmic value requirements of these resistors can vary greatly over the design possibilities. 0. % resistors may not meet the designer s requirements. In these instances, there is a useful tool by which a parallel or series combination of % resistors can be determined that will meet the design goal. It is located at jansson.us/resistors.html. Here is an example of the calculation of, R0, from circuit in Fig., using the URL above: Fig. 6 - Precision Resistor Calculator In this case would consist of a k, % resistor in parallel with an 80 k, % resistor. If both resistors were exactly at their stated values, the final parallel value would be off by -0.5 %. There are also highly precise 0.0 % resistors with very low temperature coefficients that come in non-standard values and are made to order, such as the PLT series from Vishay (see THE PROTOTYPE DAC and C8 area Fig. 7 - Prototype Photograph Reference board Alternate SiC0A demoboard Revision: 8-Jul-6 0 Document Number: 650 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT