Bi-Directional P-Channel MOSFET/Power Switch

Transcription

1 Bi-Directional P-Channel MOSFET/Power Switch PRODUCT SUMMARY V DS (V) R DS(on) (Ω) I D (A) ± 7 DESCRIPTION.7 at V GS = -.5 V ±.. at V GS = -.5 V ±. The is a low on-resistance p-channel power MOSFET providing bi-directional blocking and conduction. Bi-directional blocking is facilitated by combining a -terminal symmetric p-channel MOSFET with a body bias selector circuit a. Circuit operation automatically biases the p-channel body to the most positive source/drain potential thereby maintaining a reverse bias across the diode present between the source/drain terminals. Off-state device blocking characteristics are symmetric, facilitating bi-directional blocking for high-side battery switching in portable products. Gate drive is facilitated by negatively biasing the gate relative to the body potential. The off-state is achieved by biasing the gate to the most positive supply voltage or to the body potential. The is available in a -pin TSOP- package rated for the - 5 C to 85 C commercial temperature range. FEATURES Halogen-free According to IEC 9-- Definition Low R DS(on) Symmetrical P-Channel MOSFET Integrated For Bi-Directional Blocking.5 V to 5.5 V Operation Exceeds ± kv ESD Protected Solution for High-Side Battery Disconnect Switching (BDS) Supports Battery Switching in Multiple Battery Cell Phones, PDAs and PCS Products Low Profile, Small Footprint TSOP- Package Compliant to RoHS Directive /95/EC APPLICATION CIRCUITS AC/DC Adapter Charger Loads DC/DC Charger Figure. Charger Demultiplexing Figure. Battery Multiplexing (High-Side Switch) Note: a. Patents pending. Document Number: 7785 S9-7-Rev. D, -Nov-9

2 FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION S/D () TSOP- Top View G (3) P-Channel MOSFET ESD Protection Generator BODY 3 mm SUB 5 S/D SUB G 3 D/S D/S () BODY () Figure 3. SUBSTRATE (GND) (, 5).75 mm Figure. Ordering Information: -T-E3 (Lead (Pb)-free) -T-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS T A = 5 C, unless otherwise noted Parameter Symbol Limit Unit Drain-Source Voltage, Source-Drain Voltage a V DS - 7. to + 7. Source-, Drain-, Gate- Voltage V SB, V DB, V GB.3 to - 7. V -Substrate Voltage V BSUB + 7. to -.3 Continuous Drain-to-Source Current (T J = 5 C) a, b T A = 5 C ±. I D T A = 7 C ±. A Pulsed Drain-to-Source Current a I DM ± 8 T A = 5 C Maximum Power Dissipation b.5 P D T A = 7 C. W Operating Junction and Storage Temperature Range T J, T stg - 55 to 5 C RECOMMENDED OPERATING RANGE Parameter Symbol Range Unit Drain-Source Voltage a V DS to 5.5 Gate-Drain, Gate-Source Voltage V GD, V GS to V Source-, Drain-, Gate- Voltage V SB, V DB, V GB to Drain-to-Source Current a, b I DS ±. A -Source Current I BS to µa THERMAL RESISTANCE RATINGS Parameter Symbol Limit Unit Maximum Junction-to-Ambient b 8 R thja C/W 5 Notes: a. Bi-directional. b. Surface Mounted on FR board, t 5 s. c. Surface Mounted on FR board, Steady-State. Document Number: 7785 S9-7-Rev. D, -Nov-9

3 SPECIFICATIONS V BS = V, T J = 5 C, unless otherwise noted Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Gate Threshold Voltage V GS(th) V DS = V GS, I D = - 5 µa -. V Gate- Leakage I GSS V DS = V, V GS = V to +.3 V ± na V DS = V, V GS = V, V SB = V - Zero Gate Voltage Drain Current I DSS V DS = V, V GS = V, V SB = V, T J = 7 C - 5 µa On-State Drain Current a I D(on) V DS = - 3 V, V GS = -.5 V - 8 V DS = - 3 V, V GS = -.5 V - 3 Total Gate Charge Q g V GS = -.5 V, I D = -. A Drain-Source On-State Resistance a.3.7 R DS(on) V GS = -.5 V, I D = -. A.8. Dynamic b.. Gate-Source Charge Q gs V DS = - 5 V, V GS = -.5 V, I D = -. A.3 Gate-Drain Charge Q gd. Turn-On Delay Time t d(on) 5 Rise Time t r V DD = - 3 V, R L = 3 Ω 55 Turn-Off Delay Time t d(off) I D -. A, V GEN = -.5 V, R g = Ω 9 8 Fall Time t f 85 7 Notes: a. Pulse test; pulse width 3 µs, duty cycle %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. A Ω nc ns GATE BUFFER REFERENCE Load Load IN IN Figure 5. Gate Buffer Referenced to Most Positive Supply Figure. Gate Buffer Referenced to Pin Document Number: 7785 S9-7-Rev. D, -Nov-9 3

4 TYPICAL CHARACTERISTICS 5 C, unless otherwise noted 8 V GS = 5 V thru 3 V.5 V 8 T C = - 55 C 5 C - Drain Current (A) I D V.5 V I D - Drain Current (A) 5 C V 3 5 V DS - Drain-to-Source Voltage (V) Output Characteristics V GS - Gate-to-Source Voltage (V) Transfer Characteristics 5 - On-Resistance (Ω) R DS(on).3.. V GS =.5 V V GS =.5 V C - Capacitance (pf) 5 5 C oss C iss C rss 8 I D - Drain Current (A) On-Resistance vs. Drain Current V DS - Drain-to-Source Voltage (V) Capacitance. - Gate-to-Source Voltage (V) V DS = 3 V I D =. A R DS(on) - On-Resistance (Normalized) V GS =.5 V I D =. A V GS Q g - Total Gate Charge (nc) Gate Charge T J - Junction Temperature ( C) On-Resistance vs. Junction Temperature Document Number: 7785 S9-7-Rev. D, -Nov-9

5 TYPICAL CHARACTERISTICS 5 C, unless otherwise noted 8.5 I S - Source Current (A) T J = 5 C T J = 5 C - On-Resistance (Ω) R DS(on)..3.. I D =.5 A I D =. A V SD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage. 3 5 V GS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage 5.3 Variance (V) V GS(th)... I D = 5 µa Power (W) T J - Temperature ( C) Threshold Voltage.. Time (s) Single Pulse Power Normalized Effective Transient Thermal Impedance Duty Cycle =.5. t.. P DM.5 t t. Duty Cycle, D = t.. Per Unit Base = R thja = 8 C/W 3. T JM - T A = P DM Z (t) thja Single Pulse. Surface Mounted Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Notes: Document Number: 7785 S9-7-Rev. D, -Nov-9 5

6 TYPICAL CHARACTERISTICS 5 C, unless otherwise noted V GB = -.5 V I D - Drain Current (A) - V GB = V V DS - Drain-to-Source Voltage (V) Bi-Directional Blocking Drain-Source Voltage maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?7785. Document Number: 7785 S9-7-Rev. D, -Nov-9

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