±18V Operation 2-Channel Electronic Volume. Selectable 8-Chip Address Available for using eight chips on same serial bus line

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±18V Operation 2-Channel Electronic Volume MUSES7232 GENERAL DESCRIPTION The MUSES7232 is a ±18V operation 2-channel electronic volume, which is optimized for high-end audio and professional audio

All of functions are controlled via three-wired serial bus. Selectable 8-Chip address is available for using eight chips on same serial bus line.

1 ±18V Operation 2-Channel Electronic Volume MUSES7232 GENERAL DESCRIPTION The MUSES7232 is a ±18V operation 2-channel electronic volume, which is optimized for high-end audio and professional audio applications with advanced circuitry and layout. The MUSES7232 performs low noise and low distortion characteristics and with resistance ladder circuit. All of functions are controlled via three-wired serial bus. Selectable 8-Chip address is available for using eight chips on same serial bus line. It s suitable for highly linear volume control of Hi-fi audio systems. PACKAGE OUTLINE MUSES7232V FEATURES Operating Voltage ±8.5 to ±18V 3-Wired Serial Control Chip Address Select Function Selectable 8-Chip Address Available for using eight chips on same serial bus line Low Output Noise *It conforms to the characteristic of an external operational amplifier. Low Distortion *It conforms to the characteristic of an external operational amplifier. Volume db to 111.5dB /.25dBstep, MUTE 31.5 to db /.5dBstep Channel Separation -12dB typ. Zero Cross Detection circuit Detection CMOS Technology Package Outline SSOP32 BLOCK DIAGRAM V Zero Cross Detection Control Logic Z/C D_VDD V- DATA LATCH ADR1 CLOCK ADR ADR2 D_REF Ver. 1.1E 1

2 PIN FUNCTION No. SYMBOL FUNCTION No. SYMBOL FUNCTION 1 Z/C REFL Lch Zero Cross Detection circuit Reference Voltage 17 D_VDD Digital block Power Supply 2 L_REF Lch Reference Voltage 18 DATA Control data signal input 3 L Lch Opamp non-inverting input connect terminal 19 CLOCK Clock signal input 4 L_REF Lch Reference Voltage 2 LATCH Latch signal input 5 L- Lch Opamp inverting input connect terminal 21 D_REF Digital block Reference Voltage 6 L_REF Lch Reference Voltage 22 V Power Supply () 7 OutL Lch output 23 InR Rch input 8 DCCAP_L Switching noise rejection capacitor (Lch) 24 V Power Supply () 9 DCCAP_R Switching noise rejection capacitor (Rch) 25 V - Power Supply (-) 1 OutR Rch output 26 InL Lch input 11 Rch Reference Voltage 27 V - Power Supply (-) 12 R- Rch Opamp inverting input connect Digital block Noise Rejection 28 D_CAP terminal Capacitor terminal 13 Rch Reference Voltage 29 ADR2 Chip address setting terminal 2 14 R Rch Opamp non-inverting input connect terminal 3 ADR1 Chip address setting terminal 1 15 Rch Reference Voltage 31 ADR Chip address setting terminal 16 Z/C REFR Rch Zero Cross Detection circuit Zero Cross Detection circuit ON/OFF 32 Z/C Reference Voltage setting terminal 2

3 ABSOLUTE MAXIMUM RATING (Ta=25 C) PARAMETER SYMBOL RATING UNIT Power Supply Voltage V /V - 2/-2 V Maximum Input Voltage V IM V /V - V Power Dissipation P D 1 NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting Operating Temperature Range Topr -4 ~ 85 C Storage Temperature Range Tstg -4 ~ 125 C mw ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Power Supply (Ta=25 C, V /V - = 15V, unless otherwise specified) Operating Voltage V /V V Supply Current 1 I CC No signal ma Supply Current 2 I EE No signal ma Input/Output Characteristics 1 (Ta=25 C,V /V - = 15V, V IN=2Vrms, f=1khz, Volume=dB, Gain=dB, V OUT with MUSES1, R L=47kΩ, unless otherwise specified) Maximum Input Voltage V IM f=1khz,thd=1% Volume=-2dB Vrms Voltage Gain 1 G V1 V IN=2Vrms, f=1khz db Voltage Gain 2 G V2 V IN=2mVrms, f=1khz Gain=15dB db Voltage Gain Error 1 G V1 V IN=2Vrms, f=1khz db Voltage Gain Error 2 Maximum Attenuation Mute level Channel Separation 1 G V2 A TT Mute CS1 V IN=2Vrms, f=1khz Volume=-6dB V IN=4Vrms, f=1khz Volume=-111.5dB, A-weight f=1khz, V IN=4Vrms Volume=Mute, A-weight f=1khz, V IN =2Vrms, Rg=Ω A-weight db db db db Channel Separation 2 CS2 f=2khz, V IN =2Vrms, Rg=Ω db Input Impedance R IN 23pin, 26pin kω Input/Output Characteristics 2 (Ta=25 C,V /V - = 15V, V IN=2Vrms, f=1khz, Volume=dB, Gain=dB, V OUT with MUSES1, R L=47kΩ, unless otherwise specified) Maximum Output Voltage Total Harmonic Distortion 1 Total Harmonic Distortion 2 V OM THD1 THD2 f=1khz,thd=1% Volume=-6dB, Gain=6dB f=1khz,v IN=1Vrms BW=4Hz-3kHz f=1khz,v IN=1Vrms BW=4Hz-3kHz Vrms % % 3

4 ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Input/Output Characteristics 3 (Ta=25 C, V /V - = 15V, V IN=2Vrms, f=1khz, Volume=dB, V OUT : 3pin, 14pin, R L=1kΩ, unless otherwise specified) Output Noise1 V NO1 Rg=Ω, A-weight - Output Noise2 Logic Control Characteristics V NO2 Volume=-111.5dB Rg=Ω, A-weight (1.26μ) -118 (1.26μ) -1 (1μ) - dbv (Vrms) dbv (Vrms) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Digital block Power Supply Characteristics D_VDD Terminal Input Voltage V DVDD 17pin Terminal Input - -.8*V V D_REF Terminal Input Voltage V DREF 21pin Terminal Input V V Digital block Supply Voltage V DD V DD = V DVDD V DREF V Range Logic Control Terminal Characteristics (Ta=25 C, V /V - = 15V, V DREF =V, unless otherwise specified) High Level Input Voltage1 V IH1 DATA, CLOCK, LATCH.7*V DD - V DD V Low Level Input Voltage1 V IL1 DATA, CLOCK, LATCH -.3*V DD V Chip Address / Zero cross Terminal Characteristics (Ta=25 C, V /V - = 15V, V DREF =V, unless otherwise specified) High Level Input Voltage2 V IH2 ADR, ADR1, ADR2, Z/C.7*V DD - V V Low Level Input Voltage2 V IL2 ADR, ADR1, ADR2, Z/C -.3*V DD V 4

5 TERMINAL DESCRIPTION PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT V TERMINAL DC VOLTAGE InR InL Rch input Lch input 1Ω 2kΩ V L_REF L_REF Lch Reference Voltage Rch Reference Voltage V 1.5kΩ V V 3 14 L R Lch Opamp non-inverting input connect terminal Rch Opamp non-inverting input connect terminal V V 5 12 L- R- Lch Opamp inverting input connect terminal Rch Opamp inverting input connect terminal V 5

6 TERMINAL DESCRIPTION PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT TERMINAL DC VOLTAGE V 1Ω 7 1 OutL OutR Lch output Rch output V V 8 DCCAP_L Switching noise rejection capacitor (Lch) 9 DCCAP_R Switching noise rejection capacitor (Rch) 1.5kΩ V V V 16 1 Z/C REFR Z/C REFL Rch Zero Cross Detection circuit Reference Voltage Lch Zero Cross Detection circuit Reference Voltage 4kΩ 4kΩ V V DATA CLOCK LATCH Control data signal input Clock signal input Latch signal input 2Ω - 6

7 TERMINAL DESCRIPTION PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT D_VDD V V 125kΩ TERMINAL DC VOLTAGE 21 D_REF Digital block Reference Voltage - 125kΩ V V 125kΩ 17 D_VDD Digital block Power Supply - 125kΩ D_REF V Power Supply () V V V Z/C ADR2 ADR1 ADR Zero Cross Detection circuit ON/OFF setting terminal Chip address setting terminal 2 Chip address setting terminal 1 Chip address setting terminal 1Ω - V 28 D_CAP Digital block Noise Rejection Capacitor terminal 1Ω V 7

8 TEST CIRCUIT 1 Supply Current 1 (I CC), Supply Current 1 (I EE) V- V V V V V 15V A I EE A I CC 15V LATCH CLOCK DATA VDD Z/C ADR ADR1 ADR2 V- 5V RD k 1 F R D k D_CAP A_VEE A_VEE A_VCC A_VCC D_REF D_VDD Ref = 4V Control Logic 2k 2k L_REF 1k 1k Z/C REFL L_REF L_REF L_REF Z/C REFR TEST CIRCUIT 2 Maximum Input Voltage (V IM), Maximum Output Voltage (V OM), Voltage Gain 1 (G V1), Voltage Gain 2 (G V2), Maximum Attenuation (A TT), Mute level Mute), Total Harmonic Distortion 1(THD1), Total Harmonic Distortion 2(THD2) V V V V V- V LATCH CLOCK DATA VDD V IN 15V 15V V IN Z/C ADR ADR1 ADR2 V- 5V RD k 1 F R D k D_CAP A_VEE A_VEE A_VCC A_VCC D_REF D_VDD Ref = 4V Control Logic 2k 2k L_REF 1k 1k Z/C REFL L_REF L_REF L_REF Z/C REFR 1pF 1pF MUSES1 MUSES892 V OUT V R L=47k V OUT V MUSES1 MUSES892 R L=47k 8

9 TEST CIRCUIT 3 Output Noise 1(V NO1), Output Noise 1(V NO2) V- V V V V V LATCH CLOCK DATA VDD 15V 15V Z/C ADR ADR1 ADR2 V- 5V R D k 1 F RD k D_CAP A_VEE A_VEE A_VCC A_VCC Ref = 4V D_REF D_VDD Control Logic 2k 2k L_REF 1k 1k Z/C REFL L_REF L_REF L_REF Z/C REFR V OUT (Filter: A-weght) V R L=1k V OUT (Filter: A-weght) V R L=1k TEST CIRCUIT 4 Channel Separation 1(CS1), Channel Separation 2(CS2) V V V V V- V LATCH CLOCK DATA VDD 15V 15V V IN Z/C ADR ADR1 ADR2 V- 5V RD k 1 F R D k D_CAP A_VEE A_VEE A_VCC A_VCC D_REF D_VDD Ref = 4V Control Logic 2k 2k L_REF 1k 1k Z/C REFL L_REF L_REF L_REF Z/C REFR 1pF 1pF MUSES1 MUSES1 V OUT V R L=47k R L=47k 9

10 APPLICATION CIRCUIT <Application circuit with J-FET Input type OpAmp.> InL InR LATCH CLOCK DATA VDD V F CIN V- V CIN F 5V Caution!! RD k 1 F RD k Z/C ADR ADR1 ADR2 D_CAP A_VEE A_VEE A_VCC A_VCC Ref = 4V D_REF D_VDD Control Logic 2k 2k L_REF 1k 1k Z/C REFL L_REF L_REF L_REF Z/C REFR 1pF 1pF J-FET Input type MUSES1, MUSES892, NJM891, NJM282,, etc J-FET Input type MUSES1, MUSES892, NJM891, NJM282,, etc OutL OutR <Application circuit with Bipolar Input type OpAmp.> InL InR LATCH CLOCK DATA VDD V- Caution!! F CIN V- V C IN F 5V R D k 1 F R D k Z/C ADR ADR1 ADR2 D_CAP A_VEE A_VEE A_VCC A_VCC Ref = 4V D_REF D_VDD Control Logic 2k 2k L_REF 1k 1k Z/C REFL L_REF L_REF L_REF Z/C REFR R bias * 47k 1pF Bipolar Input type MUSES2, MUSES882, NJM88,NJM2114, 47 NJM5532,NJM268, NJM458, etc OutL 47 OutR 1pF Bipolar Input type MUSES2, MUSES882, NJM88,NJM2114, NJM5532,NJM268, NJM458, etc R bias * 47k 1

11 NOTES It is necessary to add R D to 1k for the over-current protection. Without this resistor, the IC may be damaged, depending on the power procedure. 15V V V V No Current Current flow s 5V D_VDD 125kΩ 5V D_VDD 125kΩ 125kΩ 125kΩ D_REF D_REF a) The power[v] is greater than the power[d_vdd]. b) The power[v] is less than the power[d_vdd]. Fig.1 Damaged path of the MUSES7232 The input coupling capacitors(c IN) and the input resistance(r IN=2k ) form a high-pass filter with the corner frequency determined in [fc=1/(2 R INC IN)]. The R bias affects the Volume(Att.) linearity characteristic. When R bias value is too small, the amount of attenuation increases, so that the output amplitude becomes small and THD deteriorates by an internal analog switch. On the other hand, when R bias is too large, it may be affected at the noise from the outside. Please decide resistance value after it verifies it enough by an actual application. Separate for REF terminals for High and Middle voltage(ac) and REF terminals for Low voltage(ac) in the pattern design. Pin No. Function Purpose 2 Lch Reference Voltage for Low voltage(ac) signal 4 Lch Reference Voltage for Middle voltage(ac) signal 6 Lch Reference Voltage for High voltage(ac) signal 11 Rch Reference Voltage for High voltage(ac) signal 13 Rch Reference Voltage for Middle voltage(ac) signal 15 Rch Reference Voltage for Low voltage(ac) signal Table.1 Purpose of Reference Voltage Terminal 11

12 CONTROL DATA FORMAT t7 t1 t4 t8 LATCH t2 t3 CLOCK MSB LSB DATA D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D ( ) MSB First t5 t6 Note.) Set CLOCK in High to prevent incorrect operation during a standby period. SYMBOL PARAMETER MIN TYP MAX UNIT t1 CLOCK Clock Width sec t2 CLOCK Pulse Width (High) sec t3 CLOCK Pulse Width (Low) sec t4 LATCH Rise Hold Time sec t5 DATA Setup Time sec t6 DATA Hold Time sec t7 CLOCK Setup Time sec t8 LATCH High Pulse Width sec CONTROL DATA MUSES7232 control data is constructed with 16bits. MSB D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D MSB Data Select Address Chip Address D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Lch Volume Control (Att.) * * * Lch Volume Control (Gain) 1 * * * Rch Volume Control (Att.) 1 * * * Rch Volume Control (Gain) 1 1 * * * L/R Cont 1 L/R Cont 2 Z/C Don t Care Don t Care Don t Care Don t Care LSB LSB Don t Care 1 * * * * Chip address is set by chip address select terminals (ADR, ADR1,ADR2) status. Chip address select terminal Chip address ADR2 (29pin) ADR1 (3pin) ADR (31pin) D3 D2 D1 D Low Low Low Low Low High 1 Low High Low 1 Low High High 1 1 High Low Low 1 High Low High 1 1 High High Low 1 1 High High High

13 INITIAL CONDITION MSB D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D * * * 1 * * * 1 * * * 1 1 * * * 1 * * * Note.) This product starts up by MUTE setting in power ON. Use it after removing MUTE of each setting. If any audio signal is inputted in input signal terminal before power ON, it may cause initial condition abnormality. In conditions of use such as the above, it prevents that abnormality by setting MUTE before power OFF" LSB 13

14 DEFINITION OF RESISTOR Volume Control (Att.) : db to 111.5dB /.5dBstep. : Lch Volume and Rch Volume are controlled independently when L/R Cont 1 =. D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Lch Volume Control (Att.) * * * * Rch Volume Control (Att.) 1 * * * * < Volume Control Data > Data Setting D15 D14 D13 D12 D11 D1 D9 D8 Mute ( ) 1 db dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 1-8.dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 14

15 < Volume Control Data > Data Setting D15 D14 D13 D12 D11 D1 D9 D dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 15

16 < Volume Control Data > Data Setting D15 D14 D13 D12 D11 D1 D9 D dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 1-56.dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 16

17 < Volume Control Data > Data Setting D15 D14 D13 D12 D11 D1 D9 D dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 17

18 < Volume Control Data > Data Setting D15 D14 D13 D12 D11 D1 D9 D dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Mute ( ) Initial Setting 18

19 Volume Control (Gain.) : 31.5dB to db /.5dBstep. : Lch Volume and Rch Volume are controlled independently when L/R Cont 2 =. D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Lch Volume Control (Gain) 1 * * * Rch Volume Control (Gain) 1 1 * * * < Volume Control Data > Data Setting D14 D13 D12 D11 D1 D9 D8 db () 1.25dB 1.5dB 1 1.dB dB 1 2.dB dB dB dB 1 4.dB dB dB dB dB dB dB dB 1 8.dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 1 16.dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 19

20 < Volume Control Data > Data Setting D14 D13 D12 D11 D1 D9 D dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ( ) Initial Setting 2

21 L/R Cont 1 L/R Cont 2 Z/C : Select the independent control or the Lch-Rch link control of the method of the volume control (Att). : Select the independent control or the Lch-Rch link control of the method of the volume control (Gain). : Zero Cross Detection circuit ON/OFF setting D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D L/R Cont 1 L/R Cont 2 Z/C Don t Care Don t Care Don t Care <L/R Cont 1 : Method of the volume control (Att).> D15 Setting Don t Care Lch, Rch independent control ( ) 1 Lch-Rch link control ( ) Initial Setting <L/R Cont 2 : Method of the volume control (Gain).> D14 Setting Lch, Rch independent control ( ) 1 Lch-Rch link control ( ) Initial Setting * Command table when Lch, Rch interconnected control Don t Care 1 * * * D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Lch-Rch link control (Att.) * * * Lch-Rch link control (Gain) 1 * * * No Acceptable 1 * * * No Acceptable 1 1 * * * <Z/C : Zero Cross Detection circuit ON/OFF setting > D13 Setting Zero Cross Detection circuit: ON ( ) 1 Zero Cross Detection circuit: OFF ( ) Initial Setting * Zero cross detection circuit is ON When "Z/C terminal = Low" and "Z/C bit =" are set. Z/C bit ( D13") 1 Z/C terminal (32pin) Low High Zero Cross Detection circuit : ON Zero Cross Detection circuit : OFF Zero Cross Detection circuit : OFF Zero Cross Detection circuit : OFF 21

22 Volume Control (Att).25dB to dB(.25dB/step) setting example Using Volume Control(Gain).25dB enables to set.25db/step in the range of.25db to 111.5dB. (8.25dB, 16.25,24.25 also can be used) < Volume Control Data > Lch / Rch Volume Control (Gain) Lch / Rch Volume Control (Att) D14 D13 D12 D11 D1 D9 D8 D15 D14 D13 D12 D11 D1 D9 D8 Gain Setting dB dB dB dB dB dB dB dB dB dB : : dB dB dB 1 1.5dB dB 1 db dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB : : dB dB dB dB dB dB Mute : : : : : : : : 22

23 Maximum Input Voltage [Vrms] Maximum Input Voltage [Vrms] ICC [ma] IEE [ma] ICC [ma] IEE [ma] MUSES7232 TYPICAL CHARACTERISTICS ICC vs Supply Voltage No signal IEE vs Supply Voltage No signal o C 85 o C o C o C o C o C Supply Voltage [±V] ICC vs Ambient Temperature V=±15V, No signal Supply Voltage [±V] IEE vs Ambient Temperature V=±15V, No signal Ambient Temperature [ o C] Maximum Input Voltage vs Frequency V=±15V, THD=1%, VOL=-2dB, GAIN=dB Ambient Temperature [ o C] Maximum Input Voltage vs Ambient Temperature V=±15V, THD=1%, VOL=-2dB, GAIN=dB 11 1 ±15V o C -4 o C 9 8 ±12V 7 85 o C Frequency [Hz] 6 ±8.5V Ambient Temperature [ o C] 23

24 Volume Resolution [db] Volume Resolution [db] Volume Gain Output Error [db] Volume Gain Output Error [db] Volume Gain Output [db] Volume Gain Output [db] MUSES7232 Volume Gain Output vs Volume Setting V=±15V, f=1khz, Vin=4Vrms, GAIN=dB, Bandpass Volume Gain Output vs Frequency V=±15V, f=1khz, Vin=4Vrms, GAIN=dB, Bandpass 2 db -16-2dB , 25, 85 o C dB -6dB -8dB -1dB dB Mute Volume Setting [db] Volume Gain Output Error vs Volume Setting V=±15V, f=1khz, Vin=4Vrms, GAIN=dB, Bandpass Frequency [Hz] Volume Gain Output Error vs Volume Setting V=±15V, f=1khz, Vin=1mVrms, VOL=dB, Bandpass o C 25 o C.5-4, 25, 85 o C o C Volume Setting [db] Volume Resolution vs Volume Setting V=±15V, f=1khz, Vin=4Vrms, GAIN=dB, Bandpass Volume Setting [db] Volume Resolution vs Volume Setting V=±15V, f=1khz, Vin=1mVrms, VOL=dB, Bandpass , 25, 85 o C -4, 25, 85 o C Volume Setting [db] Volume Setting [db] 24

25 Maximum Output Voltage [Vrms] Maximum Output Voltage [Vrms] Input Resistance [kω] Output Resistance [kω] Volume Matching Error [db] Volume Matching Error [db] MUSES Volume Matching Error vs Volume Setting V=±15V, f=1khz, Vin=4Vrms, GAIN=dB, Bandpass Volume Matching Error vs Volume Setting V=±15V, f=1khz, Vin=1mVrms, VOL=dB, Bandpass , 25, 85 o C.5-4, 25, 85 o C Volume Setting [db] Input Resistance vs Volume Setting V=±15V, No signal, Measure:InL Volume Setting [db] Output Resistance vs Volume Setting V=±15V, No signal, Measure:L o C 8 85 o C o C o C 2-4 o C Volume Setting [db] Volume Setting [db] Maximum Output Voltage vs Frequency V=±15V, THD=1%, VOL=-6dB, GAIN=6dB Maximum Output Voltage vs Ambient Temperature V=±15V, THD=1%, VOL=-6dB, GAIN=6dB o C 1 ±18V 1 8 ±15V o C 6 ±8.5V 85 o C Frequency [Hz] Ambient Temperature [ o C] 25

26 [CAUTION] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. 26

8-CHANNEL ELECTRONIC VOLUME WITH INPUT SELECTOR ~ -95dB/0.5dBstep, MUTE. Multi-LSin LSout Stereo Lin ( 7) REC _L.

8-CHANNEL ELECTRONIC VOLUME WITH INPUT SELECTOR GENERAL DESCRIPTION The NJU7234A is a 8-channel electronic volume with Input. It includes 8-in 2-out audio selector, REC Output and Multi-channel inputs.