Highperformance EE PLD ATF16LV8C

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David Bradley
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1 Features 3.V to 5.5V Operation Industry-standard Architecture Emulates Many 2-pin PALs Low-cost Easy-to-use Software Tools High-speed 1 ns Maximum Pin-to-pin Delay Ultra-low Power 5 µa (Max) Pin-controlled Power-down Mode Option Typical 1 na Standby CMOS and TTL Compatible Inputs and Outputs Pin-keeper Circuits Advanced Flash Technology Reprogrammable 1% Tested High-reliability CMOS Process 2 Year Data Retention 1 Erase/Write Cycles 2,V ESD Protection 2 ma Latchup Immunity Commercial and Industrial Temperature Ranges Dual-in-line and Surface Mount Packages in Standard Pinouts Inputs are 5V Tolerant Green Package Options (Pb/Halide-free/RoHS Compliant) Available Highperformance EE PLD Description The is a high-performance EECMOS programmable logic device that utilizes Atmel s proven electrically-erasable Flash memory technology. Speeds down to 1 ns and a 5 µa pin-controlled power-down mode option are offered. All speed (continued) Pin Configurations All Pinouts Top View Pin Name CLK I OE VCC PD Function Clock Logic Inputs Bi-directional Buffers Output Enable (+3V to 5.5V) Supply Programmable Powerdown Option I/CLK I1 I2 PD/I3 I4 I5 I6 I7 I8 GND TSSOP DIP/SOIC VCC I9/OE PD/I3 I4 I5 I6 I PLCC Rev. 43H 6/6 I8 GND I9/OE I2 I1 I/CLK VCC I/CLK I1 I2 PD/I3 I4 I5 I6 I7 I8 GND VCC I9/OE 1

2 ranges are specified over the full 3.V to 5.25V range for industrial and commercial temperature ranges. The incorporates a superset of the generic architectures, which allows direct replacement of the 16R8 family and most 2-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized. The can significantly reduce total system power, thereby enhancing system reliability and reducing power supply costs. When pin 4 is configured as the power-down control pin, supply current drops to less than 5 µa whenever the pin is high. If the power-down feature isn't required for a particular application, pin 4 may be used as a logic input. Also, the pin keeper circuits eliminate the need for internal pull-up resistors along with their attendant power consumption. Block Diagram Note: 1. Includes optional PD control pin. Absolute Maximum Ratings* Temperature Under Bias C to +85 C Storage Temperature C to +15 C Voltage on Any Pin with Respect to Ground...-2.V to +7.V (1) *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Input Pins with Respect to Ground During Programming...-2.V to +14.V (1) Programming Voltage with Respect to Ground...-2.V to +14.V (1) Note: 1. Minimum voltage is -.6V DC, which may undershoot to -2.V for pulses of less than 2 ns. Maximum output pin voltage is Vcc +.75V DC, which may overshoot to 7.V for pulses of less than 2 ns. DC and AC Operating Conditions Commercial Operating Temperature (Ambient) C - 7 C V CC Power Supply 3.V to 5.5V 2

3 DC Characteristics Symbol Parameter Condition (2) Min Typ Max Units I IL Input or Low Leakage Current V IN V IL (Max) -1 µa I IH Input or High Leakage Current 1.8 V IN V CC 1 µa I CC1 (1) Power Supply Current 15 MHz, V CC = Max, V IN =, V CC, Outputs Open Com. Ind ma I PD (1) Power Supply Current, Power-down Mode V CC = Max, V IN =, V CC.1 5 µa I OS Output Short Circuit Current V OUT =.5V; V CC = 3V; T A = 25 C -15 ma V IL Input Low Voltage MIN < V CC < Max V V IH Input High Voltage 2. V CC + 1 V V OL Output Low Voltage V CC = Min; All Outputs I OL = 8 ma.5 V V OH Output High Voltage V CC = Min I OH = -4 ma 2.4 V I OL Output Low Current V CC = Min 8 ma I OH Output High Current V CC = Min -4 ma Note: 1. All I CC parameters measured with outputs open. 2. For DC characteristics, the test condition of V CC = Max corresponds to 3.6V. AC Waveforms (1) Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are.v and 3.V, unless otherwise specified. 3

4 AC Characteristics Symbol Parameter Min Max Min Max Units t PD Input or Feedback to Non-Registered Output ns t CF Clock to Feedback 5 8 ns t CO Clock to Output ns t S Input or Feedback Setup Time 7 12 ns t H Input Hold Time ns t P Clock Period ns t W Clock Width 6 8 ns f MAX Internal Feedback 1/(t S + t CF ) MHz External Feedback 1/(t S + t CO ) MHz No Feedback 1/(t P ) MHz t EA Input to Output Enable Product Term ns t ER Input to Output Disable Product Term ns t PZX OE pin to Output Enable ns t PXZ OE pin to Output Disable ns Power-down AC Characteristics (1)(2)(3) Symbol Parameter Min Max Min Max Units t IVDH Valid Input before PD High 1 15 ns t GVDH Valid OE before PD High ns t CVDH Valid Clock before PD High ns t DHIX Input Don't Care after PD High 1 15 ns t DHGX OE Don't Care after PD High 1 15 ns t DHCX Clock Don't Care after PD High 1 15 ns t DLIV PD Low to Valid Input 1 15 ns t DLGV PD Low to Valid OE 25 3 ns t DLCV PD Low to Valid Clock 25 3 ns t DLOV PD Low to Valid Output 3 35 ns Notes: 1. Output data is latched and held. 2. High-Z outputs remain High-Z. 3. Clock and input transitions are ignored. 4

5 Input Test Waveforms and Measurement Levels: t R, t F < 1.5ns (1% to 9%) Output Test Loads: Commercial R1 = 316 R2 = V OUTPUT PIN CL = 35 pf Note: Similar devices are tested with slightly different loads. These load differences may affect output signals delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible devices. Pin Capacitance (f = 1 MHz, T = 25 C) (1) Typ Max Units Conditions C IN 5 8 pf V IN = V C OUT 6 8 pf V OUT = V Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 1% tested. Power-up Reset The s registers are designed to reset during power-up. At a point delayed slightly from V CC crossing V RST, all registers will be reset to the low state. As a result, the registered output state will always be high on power-up. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the following conditions are required: 1. The V CC rise must be monotonic from below.7v. 2. The signals from which the clock is derived must remain stable during T PR. 3. After T PR, all input and feedback setup times must be met before driving the clock term high. Parameter Description Typ Max Units T PR Power-up Reset Time 6 1, ns V RST Power-up Reset Voltage V 5

6 ICC ma SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 3.3V, TA = 25 C) FREQUENCY (MHz) IOL ma OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25 C) OUTPUT VOLTAGE (V) ICC ma ALIZED SUPPLY CURRENT VS. AMBIENT TEMPERATURE (VCC = 3.3V, STANDBY) AMBIENT TEMPERATURE (C) ICC ma ALIZED SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25 C, STANDBY) SUPPLY VOLTAGE (V) IOL ma OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (TA = 25 C, VOL =.45V) SUPPLY VOLTAGE (V) IOH ma OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25 C) SUPPLY VOLTAGE (V) 6

7 IOH ma OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25 C) OUTPUT VOLTAGE (V) t CO ALIZED t CO VS. AMBIENT TEMPERATURE (VCC = 3.3V) AMBIENT TEMPERATURE (C) t PD ALIZED t PD VS. SUPPLY VOLTAGE (TA = 25 C) SUPPLY VOLTAGE (V) t S ALIZED t S VS. AMBIENT TEMPERATURE (VCC = 3.3V) AMBIENT TEMPERATURE (C) t PD ALIZED t PD VS. AMBIENT TEMPERATURE (VCC = 3.3V) AMBIENT TEMPERATURE (C) t H ALIZED t H VS. AMBIENT TEMPERATURE (VCC = 3.3V) AMBIENT TEMPERATURE (C) 7

8 t CO ALIZED t CO VS. SUPPLY VOLTAGE (TA = 25 C) SUPPLY VOLTAGE (V) INPUT CURRENT ma INPUT CLAMP CURRENT VS. INPUT VOLTAGE (TA = 25 C, VCC = 3.3V) INPUT VOLTAGE (V) t S ALIZED t S VS. SUPPLY VOLTAGE (TA = 25 C) SUPPLY VOLTAGE (V) INPUT CURRENT ma INPUT CURRENT VS. INPUT VOLTAGE (TA = 25 C, VCC = 3.3V) INPUT VOLTAGE (V) 1.2 ALIZED t H VS. SUPPLY VOLTAGE (TA = 25 C) 1. t H SUPPLY VOLTAGE (V) 8

9 Ordering Information t PD (ns) t S (ns) t CO (ns) Ordering Code Package Operation Range JC -1PC -1SC -1XC JC -15PC -15SC -15XC JI -1PI -1SI -1XI JI -15PI -15SI -15XI 2J 2P3 2S 2X 2J 2P3 2S 2X 2J 2P3 2S 2X 2J 2P3 2S 2X Commercial ( C to 7 C) Commercial ( C to 7 C) Industrial (-4 C to 85 C) Industrial (-4 C to 85 C) Green Package Options (Pb/Halide-free/RoHS Compliant) t PD (ns) t S (ns) t CO (ns) Ordering Code Package Operation Range JU -1SU -1XU 2J 2S 2X Industrial (-4 C to 85 C) Using C Product for Industrial To use commercial product for industrial temperature ranges, simply de-rate I CC by 15% on the C device. No speed de-rating is necessary. Package Type 2J 2P3 2S 2X 2-lead, Plastic J-leaded Chip Carrier (PLCC) 2-lead,.3" Wide, Plastic Dual Inline Package (PDIP) 2-lead,.3" Wide, Plastic Gull-wing Small Outline (SOIC) 2-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) 9

10 Packaging Information 2J PLCC 1.14(.45) X 45 PIN NO. 1 IDENTIFIER 1.14(.45) X (.125).191(.75) B e E1 E B1 D2/E2 D1 D A A2 A1.51(.2)MAX 45 MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-18, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is.1"(.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is.4" (.12 mm) maximum. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A A A2.58 D D Note 2 E E Note 2 D2/E B B e 1.27 TYP R 2325 Orchard Parkway San Jose, CA /4/1 TITLE DRAWING NO. REV. 2J, 2-lead, Plastic J-leaded Chip Carrier (PLCC) 2J B 1

11 2P3 PDIP D PIN 1 E1 A SEATING PLANE L e B1 B A1 Notes: C E eb 1. This package conforms to JEDEC reference MS-1, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed.25 mm (.1"). ec COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A A1.381 D Note 2 E E Note 2 B B L C eb ec e 2.54 TYP 1/23/4 R 2325 Orchard Parkway San Jose, CA TITLE 2P3, 2-lead (.3"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 2P3 REV. D 11

12 2S SOIC Dimensions in Millimeters and (Inches). Controlling dimension: Inches. JEDEC Standard MS-13.51(.2).33(.13) PIN 1 ID 7.6 (.2992) 7.4 (.2914) 1.65 (.419) 1. (.394) PIN (.5) BSC 13. (.5118) 12.6 (.4961) 2.65 (.143) 2.35 (.926).3(.118).1 (.4) º ~ 8º.32 (.125).23 (.91) 1.27 (.5).4 (.16) 1/23/3 R 2325 Orchard Parkway San Jose, CA TITLE 2S, 2-lead,.3" Body, Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 2S REV. B 12

13 2X TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AC PIN 1 INDEX MARK 4.5 (.177) 4.3 (.169) 6.5 (.256) 6.25 (.246) 6.6 (.26) 6.4 (.252) 1.2 (.47) MAX.65 (.256) BSC.3 (.12).19 (.7).15 (.6).5 (.2) SEATING PLANE º ~ 8º.2 (.8).9 (.4).75 (.3).45 (.18) 1/23/3 R 2325 Orchard Parkway San Jose, CA TITLE 2X, (Formerly 2T), 2-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 2X REV. C 13

14 Revision History Revision Level Revision Date H June 26 History Added Green package options. 14

15 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(48) Fax: 1(48) Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 8 CH-175 Fribourg Switzerland Tel: (41) Fax: (41) Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) Fax: (852) Japan 9F, Tonetsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo Japan Tel: (81) Fax: (81) Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(48) Fax: 1(48) Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(48) Fax: 1(48) La Chantrerie BP Nantes Cedex 3, France Tel: (33) Fax: (33) ASIC/ASSP/Smart Cards Zone Industrielle 1316 Rousset Cedex, France Tel: (33) Fax: (33) East Cheyenne Mtn. Blvd. Colorado Springs, CO 896, USA Tel: 1(719) Fax: 1(719) Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 QR, Scotland Tel: (44) Fax: (44) RF/Automotive Theresienstrasse 2 Postfach Heilbronn, Germany Tel: (49) Fax: (49) East Cheyenne Mtn. Blvd. Colorado Springs, CO 896, USA Tel: 1(719) Fax: 1(719) Biometrics/Imaging/Hi-Rel MPU/ High-Speed Converters/RF Datacom Avenue de Rochepleine BP Saint-Egreve Cedex, France Tel: (33) Fax: (33) Literature Requests Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 26 Atmel Corporation. All rights reserved. Atmel, logo and combinations thereof, Everywhere You Are and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 43H 6/6

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