Designing DC to DC Converters with DPA-Switch TM

Transcription

1 Designing DC to DC Converters with DPA-Switch TM 8-1 Covers watt, 24/48 VDC input applications

2 Agenda Introduction DPA-Switch Operation Basics Built-in Features User Configurable Features Designing with DPA-Switch Hints and Tips Application Examples Questions and Answers 8-2

3 Introduction 8-3

4 Company Overview Leader in high voltage monolithic power conversion ICs > One billion devices shipped Revolutionary products Proven quality and delivery performance Pioneer in energy efficiency (EcoSmart ) 8-4 Power Integrations was the world s first semiconductor company to introduce highly energy efficient power conversion ICs, based on its patented EcoSmart technology. TinySwitch received the 1999 Discover magazine award for the best technological innovation, in their ENVIRONMENT category, for its power saving EcoSmart features. 10% of the world s electrical energy is wasted by products that are in standby. EcoSmart technology practically eliminates standby waste.

5 Technology Leadership Integrated high-voltage, high frequency MOSFET Patented device structure Uses industry standard 3 µ CMOS process Widely available capacity 8-5

6 Discrete PWM Circuit Start-up Feedback Compensation PWM Controller Thermal Shutdown Oscillator High Voltage MOSFET Current Limit Gate Drive 8-6 Power Integrations ICs integrate the high-voltage MOSFET, PWM controller and: The MOSFET gate-drive circuit A high-voltage current source (start-up circuit) Loss-less DRAIN current sensing and limiting oscillator timing components feedback compensation Thermal protection

7 Equivalent Power Integrations Solution 20 to 50 components eliminated 8-7 The Newest PI product families also feature integrated functions such as: A 10 ms soft-start function A switching frequency dithering (jitter) function that lowers the annoyance factor of EMI and makes it easier for a design to reliably meet EMI specifications Line Under-Voltage (UV) lockout, Over Voltage (OV) shutdown and maximum duty-cycle reduction (DC MAX ) functions An auto-restart function that limits short-circuit and overload power delivery Externally programmable, loss-less DRAIN current limiting remote ON/OFF capability very low standby and no-load power consumption (PI s patented EcoSmart Technology)

8 Continuous Innovation TIME 8-8 Power Integrations continuously introduces innovative new power conversion ICs.

9 Cost Effective Over Wide Power Range DPA-Switch 0 W W LinkSwitch 0 W - 4 W TinySwitch-II TinySwitch 2 W - 20 W TOPSwitch -GX 10 W W Output Power (Watts) 8-9 Power Integrations ICs cost effectively cover: 95% of all AC-DC power supplies, within the range of under one watt to 250 watts LinkSwitch <1 W to 4 W TinySwitch-II 2 W to 20 W TOPSwitch-GX 10 W to 250 W 24/48 V DC-DC applications, within the range of under one watt to 100 watts DPA-Switch <1 W to 100 W This graph only approximates the power capabilities of each product family. For more accurate data, see the output power table on each product family data sheet.

10 Comprehensive Design Support Design Accelerator Kits Fully tested power supply Product samples Complete design documentation PI Expert design software Technical documents on website 8-10 Power Integrations has the most comprehensive design tools in the industry.

11 Global Applications Support Fully Equipped Applications Labs 8-11 Fully equipped PI applications labs are located worldwide: United States San Jose, California Chicago, Illinois Atlanta, Georgia Europe London, UK Munich, Germany Milano, Italy Asia Taipei, Taiwan Seoul, South Korea Shenzhen, PRC Shanghai, PRC Yokohama, Japan Bangalore, India

12 Wide Customer Acceptance 8-12 Many major OEMs worldwide use Power Integrations ICs in their products.

13 Introducing DPA-Switch The Industry s First Fully Integrated 220 V Monolithic Converter IC for Distributed Power Architectures 8-13

14 DPA-Switch Highlights Ideal for 24/48 V applications Wide input range: 16 VDC to 75 VDC Scalable: <1 W to 100 W Supports Forward, Flyback and Buck topologies Integrated 220 V, high-speed, power MOSFET + control circuitry Programmable loss-less current sensing and limiting Accurate input UV/OV detection Overload, open loop, and thermal fault protection Synchronous or diode rectification (300/400 khz) Maximum 75% duty cycle wide input range & high efficiency Integrated high-voltage startup current source Soft-start minimizes component stress and output overshoot 8-14

15 Shrinking the Footprint of Power 70 components 37 components 30 W discrete solution 30 W DPA-Switch solution 8-15 On the left is a commercially available, single sided, one board, DC/DC converter Converters with double sided component placement and multiple PCBs may look smaller, but their component count remains very high The DPA-Switch based converter on the right is also a one board, single sided unit

16 DPA-Switch Applications Telecom and network infrastructure/poe DC-DC Converters Servers Automotive Industrial controls Digital PABX/VoIP phones 8-16 DPA-Switch can cost effectively provide power solutions for a wide range of products and applications

17 DPA-Switch Operation 8-17 Seminar_DPA_100102_screen_102102

18 Basics 8-18

19 DPA-Switch Basics CONTROL pin characteristic DPA-Switch supply I C DPA-Switch is a current to duty-cycle converter Current into the CONTROL pin reduces the PWM duty-cycle 8-19 The CONTROL pin is a combined supply and feedback input. Once the supply current (grey area in the above graph) for the IC has been exceeded, the more the feedback current increases, the more the internal MOSFET duty cycle is reduced DPA-Switch is based on the proven TOPSwitch technology Similar to the TOPSwitch-GX in function, the 220 V MOSFET is optimized for higher switching frequencies (300/400 khz) Fixed-frequency, voltage-mode control (duty-cycle, not current-limit controlled) Voltage mode control allows >50% duty cycle without requiring slope compensation Maximum duty cycle can be reduced, as V IN increases, preventing transformer saturation at high line (see the Built-in Features section)

20 Start-up: Charging CONTROL Pin Capacitor The CONTROL pin capacitor is charged to 5.8 V, by a high-voltage current source (from the DRAIN pin) No external start-up resistor is required CONTROL pin capacitor (68 µf typical) 8-20 The charging current is only about 4 ma, and the di/dt is zero once 5.8 V is reached. Therefore, this charging current does not affect (raise) the output voltage

21 Start-up: Drain Starts Switching Output voltage starts rising When the CONTROL pin reaches 5.8 V, MOSFET switching (soft)starts, with gradually increasing duty-cycle & current limit The CONTROL pin capacitor is recharged (during the MOSFET off times), by the highvoltage current source, to maintain 5.8 V during the soft-start period 8-21

22 Output Reaches Regulation I C The opto turns on when the output voltage value reaches regulation, closing the feedback loop The DPA-Switch now receives current from the bias winding, and its internal high-voltage current source has been disabled. CONTROL pin current in excess of the supply current is used as feedback, to keep the output in regulation. 8-22

23 Start-up Control Pin Waveform Soft-start output voltage rises Charging the CONTROL pin Output in regulation, DPA-Switch powered from the bias winding 8-23 CONTROL & DRAIN pin start-up waveforms: normal load conditions At start-up, the internal high-voltage current source charges the CONTROL pin capacitor to 5.8 V At 5.8 V, MOSFET switching begins, in the soft-start mode The output voltage rises and reaches the regulation value and the opto turns on, driving current into the CONTROL pin The IC adjusts the duty cycle, based on the CONTROL pin current, maintaining output regulation The CONTROL pin voltage is set by an internal shunt regulator, making it a current driven input. Any in-circuit testing performed at incoming inspection must limit the current supplied to the CONTROL pin to the range specified in the device data sheet, which also has recommended test circuits.

24 Auto-restart: Overload/Open Loop Protection Soft-start period If no feedback current is received before the CONTROL pin discharges to 4.8 V, an auto-restart sequence starts 8-24 CONTROL & DRAIN pin start-up waveforms: overload/open loop fault conditions If the CONTROL pin receives no current from the opto, by the end of the soft-start period (when the internal high-voltage current source is disabled), the CONTROL pin capacitor begins to discharge When the CONTROL pin capacitor has discharged to 4.8 V, the MOSFET is disabled and the CONTROL pin capacitor is charged and allowed to discharge, for 7 cycles The MOSFET is again enabled, after the 7th charge/discharge cycle, and the IC initiates the soft-start function again If the CONTROL pin receives no current from the opto, by the end of the soft-start period, the entire sequence repeats again Overload/open loop protection is very well defined It does not rely on the loss of the bias winding supply voltage Any time output regulation is lost, the opto turns off, the CONTROL pin capacitor discharges to 4.8 V, and the auto-restart function is initiated

25 Built-in Features 8-25 These features do not require external components

26 DPA-Switch Loss-less Current Sense R DS(ON) is used as the current sense resistor No sense resistor is needed (no extra I 2 R losses incurred) No expensive current sense transformer is needed Trimmed to ±7% accuracy Temperature compensated R REF tracks R DS(ON) temperature Built-in leading edge blanking Filters turn-on spikes without requiring external components Allows very fast current limit 8-26 The Leading Edge Blanking (LEB) feature (not shown) eliminates the need for low pass filter components on the input of the current limit comparator This allows very fast current limiting: turns off the MOSFET in about 100 ns The current limit comparator is only connected to the DRAIN when the MOSFET is on. When the MOSFET is off, the comparator is disconnected from the DRAIN

27 DPA-Switch vs Discrete Sense Resistor Effectively increases resistance by up to 150% (R DS(ON) + R SENSE ) Adds to conduction losses Higher cost Layout is more difficult Additional components PARAMETER SENSE RESISTOR DPA424 I LIMIT */Selected 2.0 A 2.0 A R SENSE 0.25 Ω 0 Ω R DS(ON) 0.75 Ω 0.75 Ω Effective Resistance 1.00 Ω 0.75 Ω PI * - Assumes 0.5 V I SENSE voltage Threshold 8-27 A discrete implementation requires a low pass noise filter, to keep the turn-on noise spike from prematurely tripping the comparator. This increases both the turn-off delay time and the minimum on-time of the MOSFET To match the equivalent effective resistance of the DPA-Switch (in the above example) the discrete MOSFET would need to have 33% lower R DS(ON)!

28 DPA-Switch vs Current Sense Transformer Current sense transformer disadvantages Very high cost Require more board space Require many additional components Additional current sense transformer components 8-28 Current sense transformers are typically used in discrete converters of 25 watts DPA-Switch totally eliminates current sense transformers, at any power level

29 Discrete vs DPA-Switch Losses DEVICE R DS(ON) (Ω) D MAX AT 48 VDC (%) FREQ (khz) TURN ON LOSS (mw) CONDUCTION LOSS (mw) TURN OFF LOSS (mw) TOTAL LOSS (P ON + P COND + P OFF ) (mw) IRFR IRF640NS IRF634S DPA DPA PI IRF640NS vs DPA425 half the R DS(ON) but twice the switching losses, even at a lower switching frequency IRFR220 vs DPA424 lower R DS(ON) but higher overall losses (due to lower duty cycle and higher rms currents than the DPA424) DPA425 lowest overall loss, for a 30 W design 8-29 Three commercially available 30 W DC/DC converters were measured and compared to DPA-Switch performance, at the same power levels R DS(ON) alone is not a good measure of switching efficiency

30 The Goal is Efficiency not just low R DS(ON) Measured loss per switching cycle: DPA-Switch vs Discrete Energy Loss (µj) DPA424 Supply, 48 V, 30 W R DS(ON) = 0.75 Ω Turn off loss Conduction loss Turn on loss Time (µs) IRF640NS Supply, 48 V, 30 W R DS(ON) = 0.15 Ω Turn off loss Conduction loss Turn on loss Time (µs) PI MOSFET technology has extremely low switching losses, enabling higher efficiency designs even with > 4 times the R DS(ON) of a discrete 8-30 Measurements were made on an EP-21 (DPA424) and a commercially available IRF640NS based, 30 W DC/DC converter, at the same power rating The IRF640NS based converter had 600% higher turn off losses than the DPA-Switch converter. A direct comparison of conduction losses was not possible, since the solutions operate at different switching frequencies (400 khz vs 277 khz) and have different primary current waveforms

31 Fully Integrated 5 ms Soft-start Function Duty cycle and DRAIN current limit are ramped up, during this period Soft-start is reinitiated after the removal of an overload or a thermal fault Benefits Reduces start-up component stresses Helps avoid core saturation during start-up Minimizes start-up overshoot 78% Duty Cycle Loop closed No soft-finish capacitor Internal DC MAX Limit Loop closed With soft-finish capacitor 5 ms Final operating Duty Cycle Time 8-31 DC MAX : Maximum Duty-Cycle For an output voltage > 5 V, a soft-finish capacitor is usually not required. However, the effects of a soft-finish capacitor are described on the next slide

32 Soft-finish: Eliminates Output Overshoot Soft-start improves but does not eliminate output overshoot Overshoot can be completely eliminated by using a soft-finish capacitor (C13) When output voltage rises to LED + diode drop, the soft-finish capacitor forces current through the opto, closing the loop 1 V/div Output rises in closed loop, preventing overshoot, from that point forward Modify value of C13 to adjust output voltage rise time V OUT 5 ms/div 8-32 R7 discharges C13 at turn off, resetting the soft-finish function D3 isolates C13 from the main control loop, once it has been fully charged by R7, to prevent C13 from influencing the control loop response NOTE: The initial step in V OUT is due to a fixed, 2 ms, minimum duty cycle period, that must elapse before the soft-start circuit begins ramping up the duty cycle

33 Hysteretic Thermal Shutdown Protection On-chip MOSFET temperature sensing provides robust protection Protects the entire system: the IC, the PC board and the magnetic components PARAMETER VALUE Shutdown (t OFF ) 137 C ± 5% Hysteresis 27 C PI

34 Discrete Source Connected Tab Improves EMI Capacitively coupled substrate current (I SUB ) causes common mode EMI DPA-Switch For DPA-Switch I SUB = 0, low common mode EMI 8-34 The Drain of discrete MOSFETs are connected to their package tabs, which makes them radiate switching noise The DPA-Switch package tab is connected to the Source of its MOSFET, leaving it electrically quiet (a fundamental advantage of the PI lateral, high-voltage process)

35 Temperature Compensated Critical Parameters Current Limit Frequency Tolerance at 25 C MIN TYP MAX Tolerance at 25 C MIN TYP MAX I LIMIT (DPA423) % +7% PI FREQUENCY % +7% PI All critical parameters are temperature compensated and trimmed during testing, for high accuracy Easier to design for high volume manufacturing

36 Cycle Skipping Operation As load CONTROL pin current Duty cycle At light load, cycle skipping starts as the CONTROL pin current increases (beyond minimum duty cycle) Retains output regulation at light/no-load Reduces standby consumption (EcoSmart) 8-36 Minimum duty cycle is typically 4%. Therefore, cycle skipping only occurs at very light loads A small output pre-load (typically < 0.5% of full load) can prevent cycle skipping

37 Built-in Features - Summary FEATURE Lossless current sense High speed MOSFET Soft-start Auto-restart Thermal shutdown High maximum duty cycle (75%) BENEFIT Lower conduction losses Dramatically lower switching losses Prevents transformer saturation / reduces component stresses Very well defined overload/open-loop protection Provides system level thermal protection High efficiency & wide input range with no slope compensation components required (voltage mode control) PI Voltage-mode control-loop response: the output voltage typically settles < 200 µs of a step-load change - See Application Examples, section EP-21, load step response

38 Built-in Features - Summary FEATURE Internal high voltage start-up current source Tab connected to Source Tight tolerance over temperature on all critical parameters Cycle skipping (EcoSmart) Industrial temperature range Pin removed from package BENEFIT Increased efficiency/lower power loss No external startup resistor Low EMI Improved design margin for high volume production Energy efficient no-load regulation Addresses all markets Wider creepage/clearance PI

39 User Configurable Features 8-39

40 Single Resistor (R IL ) Sets Loss-less Current Limit 86% using 8.25 kω 64% using 12 kω 34% using 25 kω Note: R IL > 35 kω can trigger remote OFF 8-40 The DPA-Switch is a voltage-mode controlled device The current limit is typically set lower than the default, to limit overload power delivery The max & min limits shown include both device-to-device & temperature tolerances An externally programmed current limit is still loss-less Resistor values greater than 35 kω are not recommended

41 R IL Sets Output Overload Power Limit I LIMIT = 100 % R IL = 0 Ω 500 ns/div I DRAIN Overload = 8.5 A out Max load = 6.0 A out I LIMIT = 86 % R IL = 8.25 kω time 500 ns/div I DRAIN R IL sets I LIMIT Overload = 7.0 A out time Max load = 6.0 A out 8-41 In the example shown, the value of R IL chosen reduces overload current by 20% Allows lower cost rectifiers, chokes and capacitors to be used, without reducing reliability The above measurements were taken on the EP-21 unit Sensing and adjusting the current limit can take up to 6 external components, when implemented with discrete components Leading edge blanking prevents the initial current spike from triggering the current limit function

42 Single Resistor (R LS ) Sets Input UV/OV UV hysteresis meet ETSI standard Fixed UV/OV ratio of 1 : 2.7 Extra components allow independent adjustment UV, OV or both can be disabled R LS = V IN(UV) I UV V V ( L = 2.35 V I UV = 50 µa ) L 8-42 Line under-voltage (for the example shown in the slide) As the input voltage increases, the supply will turn on at about 33.4 V As the input voltage decreases, the supply will turn off at about 31.5 V As the input voltage decreases, if regulation is lost before 31.5 V, the input must increase back up to 33.4 V, for the supply to turn on again Line overvoltage (for the example shown in the slide) As the input voltage increases, the supply will turn off at about 86.0 V As the input voltage decreases, the supply will turn back on at about 83.5 V The Magnetics Design Spreadsheet assists in choosing a value of R LS, for a specified pair of UV/OV set-points (see Designing with DPA-Switch) R LS also actuates the DC MAX reduction function described on the next slide When the L pin current reaches 50 µa, operation is enabled. When it reaches 135 µa, operation is disabled. With a 619 kω resistor, this corresponds to input voltages of 33.4 V and 86 V respectively. There is hysteresis on both set-points As shown above, the supply would start operating before V IN reached 36 V

43 R LS Also Programs DC MAX Reduction As V IN (and L pin current) increases, maximum duty cycle is reduced Extends transformer reset time as V IN increases Prevents forward converter transformer saturation 8-43 The DC MAX reduction function was designed to correlate with the requirements that a typical Forward converter would have, for a given value of R LS and UV/OV set-points It is recommended that an R LS resistor be included in all Forward converter designs If R LS is not used, DC MAX stays at the maximum value, for all input voltages. This may be acceptable in low voltage applications (18 to 36 V), but transient load tests should be performed at max V IN, to verify that the transformer does not saturate Since the DPA-Switch is voltage-mode controlled, no slope compensation components are required to maintain loop stability at >50% duty cycle

44 Temperature Compensated UV/OV Thresholds Undervoltage Threshold Overvoltage Threshold Tolerance at 25 C MIN TYP MAX Tolerance at 25 C MIN TYP MAX I UV (ON to OFF) I UV (OFF to ON) % +5.5% PI I OV (ON to OFF) I OV (OFF to ON) % +10% PI The UV threshold is more tightly specified than the OV threshold is, to meet ETSI requirements

45 Adjusting the UV/OV ratio The UV/OV ratio is fixed at 1 : 2.7 The ratio can be modified by making the L pin current nonlinear with VIN Zener diode V Z modifies the linearity of the L pin current with VIN The data sheet shows many other L pin configurations, including ways to disable the UV or OV functions individually R LS sets V IN(UV) (V z > V IN(UV) ) V Z, R 1 and R LS set V IN(OV) 8-45

46 Selecting Switching Frequency 400 khz 300 khz Smallest magnetics Optimum for diode rectification Lower switching losses More reset time for transformer Optimum for sync. rectification Note: The F pin should not be left open 8-46 In a discrete design, adjusting frequency can take 3 or more external components

47 Remote ON/OFF Configurations INPUT VOLTAGE 36 V 48 V 72 V Remote OFF Input Power 36 mw 48 mw 72 mw PI (1) Active ON (2) Active OFF The data sheet shows many other configurations 8-47 In a discrete design, equivalent functionality can take up to 7 components

48 Synchronization: Non-Isolated Free Running When the L-pin goes above 1 V, the oscillator stops at the end of the cycle If the L pin is left floating, the internal 170 µa pull-up to 1.5 V stops the oscillator When the L-pin is pulled below 1 V, the oscillator restarts a new cycle R2 turns Q1 on at start-up, allowing the DPA-Switch to free run The R2-C1 time constant should be much greater than the maximum sync off time C1 couples the sync pulse to the gate of Q The oscillator can only be synchronized to lower frequencies The oscillator stops and starts according to the sync pulses, therefore only frequencies below that of the internal oscillator frequency can be synchronized to When the L pin is used for synchronization, it cannot also be used for UV/OV D1 clamps the Q1-gate, ensuring that the falling edge of the sync pulse turns Q1 off The maximum turn-on delay, following the sync signal, is 250 ns If free running start-up is not required, R2 can be eliminated. Then Q1 will be off until the sync pulses arrive. D1 should then be connected with its anode to the source of Q1 and its cathode to the gate of Q1, to reset C1 every time the sync pulse goes low The internal L pin, pull-up current source (170 µa) is disabled at approximately 1.5 V, to avoid pulling the L pin up into its UV/OV threshold operating range

49 Synchronization: Isolated Free Running Pulse transformer Note: opto-couplers are too slow for synchronization 8-49 Isolation is provided by the pulse transformer Again, R2 provides free running operation, if the sync pulses are not present Again, how D1 is connected depends on whether free running operation is desired or not

50 Synchronization Considerations SWITCH FREQUENCY PRACTICAL SYNC RANGE 300 khz 300 khz to 180 khz 400 khz 400 khz to 300 khz PI DC MAX can effectively limit the maximum power capability of a solution, if its switching is synchronized at a lower frequency DC MAX is defined at full frequency; lower frequencies add dead-time Therefore, lower switching frequencies effectively reduce the DC MAX DC MAX(EFF) = 0.75 f SYNC /f OSC The UV/OV function is not available when externally synchronized When slaved to a master DPA-Switch, the UV/OV on the master can be used 8-50 To take advantage of the maximize power capability of the DPA-Switch, use the lowest internal oscillator frequency that can be synchronized to, to obtain the highest DC MAX possible (the DC MAX at 300 khz > the DC MAX at 400 khz)

51 Synchronization Timing Requirements t on(sync) must be >120 ns to ensure it is recognized as an ON command t off(sync) >7700 ns can be interpreted as a remote off condition, triggering soft-start when re-enabled 8-51

52 Other X-pin and L-pin Configurations Many other configurations possible See DPA-Switch data sheet 8-52

53 User Configurable Features Summary DESCRIPTION PIN BENEFITS Programmable lossless current limit X-pin Replaces/eliminates current transformer or power resistor Accurate UV/OV L-pin Single resistor programming DC MAX reduction L-pin Prevents transformer saturation Selectable switching frequency Remote ON/OFF F-pin L-pin/X-pin 300 khz for sync rectification 400 khz for diode rectification Low parts count and low standby power Synchronization L-pin Allows sync to lower frequency PI Three DPA-Switch pins have user configurable functions associated with them: The X pin allows the drain current limit to be programmed lower than the default value The L pin sets the UV/OV thresholds and reduces the maximum duty cycle as VIN increases The L pin also allows external synchronization to a lower frequency Either the L pin or the X pin can be used for remote ON/OFF control

54 Disabling User Configurable Features Features on user configurable pins can be disabled by connecting those pins to SOURCE Built-in features work even when used in three terminal mode Three terminal operation 8-54 The built-in features only require the three standard DPA-Switch terminals, DRAIN, SOURCE, and CONTROL, and no external components The functions on the other pins are disabled by connecting the pin to SOURCE

55 DPA-Switch Block Diagram Accurate programmable loss-less current limit Internal soft-start No external components Switched, high-voltage, Startup Current Source 1V threshold for ext. sync. Auto-restart for short circuit protection Accurate OV/UV line sense Loss-less current sense Accurate 300/400 khz clock High Speed 220 V MOSFET Cycle skipping, for no load regulation (EcoSmart) Thermal shutdown 8-55 This diagram shows the various functional blocks within the DPA-Switch, which were covered in detail, in the Built-in and User Configurable Features sections The DPA-Switch provides the highest level of integration by incorporating practically all primary side functions within a single monolithic device

56 DPA-Switch Features Reduce Component Count Discrete DC-DC supply Color coded functional blocks DPA-Switch DC-DC supply Color coded functional blocks 8-56

57 DPA-Switch Features Reduce Component Count DESCRIPTION # OF PARTS REDUCED COMMENT Accurate OV/UV up to 11 Thermal protection up to 4 Current sense using R DS(ON) up to 6 Temperature stable Single resistor Directly senses MOSFET temperature Hysteretic/self-resetting No sense power resistor, no current sense transformer Tight tolerance & temperature compensation Fixed accurate switch frequency up to 3 Tight tolerance & temperature stable Selectable 300 khz or 400 khz High voltage start-up up to 4 Integrated high voltage start-up Integrated soft-start PI These component savings were observed from comparisons with commercially available DC/DC converters

58 DPA-Switch Features Reduce Component Count DESCRIPTION # OF PARTS REDUCED COMMENT Source connected tab - Voltage mode control up to 5 Remote off (primary side) up to 7 Heatsink connected to source (tab) Reduced EMI Allows >50% duty cycle without slope compensation DPA-Switch implements with transistor and two resistors Controller and discrete components MOSFET & drive components TOTAL COMPONENT SAVING WITH DPA-Switch up to 6 up to 4 up to 50 Integrated DPA-Switch features save external components Integrated DPA-Switch MOSFET PI These component savings were observed from comparisons with commercially available DC/DC converters Component placement and assembly cost savings should also be considered in a full cost comparison

59 Designing with DPA-Switch 8-59

60 Flyback vs Forward Flyback Lowest cost solution for output currents < ~ 6 Amps Advantages: simple circuit - no output energy storage choke required Disadvantages: higher output ripple current - higher output capacitor costs Forward Lowest cost solution for output currents > ~ 6 Amps Advantages: low output ripple - lower cost output capacitors Disadvantages: more complex circuit - output energy storage choke required 8-60 Although a Flyback converter may also use an output choke, it is being used to filter high frequency noise, not store significant energy. Therefore, the output chokes used in Flybacks are very low inductance

61 Flyback basics When switch is on, primary current ramps up storing energy in transformer When switch is off, the stored energy is transferred to the output The clamp circuit limits the transformer leakage inductance spike 8-61

62 Flyback Design Process Use the Step by step Flyback design methodology in AN-32 AN-32 was written to support AC/DC designs with TOPSwitch-GX The DPA-Switch Flyback procedure is identical, other than: No input storage capacitance calculation Lower V OR choice, typically 30 to 40 Volts Clamp chosen appropriate to 220 V BV DSS - a single 130 V Zener from drain to source is adequate for most designs (see DI-29) Use V DS of 2.5 V: lower R DS(ON) and current limit threshold voltage Transformer manufacturer s core data for 300/400 khz operation Output capacitors: use tantalums for lowest impedance at high frequency Select feedback components according to the DI-29 reference circuit Use the DPA-Switch Flyback spreadsheet in PI-Expert, to design the transformer 8-62 Since Flyback design is similar to previous PI products, it will not be covered in detail here. Forward converter design is covered in detail, later in the presentation A full Flyback design methodology is available in AN-32 (with the differences listed above). However, the spreadsheet provided in PI-Expert automates this process, incorporating all of the above noted changes

63 Flyback Transformer Design Using Spreadsheet The DPA-Switch Flyback Design Spreadsheet is part of PI Expert USER INPUTS Specifications: V IN range Output Voltage(s) Total P OUT Core Choice* Design Variables: DPA-Switch Reflected Voltage Secondary turns SPREADSHEET OUTPUTS Primary inductance and primary/bias turns L and X pin resistor recommended values Core flux density recommends different core if necessary Output ripple current for output capacitor choice Output current/max reverse voltage for output diode choice PI-3344b * Database contains parameters for popular DC/DC core types: EFD, RM, PQ, EPC, PR, ER and ELP (planar) 8-63

64 Quick Design Checklist for Flyback Maximum drain voltage Verify that peak drain voltage <80-90% BV DSS, under the worst case conditions (typically high line and output overload) Drain current at maximum input voltage, load and ambient temperature Check for transformer saturation at start-up and under steady state conditions Leading edge current spikes must be within DPA-Switch current limit envelope Thermal Verify that key component temperatures are within limits at maximum load, maximum ambient temperature and minimum input voltage DPA-Switch, transformer, output diodes and output capacitors The recommended maximum DPA-Switch source pin/tab temperature is 110 C See manufacturer specifications for the temperature limits of other components 8-64 Typically, 25 V of additional drain-voltage margin is recommended, to allow for the unit-to-unit tolerances of other components Maximum overload power will be demanded from the converter, when the output is loaded to just before auto-restart occurs (when output regulation is lost) At a minimum, a design must pass these three tests, before it can be considered production worthy

65 Quick Design Checklist - Drain Current Waveform Check that the current waveform is within the recommended limits Leading edge current spike 100 ns Designs with core saturation not recommended After leading edge blanking time (t LEB =100 ns) drain current should be below current limit envelope characteristic t LEB 8-65

66 Forward Basics: Energy Delivery K I = I I O t (a) Switch ON: I L ramps up, delivering energy to inductor L and output (b) Switch OFF: I L ramps down continuing energy delivery to output Energy delivered during on and off time - more efficient than flyback 8-66 K I is a term used in PI Expert, which is defined as the quotient of inductor ripple current divided by the DC output current - typical values are between 0.15 to 0.20

67 Forward Basics: Transfer Function N P : N S NS V = V D O IN N Step down Average D = DPA-Switch duty cycle P Forward converter is a step down transformer followed by a buck converter which averages the transformer output voltage waveform 8-67

68 Forward Basics: Transformer Reset The practical transformer has finite magnetizing inductance Flux builds up in the magnetizing inductance when the switch is on Flux is reset each cycle, by the reset circuit, to prevent core saturation (V RESET t OFF ) (V IN t ON ) to reset flux and prevent transformer saturation 8-68 The magnetic flux, which is built up in one direction (V IN xt ON ), is reset by an equal and opposite Volt-second area (V RESET xt RESET ) The transformer should also be designed to prevent excessive peak flux, within the on-time (t ON ) of each switch-cycle. Excessive peak flux can cause transformer saturation

69 Step by Step Forward Design Process 1. Define the system requirements 2. Choose the DPA-Switch biasing technique 3. Magnetics design and DPA-Switch Selection 4. Clamp and reset circuit selection 5. Output capacitor selection 6. Feedback design See Application Note AN-31 for full details 8-69

70 Step 1: Define System Requirements Input voltage range Define the UV/OV thresholds [33.5 V is the typical UVLO threshold, for VDC designs (assures 36 V start-up, including the L pin tolerances)] Output characteristics Most regulation spec.s require a temperature compensated reference (TL431) Define output ripple requirements: influences output inductor and capacitor choices Efficiency target High efficiency designs (>85%) typically require synchronous rectification Other designs can use Schottky diodes - lower cost Choice of rectification technique influences the transformer design Operating Temperature range Influences the choice of the output capacitors and of the DPA-Switch device, plus the design and testing of the control loop 8-70 PI Expert calculates the L pin resistor value, for the desired input voltage range

71 Step 2: Choose DPA-Switch Biasing Technique Three techniques are available BIAS TYPE INPUT VOLTAGE EFFICIENCY COMPLEXITY LIMITS OF USE DC Input Derived V Low Low Max bias limited by Opto/Zener dissipation Forward Transformer bias winding Any Medium Medium Max bias limited by Opto dissipation Bias voltage proportional to input voltage Output coupled inductor Any High High May require minimum load PI NOTE: Overload protection is not influenced by the bias technique. The DPA-Switch auto-restart function is activated when feedback current (not bias voltage) is lost The following slides describe each of the three bias techniques

72 Step 2: Bias Circuits: DC Input Derived Very Simple - no additional windings Limited by opto and zener losses Zener reduces dissipation in opto Minimum opto collector voltage for correct operation is 8 V Typically only for VDC inputs DEVICE DPA423 DPA424 DPA425 DPA426 PI I C(SKIP) 9 ma 10 ma 12 ma 14 ma Maximum feedback current required (I C(SKIP) ) depends on device 8-72 I C(skip) is the highest DPA-Switch control current required. Therefore, it is the worst-case loss condition for both the opto-coupler and the Zener diode

73 Step 2: Bias Circuits: Forward Winding P OPTO = (VBIAS VC ) I C(skip) ) Winding on transformer Lower dissipation than DC input derived Bias voltage of at least 8 V required at minimum DC input Bias voltage changes directly with input voltage Flyback winding not recommended Affects transformer reset 8-73 With this technique, the bias voltage and opto dissipation vary with the input voltage If a Flyback winding were used, the large bias capacitor would clamp the drain voltage, limiting the reset voltage

74 Step 2: Bias Circuits: Coupled Inductor Winding A Flyback winding on the output inductor The most efficient, due to unvarying opto feed voltage A small preload may be required to keep bias in regulation at no-load (if no-load is required) Sufficient current through the output inductor is required to maintain bias for the DPA-Switch (see DI-24) 8-74

75 Step 3: Magnetics Design/DPA-Switch Selection Performed by PI Expert USER INPUTS Specifications: V IN range Output Voltage(s) Output Current(s) Design Variables: DPA-Switch Switching Frequency Rectification Type (Sync/Diode) SPREADSHEET OUTPUTS Primary inductance and primary turns Output choke inductance/bias winding turns ratio DPA-Switch D MAX /I PEAK /I RMS L and X pin recommended resistor values Core flux density recommends different core if necessary Output ripple current for output capacitor choice Output Average current/max reverse voltage for choice of output rectifiers PI The design database contains parameters for popular DC/DC core types: EFD, RM, PQ, EPC, PR, ER and ELP (planar) 8-75 PI Expert assumes that a coupled output inductor bias winding will be used. However, other bias techniques may be selected

76 Step 3: Magnetics Design/DPA-Switch Selection PI Expert chooses the smallest DPA-Switch for the peak power required The power table allows the efficiency of a larger device to be estimated OUTPUT POWER TABLE 48/60 V (36 75 VDC) INPUT RANGE Total Device Dissipation PRODUCT 0.5 W 1 W 2.5 W 4 W 6 W Max Power Output DPA423R 12 W 16 W W DPA424R 16 W 23 W 35 W W DPA425R 23 W 32 W 50 W 62 W - 70 W DPA426R 25 W 35 W 55 W 70 W 83 W 100 W PI Example: In a 23 W output design, the DPA424 will dissipate 1 W, worst-case, versus 0.5 W for the DPA PI Expert will choose the smallest DPA-Switch, that has sufficient power capability, for the lowest cost design. A device one size larger can be chosen, for higher efficiency (see Hints & Tips section) The data sheet provides the assumptions that were made, in generating the power table dissipation estimates The data sheet also provides power tables for other input voltage ranges (16-32 VDC and VDC) The table above shows worst case dissipation for a 5 V Forward converter, with Schottky diode rectification (based on assumptions from the datasheet) The power capability depends on the allowable dissipation and/or the efficiency of the converter. The maximum power output is limited by the internal current limit

77 Step 4: Clamp and Reset Circuit for P O <40 W C S is the main reset capacitor. It captures the magnetizing energy when the switch first turns off, then returns it to the core, as negative flux, during the Relaxation Ring part of the switching cycle (t RN ). R S (typically 1 Ω) dampens oscillations. A minimum value of C CP is used to clamp primary leakage inductance during normal operation. Zener only clamps during transients and fault conditions. See AN-31 page 6 Typical values shown 8-77 The advantage of this reset scheme is that the energy in C S is recovered and transferred to the output during next switch-on cycle, increasing efficiency. The minimum value to guarantee worst-case reset should be selected (see next slide) In contrast, the energy in C CP is lost. Therefore, only a minimum value of C CP should be used to clamp the leakage inductance spike C CP may not be required in low power designs C S may not be required in synchronous rectification designs, due to MOSFET gate capacitance performing the same function NOTE: AN-31 page numbers refer to the pages of the stand-alone document

78 Step 4: Selecting C S value using Drain Waveforms Acceptable Drain voltage waveform V/div Reset voltage beyond recommended levels. Reset capacitor (C S ) too small Insufficient reset time. Reset capacitor (C S ) too large T s - switching period t on - MOSFET on time t RZ - reset of magnetizing flux to zero t RN - relaxation ring (negative flux) t VO - clamped by forward output diode 8-78 The reset voltage should be designed to be below VR1 s voltage rating If Cs is too large: The drain waveform does not flatten out, indicating that the magnetizing flux is still positive (the transformer has not been fully reset) Verify drain waveforms at both the lowest and the highest input voltages

79 Step 4: Resonant Reset Circuit for P O >40 W At high power levels, this technique allows re-circulation of both magnetizing and leakage energy Resonant L 1 /C 1 period must be shorter than minimum DPA-Switch conduction time (1 to 1.5 µs, for one LC half-cycle) More complicated and expensive than the simple Zener/Capacitor scheme See AN-31, page 7, for typical component values 8-79 At DPA-Switch turn-off, any energy previously stored in C 1 is delivered to output inductor When V 1 exceeds V IN, D 2 clamps to V IN, and C 1 charges with energy from the leakage and magnetizing inductances During the remaining off time, the drain voltage will relax to V IN. C 1 will retain its peak voltage value of V DS(PK) V IN, unless V DS(PK) V IN is > V IN, in which case D 1 will conduct, clamping the voltage across C 1 to V IN When the DPA-Switch turns on, V 1 drops by a delta voltage equal to V IN and goes negative C 1 recharges via the DPA-Switch MOSFET, diode D 1 and inductor L 1 and raises the voltage V 1 to an equivalent positive voltage At the DPA-Switch turn-off, the voltage transition V DS causes D 2 to conduct again, transferring the energy stored in C 1 to the output inductor Resonant current through the DPA-Switch does increase the device losses. However, the clamp losses are recovered NOTE: AN-31 page numbers refer to the pages of the stand-alone document

80 Step 5: Output Capacitor Selection Select low enough ESR to meet output voltage ripple specifications Tantalum type normally chosen (for low impedance at high frequencies) Select capacitance value to provide a 4-6 khz pole with output inductor See step 6: Feedback design Test control loop stability at extremes of specified temperature range Capacitor parameters change with temperature, and can influence loop behavior See AN-31, page 9, for details 8-80 NOTE: AN-31 page numbers refer to the pages of the stand-alone document

81 Step 6: Feedback Design - Output LC Filter The resonant frequency of the typical LC filter is between 4-6 khz (f) This range is typical of the values required for voltage and current ripple Use L2 value from Step 3: Magnetics Design Calculate the required amount of output capacitance C10 + C11= 1 ( ) 2 L2 2 π f See AN-31, page V output shown (4-6 khz is typical of a 5 V output). The LC resonant frequency will typically be higher at lower output voltages NOTE: AN-31 page numbers refer to the pages of the stand-alone document

82 Step 6: Feedback DPA-Switch Compensation C6, R4 and CONTROL pin impedance introduce one pole and one zero in the converter frequency response C6: choose 47 µf to 100 µf Low ESR recommended: reduces effect of ESR change with temperature on the loop R4: Typically 1 Ω Locate high frequency bypass capacitor (C5) close to the CONTROL pin 0.22 µf typical value (has negligible influence on loop response) Follow layout guidelines to keep switching noise out of the loop See AN-31, page 11, for details 8-82 The CONTROL pin impedance is typically 15 Ω (see datasheet, Z C parameter) NOTE: AN-31 page numbers refer to the pages of the stand-alone document

83 Step 6: Feedback Design - Opto Compensation Low cost % CTR opto Provides required CONTROL pin drive and loop gain in most designs R6 must allow adequate CONTROL pin current Check maximum current required (I C(SKIP) in datasheet) The Phase boost zero (R12, C16) counters the LC output filter double pole Choose values to provide a zero at 1 to 3 times the output LC resonant frequency f = See AN-31, page π ( R6+ R12) C NOTE: AN-31 page numbers refer to the pages of the stand-alone document

84 Step 6: Feedback Design - TL431 Compensation Provides high loop gain at low frequencies Compensation network designed to optimize low frequency gain Use 1 µf compensation capacitor (C14): establishes zero at <20 Hz Series resistor R9 provides ~700 Hz zero, improving light load stability See AN-31 page 12 for details 8-84 NOTE: AN-31 page numbers refer to the pages of the stand-alone document

85 Step 6: Feedback Design - Summary AN-31 provides typical component recommendations Application specifications can influence component values Converter operating temperature range Transient load response specifications Circuit board material used: Aluminum substrate versus FR-4 PCB Component value choices should be made based on prototype tests Output voltage transient load response (peak deviation and settle time) provides a good first indication of control loop stability All tests should be performed at both input voltage extremes, load-step extremes and operating temperature extremes, to confirm acceptable performance 8-85

86 Quick Design Checklist for Forward Maximum drain voltage Verify peak drain voltage < 80-90% of BV DSS under worst-case conditions (high line/overload) Transformer reset margin Verify that the transformer resets at the highest VIN, with a % load step (this test puts the greatest demand on the reset circuit) Drain current at maximum input voltage, load and ambient temperature The transformer must not saturate at start-up, or various steady state conditions The leading edge current spike must be within the device current limit envelope (see the quick design checklist for Flyback design) Thermal Verify that key component temperatures are within specified limits, at maximum load, maximum ambient temperature and minimum input voltage The DPA-Switch, the transformer, output rectifiers and output capacitors The recommended maximum DPA-Switch source pin/tab temperature is 110 C 8-86 Worst-case loading (maximum overload) occurs just prior to auto-restart See AN-31, page 14

87 Design Support Tools Application Note: AN-31 DC-DC Forward Converter Design Guide Design Accelerator Kit: DAK-21 Includes tested EP-21 board Engineering Report (EPR-21) Datasheet and device samples Blank PC Board Design Ideas DI-24, 25, 29, 31, 32, 37 and 40 PI Expert PIXls forward design spreadsheet PIXls flyback design spreadsheet 8-87 All PI Design Ideas and Application Notes are available at

88 Hints and Tips 8-88

89 DPA-Switch - Layout Considerations DPA-Switch is a precision, high frequency, high current power IC Layout is critical to achieve optimum performance The suggested guidelines should be followed as closely as possible 8-89

90 Minimize loop area from TAB (SOURCE) to input capacitors Primary Side Layout Suggestions Only use SOURCE (PIN) as reference for small signals (low currents) Only use TAB (SOURCE) as return for high switching currents Place decoupling capacitor right at CONTROL/SOURCE pins of device Place L pin resistor close to device and keep L pin trace short to minimize noise on pin 8-90

91 Secondary Side Layout Suggestions Connect common mode EMI capacitor to primary (V IN + ) positive input rail, not to SOURCE of DPA-Switch Minimize loop area (output diode, output inductor, transformer winding) Locate high frequency de-coupling capacitor right next to output pins of power supply 8-91

92 Efficiency Improvement Techniques PARAMETER Larger vs Minimum required DPA-Switch Larger vs Minimum required Magnetics Synchronous vs Diode Rectification PI EFFICIENCY CHANGE +1% to 2% +1% to 2% +3% to 8% Using larger DPA-Switch reduces MOSFET conduction losses Optimum selection is typically one device size larger than minimum required for power delivery Further increases in device size may decrease efficiency due to increase in switching loss Programmable I LIMIT allows same current limit with larger devices Larger magnetics can reduce copper/core losses Synchronous rectification reduces rectification losses See DI-24 vs DI-25 for example of these improvements 8-92 The externally programmable current limit allows a larger device to be used, without increasing the overload power or requiring magnetics design changes

93 Basic Synchronous Rectification Circuitry Self driven synchronous rectification (SDSR) Auto-restart prevents D3 from failing during short circuit OUTPUT VOLTAGE EFFICIENCY GAIN OVER DIODE RECTIFICATION 5 V +3% 3.3 V +6% 2.5 V +8% Accurate DPA-Switch OV/UV keeps Q1/Q2 gate drive within safe limits (2.5 V to 25 V) 300 khz minimizes crossover losses PI See DI-25 and DI-40 for examples 8-93 Q2 is turned on as the DPA-Switch turns on R1 limits the gate drive current and voltage spike during this hard switch event Q1 turns on with the primary reset voltage waveform Parallel diode D3 conducts when the primary reset is complete and Q1 gate drive has been lost (this prevents the Q1 body diode from conducting any substantial current)

94 Magnetics Construction Core gapping: Forward Converters Start with the transformer core un-gapped - minimizes magnetizing energy For some designs, a gap may be necessary, to reduce the reset time Higher magnetizing energy forces a higher reset voltage and shorter reset time Core gapping: Flyback Converters Always gap transformer cores according to PI Expert recommendations Flux density AC-flux 1000 < B M < 1500 Gauss (for Forward) [100 < B M < 150 mt] Peak-flux B P < 3000 Gauss (for Flyback) [B P < 300 mt] Windings Use a split primary winding to reduce the leakage inductance Use multi-strand wire to minimize Skin Effect - up to 4 strands can (typically) be terminated, per pin Consider using foil, if more than 4 strands are required 8-94 A small core gap may be necessary. For example, if there is significant secondary capacitance, such as synchronous rectifier MOSFET gate capacitance, a small gap can help ensure complete core reset. The gap should be created using thin plastic film, between all legs of the core, since consistent center leg gapping can be difficult and problematic.

95 Hints for Low Output Voltage DC-DC Converters With <3.3 V outputs, a boost supply is required to drive feedback current An additional transformer winding will be required to supply the TL431 and opto-coupler (or, a low voltage (1.25 V) TLV431 could be used) With <2.5 V output, a higher voltage winding will be required to drive the synchronous rectifier MOSFET gates For low voltage outputs, remote sense is often required to compensate for the voltage drop in the output connections and the path to the load The anticipated voltage drop should be factored into the initial design specs Printed circuit traces should be short and wide to minimize voltage drops A secondary, high frequency LC post filter may be required to reduce switching frequency ripple and noise 8-95 DI-40 is an example of a design with an output under 3.3 V

96 Hints for High Power DC-DC Converter Design Use aluminum-clad circuit board to optimize heatsinking Use resonant primary snubber/clamp to recycle energy (see DI-31) Secondary capacitance from synchronous rectifiers/snubber may require transformer gapping to reduce reset time Synchronous rectifiers: use gate resistors (1-10 Ω) to filter voltage spikes Place secondary catch diode close to transformer to reduce secondary leakage spikes Use foil secondary windings or planar magnetics to reduce copper loss Use wide secondary traces or remote sensing to minimize voltage drops 8-96 An example circuit for remote sensing is shown on the following slide

97 Example Remote Sense Circuit using TL431 R2/R3 divider sets LOAD regulation voltage Provides local feedback if remote sense line not connected: typically chosen to be < 1% of R2 value TL431 current path when sense line is disconnected C1 and C2 provide local AC feedback: they are only required if cable/trace impedance includes circuitry introducing significant phase shift e.g. local LC filter at remote LOAD R4 provides return for TL431 current when sense line is not connected. Choose lowest value possible but still much greater than Cable/Trace impedance 8-97 A remote sense circuit ensures that regulation is maintained at the load The estimated, full-load cable and/or trace impedance related voltage drops should be taken into account, in the converter specifications: e.g. 5 V at the remote load may require 5.2 V at the converter output, increasing the rated power requirement by 4%

98 DPA-Switch Application Examples 8-98 Seminar_DPA_100102_screen_102102

99 Application Examples 30 W Forward with diode rectification (EP-21/DI-24) 5 V/6 A output, 36 V to 75 V input 30 W Forward with synchronous rectification (DI-25) 5 V/6 A output, 36 V to 75 V input 20 W Forward with synchronous rectification (DI-40) 2.5 V/8 A output, 36 V to 75 V input 70 W Forward with synchronous rectification (DI-31) 5 V/14 A output, 36 V to 75 V input 15 W Multi output Forward with diode rectification (DI-32) 5 V, 7 V, 20 V outputs, 36 V to 75 V input 25 W Flyback with diode rectification (DI-29) 7 V/3.6 A output, 36 V to 75 V input DI: Design Idea EP: Engineering Prototype Board 8-99

100 Specification (DI-24) PARAMETER Input Voltage SPECIFICATION V Output Voltage 5 V ± 5% Output Current Output Power 6 A 30 W Efficiency 85% Ambient Temp Range -40 C to 65 C with no heatsink -40 C to 85 C with heatsink Optimized for low cost Smallest possible DPA-Switch Diode output rectification 400 khz frequency to reduce magnetics size Features used Lossless current limit - no current sense components UV/OV and DC MAX reduction No-load regulation Thermal/overload protection Dimensions mm ( ) PI

101 Schematic (DI-24) Capacitor limits DRAIN voltage under normal load conditions Reset capacitor Coupled choke bias winding for +1% efficiency improvement Sets UV/OV & DC MAX reduction Zener clamps DRAIN voltage under transient & overload conditions ILIMIT program resistor Only 11 primary components Soft finish capacitor removes startup overshoot 8-101

102 PC Board (DI-24) Provided in DAK-21 with full engineering report (EPR-21) 8-102

103 Drain Current and Voltage Waveforms 36 VDC IN/5 V 6 A OUT 72 VDC IN/5 V 6 A OUT 1 A/div 1 A/div 50 V/div 96 V 50 V/div 134 V 500 ns/div 500 ns/div Resets fully with comfortable margin at all line voltages (36 V to 72 V) Drain Voltage well within minimum device specifications 8-103

104 Thermal Derating Curve 8-104

105 Output Ripple and Transient Response (DI-24) Measurements made at 48 V input Output Switching Ripple - full load 50% to 75 %, 100 ma/µs Step Load 20 mv/div 2 A/div 1.5 A 15 µs 50 mv/div Settling time < 200 µs Ripple p-p = 34 mv Peak Deviation < 3% 1µs/div 100 µs/div 8-105

106 Summary (DI-24) Only 11 primary side components 85% efficiency with diode rectification 90% efficiency possible with synchronous rectification (see DI-25) 400 khz operation Accurate input UV/OV - meets ETSI standards Maintains regulation at no-load No current sense components Thermal/overload fault protection with automatic recovery 8-106

107 30 W Forward with sync. rectification (DI-25) PARAMETER Input Voltage SPECIFICATION V Output Voltage 5 V ± 5% Output Current Output Power 6 A 30 W Efficiency 90% Ambient Temp Range -40 C to 65 C with no heatsink -40 C to 85 C with heatsink Optimized for high efficiency One size larger DPA-Switch than DI-24 (identical output power) synchronous rectification 300 khz frequency Features used Lossless current limit - no current sense components UV/OV and DC MAX reduction No-load regulation Thermal/overload protection Dimensions mm PI

108 30 W 5V/6A Forward with sync. rectification (DI-25) Simple SDSR circuit - DPA-Switch UV/OV features limit gate drive voltage range Only 10 primary side components! SDSR Self-Driven Synchronous Rectification

109 Comparison: Diode vs Synchronous Rectification Efficiency of Diode Rectification vs Sync Rectification Sync. rectification (DI-25) 90% 85% Diode rectification (DI-24) Note approximately 5% efficiency improvement with synchronous rectification, one size larger DPA-Switch and optimized magnetics 8-109

110 20 W 2.5 V/ 8 A Forward with sync. rectification (DI-40) PARAMETER Input Voltage SPECIFICATION V Output Voltage 2.5 V ± 5% Output Current Output Power 8 A 20 W Efficiency 86% Ambient Temp Range -40 C to 65 C with no heatsink -40 C to 85 C with heatsink High efficiency for low voltage output (86%) Optimized magnetics Synchronous rectification 300 khz frequency Features used Lossless current limit - no current sense components UV/OV No-load regulation Thermal/overload protection PI This design uses the smallest DPA-Switch for the power required. One size larger could also be considered if higher efficiency is required.

111 20 W 2.5 V/8 A DC to DC Converter Circuit (DI-40) Low output voltage requires boost winding from output choke to supply opto/tl431 Forward bias winding taken from main transformer for DPA-Switch supply Only 10 primary side components! 8-111

112 20 W 2.5 V/8 A Converter Efficiency Results 8-112

113 70 W Forward with sync. rectification (DI-31) PARAMETER Input Voltage SPECIFICATION V Output Voltage 5 V ± 5% Output Current Output Power 14 A 70 W Efficiency 87% Ambient Temp Range -40 C to 85 C with heatsink PI Optimized for efficiency Largest DPA-Switch used Synchronous rectification 300 khz frequency 90% efficiency achieved Features used Lossless current limit - no current sense components even at 70 watts! UV/OV and DC MAX reduction No-load regulation Thermal/overload protection 8-113

114 70 W Forward with sync. rectification (DI-31) Resonant clamp used to recycle magnetizing and leakage energy Only primary circuitry shown for clarity. For full schematic see DI-31 Even at 70 Watts, no current transformer required. Reduces system cost significantly Only 14 primary side components! Simple DPA-Switch compensation components identical to lower power designs High power requires a resonant clamp circuit but otherwise primary circuitry is unchanged from lower power DPA-Switch designs - easily scalable solution

115 15 W Multi-output (DI-32) PARAMETER Input Voltage Output V1 V2 V3 Output I1 I2 I3 Output Power SPECIFICATION VDC 5 V ± 5% 7.5 V ± 5% 20 V ± 15% 2.4 A 0.4 A 0.01 A 15 W Excellent cross regulation on 3 outputs High efficiency: 88% Sync. rectification at 400 khz minimizes magnetics size Features used Lossless current limit - no current sense components UV/OV and DC MAX reduction No-load regulation Thermal/overload protection Efficiency 90% PI

116 15 W Multi-output (DI-32) Only 10 primary side components! Lower power design did not require primary leakage clamp capacitor Secondary reset capacitor is not required as Q1 has sufficient gate capacitance to perform this function DI-32 was not optimized until after print The Schematic shows working design however secondary feedback can be simplified per previous example circuits Please see DI-32 for corrected version

117 Cross Regulation Performance (DI-32) Output Voltage Voltage Range (VDC) Load Range Cross Regulation (%) V % 7.5 V % 20 V % PI

118 25 W Flyback (DI-29) PARAMETER Input Voltage Output Voltage Output Current Output Power SPECIFICATION VDC 5 V, 7.5 V, 20 V 2.4 A, 0.4 A, 10 ma 15 W Efficiency 88% Ambient Temp Range -40 C to 65 C PI khz to minimize magnetics size 87% efficiency at full load 48 V without synchronous rectification Features used Lossless current limit - no current sense components UV/OV No-load regulation Thermal/overload protection 8-118

119 25 W, 400 khz Flyback Example (DI-29) Only 10 primary side components! 8-119

120 Cost Savings 8-120

121 8-121