Techniques for On-Chip Process Voltage and Temperature Detection and Compensation

Transcription

1 Techniques for On-Chip Process Voltage and Temperature Detection and Compensation Qadeer A. Khan 1, G.K. Siddhartha 2, Divya Tripathi 3, Sanjay Kumar Wadhwa 4, Kulbhushan Misri 5 Freescale Semiconductor India Pvt. Ltd. { 1 q.khan, 2 siddhartha.gk, 3 divya, 4 sanjay.wadhwa, 5 k.misri}@freescale.com Abstract This paper presents techniques to detect process, voltage and temperature (PVT) variations in an integrated circuit chip and wafer. Conventional techniques are limited to detection of Process Variations in which the MOS devices (NMOS and PMOS) move in similar direction i.e. fast n-fast p or slow n slow p. The presented techniques can be used to compensate skewed variations on the chip i.e. fast n slow p or slow n-fast p thus increasing the utilization (yield) of the wafer. The proposed techniques can be implemented in any standard CMOS process and can easily be integrated with any circuit requiring PVT compensation. Major applications of these circuits are in I/O drivers and PVT sensitive analog circuits. For I/O drivers, simulation results show that the rise/fall time variation with PVT has been reduced to more than half using the proposed circuits. 1. Introduction As technology is shrinking to sub 100nm, the sensitivity of circuits towards process, voltage and temperature (PVT) variation is hampering circuit performance and yield. For example, in the case of I/O pads it is difficult to meet the rise and fall times, current, power and ground bounce specifications across all PVT corners. Driver circuits are oversized to meet timing at slow corners. This causes high current and Simultaneous Switching Noise (SSN) at fast corners. Such effects degrade the reliability of the circuit and require considerable amount of design resources and time to meet circuit performance across PVT variation. Previously proposed PVT detection techniques [1-4] are limited to detection of Process Variations in which the MOS devices (NMOS and PMOS) move in similar direction i.e. fast n-fast p or slow n slow p. Thus, they fail to work on a chip fabricated at skewed process corners (fast n slow p or slow n-fast p). The circuit proposed in [5] uses complex body-biasing technique. This not only requires the costlier Isolated P-Well process but may also cause floating of the bodies while supply ramp-up which may lead to latch-up in the circuits. To overcome this drawback, we propose circuits to detect and compensate the PVT variation across aligned as well as skewed process corners. Various applications of the proposed circuits and simulation results for compensating I/O drivers are presented. 2. Design Description We propose two circuits namely: 1. Delay locked loop (DLL) Based PVT compensation: change in phase error between input and output is tracked across PVT. 2. Ring oscillator based PVT compensation: variation in frequency of a ring oscillator tracks variation in PVT, which is measured in a reference clock cycle. 2.1 Delay Locked Loop (DLL) Based PVT compensation In this circuit, a Delay Locked Loop is employed such that the phase difference between input and output of a delay stage is digitized to generate a set of binary codes. These are fed back to control its delay. Figure 1 shows the block diagram of the proposed scheme. A reference clock signal is applied to the driver input, IN. The phase detector compares the phase difference between IN and the driver output signal, OUT and generates a phase error (PE) signal. PE is averaged using a Low Pass Filter and fed to analog comparator block. The output of the comparators is compared with a reference code (obtained at typ corner) in a digital logic stage. The output of the digital logic adjusts the driver delay. The internal modules are described below.

2 The APE values are calculated for rising (corresponding to PMOS corner) and falling (corresponding to NMOS corner) edges of the output, OUT as shown in Figure 3 and Figure 4 respectively. The NMOS and PMOS driver units can be independently detected and compensated. This ensures compensation for skewed corners on the wafer as well Reference Generator and Analog Comparator Fig 1. DLL based PVT detection and correction circuit Phase Detector As shown in Fig2, an XOR gate has been used as a phase detector. Whenever the PVT corner changes, slew rate of the output changes that change the phase difference between IN1 and IN2. The output pulse width of XOR gate changes according to the phase difference between IN1 and IN2. The output of XOR gate is passed through a LPF filter which generates the output, average phase error (APE). The APE value varies according to the PVT corner. As shown in Figure 5, the average phase error (APE) output is applied to the negative input of a set of comparators along with multiple reference signals derived from supply voltage (VDD) and a digital code P [n:0] is generated corresponding to the APE value. Bcs_fet indicates fast-p fast-n corner and wcs_fet is slow-p slow-n corner. If supply variation needs to be taken care of, the reference can be generated from Bandgap Reference. Fig 2. Phase Detector Block Diagram and Response The above principle can be extended for skewed corner detection as well. Fig 3. Phase Detector for detecting PMOS corner Fig 4. Phase Detector for detecting NMOS corner Corner Fig 5. Circuit Diagram Average Phase Error (APE) V Digital Code P[n:0] Bcs_fet (-40) Bcs_fet (-25) Bcs_fet (125) Typ_fet (-40) Typ_fet (-25) Typ_fet (125) Wcs_fet (-40) Wcs_fet (-25) Wcs_fet (125) Table1: Shows codes obtained at different corners

3 2.1.3 Digital Logic As shown in Figure 6, the inputs to the digital logic are P[n:0] (from voltage reference and comparators), a reference code Typ[n:0] corresponding to typical drive strength of the comparator, and a low frequency clock CAL_CLOCK that is used to enable the PVT calibration phase. This digital logic generates code C[n:0] by comparing P[n:0] and Typ[n:0]. C[n:0] is applied to the driver to increase or decrease its drive strength. At reset, Typ[n:0] is output at C[n:0]. Thus, the system will evaluate APE value for the fabricated corner with driver strength set corresponding to the typical PVT corner. Fig 7. Locking action of circuit after reset Fig 6. Digital comparator P[n:0] Flag Values C[n:0] = Typ[n:0] > Typ[n:0] > Typ[n:0] lock=1, shr=0, shl=0 lock=0, shr=1, shl=0 lock=0, shr=0, shl=1 No change Shift Right C[n:0], stuff 0 Shift Left C[n:0], stuff 1 Table2: Logic table showing values of flags lock, shr and shl At the positive edge of CAL_CLOCK, depending on whether P[n:0] is equal, greater or lesser than Typ[n:0], the flags lock, shr (shift right), shl (shift left) are set. The output code C[n:0] is left unchanged, shifted right or shifted left respectively. At each positive edge of CAL_CLOCK, P[n:0] is again compared with Typ[n:0] and the process continues till lock flag goes high. If there is any temperature or voltage change, APE value will change and this process will dynamically compensate by increasing/decreasing the driver size. Figure 7 shows simulation results of the circuit. It shows the locking of the loop and the adjustment in the APE value to bring it near the typical value for bcs_fet, 25 degrees. Initially, when the system is reset, the code Typ[n:0] is applied to the drivers and the APE value corresponding to bcs_fet, 25 degrees is 226.7mV. The circuit keeps on changing the code C[n:0] till the loop locks (shown by lock flag going high) and the APE value finally settles to 269.7mV which is close to that in the typical corner APE value (264mV as shown in Table 1). 3. Ring oscillator based PVT compensation This technique is based on measuring the variation in the frequency of a Ring Oscillator across PVT corners in a reference clock period. The digital count generated determines the corner at which the chip is working. For compensating the skewed corner, either a threshold detect circuit is added or separate N-type and P-type ring oscillators are used. The topology is used in an open-loop configuration guaranteeing stability. Based on skewed corner detection and compensation techniques, two different topologies have been proposed. 3.1 Ring Oscillators and Threshold Detect In this technique a threshold detect circuit along with a ring oscillator is used. Figure 8 shows the block diagram of the circuit. The Ring Oscillator detects slow-slow and fast-fast corners and threshold detect is used for detecting skewed corners i.e slow-fast and fast-slow. The codes generated by the two blocks are combined in the mapping logic to generate the final code. Fig 8. Ring Oscillator based PVT detection with skewed corner detection using threshold detect circuit

4 3.1.1 Current reference and threshold detect Figure 9 shows the diagram of the current reference and threshold detect circuit. Reference current is generated using a simple Vref/R circuit. Vref can be from a Bandgap Reference output or generated from the supply voltage. The R is implemented using diode connected PMOS and NMOS transistors acting as a threshold detector. At worst case and best case corners, relative resistance of PMOS and NMOS remains same and hence Vdet almost remains constant (same as typical corner) but current Ico is changed thereby detecting wcs and bcs. Ico also changes with temperature variations. If Vref is generated from supply VDD, Ico detects voltage variations as well. For skewed corner relative resistance of PMOS and NMOS varies almost equally in opposite directions, therefore Ico almost remains unchanged while voltage Vdet changes. Current Ico is used in a current controlled oscillator to generate PVT dependent frequency. Voltage Vdet is compared with reference voltages Vref[m:1] in comparator to generate a code to determine skewed corner. Corner Detected Ico Vdet Temperature and Voltage Yes No Typ Yes No Wcs_fet Yes No Bcs_fet Yes No Wnbp_fet No Yes Bnwp_fet No Yes Table3: Shows corners detected by Ico and Vdet Voltage reference and Comparator Block Voltage reference and comparator block is shown in figure 11. Fig 11. Voltage Reference and Comparator Circuit Fig 9. Circuit Diagram Current controlled oscillator (CCO) Figure 10 shows the CCO that generates a clock clk_osc of frequency (Fosc) proportional to Ico. Since Ico depends on PVT, the output frequency of CCO also tracks PVT corner. Fig 10. Current controlled oscillator Corner Vdet (V) code skwd [2:1] code bcs_wcs [7:1] bcs_fet (-40) bcs_fet (-25) bcs_fet (125) bnwp_fet (-40) bnwp_fet (-25) bnwp_fet (125) typ_fet (-40) typ_fet (-25) typ_fet (125) wnbp_fet (-40) wnbp_fet (-25) wnbp_fet (125) wcs_fet (-40) wcs_fet (-25) wcs_fet (125) Table4: Showing simulation results of Current reference and threshold detect circuit

5 A set of comparators are used to compare Vdet to generate a set of bits (code_skwd[m:1]) for skewed corner detection. Depending on the resolution required, the number of bits can be increased or decreased. Table 4 shows the Vdet values, and code generated at the different process corners Figure 14, 15 & 16 and table 5 shows the response of the driver circuit at three corners with and without compensation. 3.2 P and N ring oscillator based PVT compensation Figure 12 shows the block diagram in which NMOS and PMOS corners are detected by using two separate Ring Oscillators, one consisting of only PMOS and the other consisting of only NMOS. The number of cycles of the ring oscillator outputs is counted in a references time period and PVT corner is determined. Fig 14. Compensated Driver Response at bcs_fet, 25DegC Fig 12. P and N Ring Oscillator based PVT compensation 4. Applications and Simulation The proposed PVT detection and compensation circuits can be used in various circuits sensitive to PVT variation. Some the applications are listed below: 4.1 I/O Drivers Fig 15. Compensated Driver wcs_fet, 25DegC Figure 13 shows a I/O driver whose drive strength can be changed across PVT according to logic bits pvt_code_p[n:0] and pvt_code_n[n:0] generated via any of the above schemes. Since PMOS and NMOS drive strengths are controlled separately, this configuration can be used to provide compensation in conjunction with circuits that detect skewed corners. Fig 13. Application of PVT detect code shown with I/O Drivers z Fig 16. Compensated Driver typ_fet, 125DegC The waveforms show the response at ideal, uncompensated and compensated driver respectively. Ideal response refers to the response at typ_fet, 25DegC.

6 Table 5 shows the results of the rise and fall times before and after DLL based PVT compensation. It is evident from the results that compensation technique significantly reduces the variation in rise/fall times across PVT. Corner typ, 25 Trise (ns) % deviation wrt typ Tfall (ns) % deviation wrt typ typ, 125 uncompensated typ,125, compensated wcs,25 uncompensated wcs,25 compensated bcs,25, uncompensated bcs,25, compensated Table 5: Rise-fall values before and after compensation and % variation wrt typical 25 corner 4.2 Impedance Matching in USB, SATA, LVDS Transceivers Conventionally Rs is varied to match the impedance across PVT. Use of PVT detect will automatically control the impedance by adjusting R TX on-chip Fig 17. Compensation technique for I/O transmitter 4.3 Reduction in Frequency Variation in Ring Oscillator Fig 18. Compensation technique for ring oscillator MUX is controlled by PVT detection circuit output to determine number of inverter stages in the Ring 4.4 Constant delay circuit in data/clock path The MUX is controlled by PVT Detector to determine number of buffers to be in delay path depending upon the corner. This can be used in critical delay paths for e.g. in DDR memory data capture. Fig 19. Compensation technique for delay line 5. Conclusion Circuits have been presented to detect Process, Voltage and Temperature corners across a chip/wafer. It can be easily integrated with PVT sensitive circuits. Unlike conventional techniques, they are able to detect skewed corners with cost-effective techniques and no additional processing steps thereby reducing design effort and increasing the yield of the chip. Various applications of the proposed techniques are also shown. Simulation of I/O driver compensation showed that the variation in rise-fall times was reduced by more than half. 6. References [1] Output buffer with self-adjusting slew rate and on-chip compensation, Lim, C.H.; Daasch, W.R.; IEEE Symposium on IC/Package Design Integration, Proceedings. 1998, 2-3 Feb. 1998, Pages: [2] A PVT-insensitive CMOS output driver with constant slew rate, Seok-Woo Choi; Hong-June Park; Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits 2004., 4-5 Aug. 2004, Pages: [3] Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin x16 DDR SDRAM, Jung-Bae Lee; Kyu- Hyoun Kim; Changsik Yoo; Sangbo Lee; One-Gyun Na; Chan-Yong Lee; Ho-Young Song; Jong-Soo Lee; Zi-Hyoun Lee; Ki- Woong Yeom; Hoi-Joo Chung; Il-Won Seo; Moo-Sung Chae; Yun-Ho Choi; Soo-In Cho; Solid-State Circuits Conference, Digest of Technical Papers. ISSCC IEEE International 5-7 Feb Page(s):68 69, 431. [4] Process, voltage and temperature compensation of offchip-driver circuits for sub-0.25µm CMOS technology, Hua Chi; Stout, D.; Chickanosky, J.; ASIC Conference and Exhibit, Proceedings., Tenth Annual IEEE International 7-10 Sept Page(s): [5] Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage, Tschanz, J.W. et. al., IEEE Journal of Solid-State Circuits, Volume: 37, Issue: 11, Nov. 2002, Pages: