DISTRIBUTED POWER SYSTEMS (DPSs) are widely

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1 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST High-Frequency High-Efficiency CLL Resonant Converters With Synchronous Rectifiers Daocheng Huang, Dianbo Fu, Member, IEEE, FredC.Lee,Fellow, IEEE, and Pengju Kong, Member, IEEE Abstract This paper proposes a CLL resonant dc dc converter as an option for offline applications. This topology can achieve zero-voltage switching from zero load to a full load and zero-current switching for output rectifiers and makes the implementation of a secondary rectifier easy. This paper also presents a novel methodology for designing CLL resonant converters based on efficiency and holdup time requirements. An optimal transformer structure is proposed, which uses a current-type synchronous rectifier (SR) drive scheme. An 800-kHz 50-W CLL resonant converter prototype is built to verify the proposed circuit, design method, transformer structure, and SR drive scheme. Index Terms Design methodology, driving scheme, high efficiency, high frequency, high power density, resonant converter, synchronous rectifier, transformer. I. INTRODUCTION DISTRIBUTED POWER SYSTEMS (DPSs) are widely used in offline applications, such as servers and telecom applications. In a DPS, power is processed in two stages: front-end converters and load converters. Efficiency and power density are the two main driving forces of front-end converters [1]. Front-end converters normally consist of three parts: an electromagnetic interference (EMI) filter, a power-factorcorrection circuit, and a dc dc converter. For computing applications, holdup time operation is required. Bulky capacitors must be used to provide energy during the holdup time. A wide operation range in the dc dc stage is necessary to reduce the holdup time capacitance. Pulsewidth modulation (PWM) converters are widely employed as front-end dc dc converters. Two-switch forward converters [] have received a lot of interest for their robustness and their easy transformer reset mechanism. However, their high switching loss and large filter inductance are major concerns. Phase-shift full-bridge (PSFB) converters [3] can achieve zerovoltage switching (ZVS) to enhance the efficiency of the converter. However, when a holdup time is needed, the duty cycle of PSFB converters is small at nominal conditions. A small duty cycle leads to large circulating energy and high turnoff switching loss, which significantly sacrifices the efficiency. Manuscript received January, 010; revised May 3, 010 and August 9, 010; accepted September 9, 010. Date of publication November 18, 010; date of current version July 13, 011. D. Huang, F. C. Lee, and P. Kong are with the Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, VA 4061 USA ( huangdao@vt.edu; fclee@vt.edu; pjkong@vt.edu). D. Fu is with Huawei Technologies, Plano, TX USA ( dfu@huawei.com). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TIE The aforementioned problems can be solved by using an LLC resonant dc dc converter [4] [6]. Low switching loss and low circulating energy are achievable at nominal conditions. Thus, high-efficiency operation is accomplished. A wide input voltage range is obtained in the low-frequency range, where the voltage gain is very high. Thus, the LLC resonant converter is suitable for offline applications with holdup time requirements. Nevertheless, for LLC resonant converters, there are still issues, such as how to drive synchronous rectifiers (SRs) and how to achieve low loss for a gapped transformer at high switching frequencies. Commercially, the drain source voltage of SRs is sensed to drive SRs. However, the package inductance of an SR would cause a phase shift of the sensed voltage, which introduces high body-diode conduction loss. A compensation driving scheme has been proposed to correct the deviation [7]; however, this compensation scheme requires extra circuits, which are complicated. A secondary-side current-sensing method is also used to drive SRs [8]. However, the large size of the currentsensing transformer makes it awkward to use. For high-current applications, the extra resistance of the current transformer (CT) winding becomes lossy. On the other hand, the primaryside current is much lower, which means that the CT can be small and more efficient. However, the magnetizing inductance of the transformer for an LLC converter is used as resonant inductance and thus is relatively small. Due to the magnetizing current, the sensed primary-side current and the SR current are out of phase. Hence, the SR cannot be driven by sensing the primary-side current. To solve these issues, Wu et al. [9] propose an improved current-sensing method with an additional inductor and compensation circuits. However, the complexity and cost are major drawbacks. Consequentially, determining how to effectively drive an SR remains an issue for LLC resonant converters. In the transformer design, an air gap is used to control the magnetizing inductance. However, high eddy-current losses are induced due to the fringing effect of the air gap. The higher the switching frequency, the stronger the fringing effect. The CLL resonant converter is a potential alternative solution for front-end dc dc converters. The CLL resonant converter is studied with a full-bridge configuration in [10]. The design methodology is limited to zero-current switching (ZCS) applications where insulated-gate bipolar transistors are employed, and it is not suitable for high-frequency applications where MOSFETs are used. In addition, the impact of the holdup time operation is not considered. An asymmetrical PWM ZVS CLL converter is proposed in [11] and [1]. The asymmetrical operation introduces high rms currents and high turnoff /$ IEEE

2 346 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 011 currents, which cause high conduction loss and turnoff loss. An extra snubber capacitor is needed to reduce the high turnoff loss, which increases the cost and complexity of the whole system. This paper proposes a symmetrical-duty-cycle frequencycontrolled CLL resonant converter. Using this control mode, lower rms current and turnoff currents can be achieved. This leads to much lower conduction loss and switching loss than that in an asymmetrical PWM-controlled converter. In addition, snubber capacitors and complicated design are not required. Based on the symmetrical operation mode, it is possible to achieve ZVS for the entire load range. Meanwhile, the air gap in the transformer is omitted to eliminate the fringing effect. Moreover, because of very high magnetizing inductance, the transformer s primary-side current is in phase with the secondary-side current. Thus, the SR can be easily driven. Hence, higher efficiency and higher power density can be achieved. This paper is organized as follows. The basic characteristics of the proposed CLL resonant converters are discussed in Section II. A novel optimization design methodology of CLL resonant converters is presented in Section III. Section IV presents the optimal transformer structure for CLL resonant converters. A current-type SR drive scheme is proposed in Section V. Finally, the experimental results are discussed in Section VI. An 800-kHz 50-W prototype is built to verify the proposed optimal design method, the transformer structure, and the proposed SR driving scheme. Using this prototype, up to a 96.7% efficiency is achieved. II. CHARACTERISTICS OF CLL RESONANT CONVERTER The topology of the CLL resonant converter is shown in Fig. 1. The main relationships in the CLL resonant converter are given in (1) (9), where ω s is the switching angular frequency, R o is the load resistor, and T s is the switching period. 1) Normalized voltage gain ) Resonant inductor ratio 3) Equivalent resonant inductor M =V o n/v in. (1) L n = L 1 /L. () L eq = L 1 L /(L 1 + L ). (3) 4) Equivalent characteristic inductor L P = L 1/(L 1 + L )=L eq L n. (4) 5) Characteristic impedance Z 0 = L eq /C 1. (5) 6) Characteristic angular frequency ω o =πf o =π/t 0 =1/ L eq C 1. (6) Fig. 1. CLL resonant converter. Fig.. Basic characteristics of the CLL resonant converter. (a) Equivalent circuit of CLL resonant converter. (b) CLL resonant converter s gain curves. 7) Parallel resonant frequency 8) Quality factor f 0 =1/(π L 1 C 1 ). (7) Q = Z 0 /(n R o ). (8) 9) Normalized characteristic angular frequency ω n = ω s /ω o = f s /f o. (9) Fundamental mode approximation is used for resonant tank analysis. Based on the equivalent circuit shown in Fig. (a), the voltage gain expression of the CLL resonant converter is deduced as follows: M = nv o V in = (1+L n ) L n (1 + L n ) ωn 8 Q (1 ω n) jω n +1 (1 + L n ) ωn. (10) π The gain curves of the CLL resonant converter are plotted in Fig. (b). There are two resonant frequencies for CLL resonant converters. One is the series resonant frequency, whose value is equal to the characteristic frequency. The other resonant frequency is the parallel resonant frequency. The parallel resonant frequency is introduced by L 1 and C 1 and is defined as f 0.The operation regions of CLL resonant converters could be divided into three parts, as shown in Fig.. These operation regions are the ZCS region, the ZVS1 region, and the ZVS region.

3 HUANG et al.: HIGH-FREQUENCY HIGH-EFFICIENCY CLL RESONANT CONVERTERS WITH SRs 3463 contributes to the ZVS operation. When S 1 is turned off, V s drops sharply. However, due to the conduction of the SR, V m is clamped to nv o. During the MOSFET s transition dead time, V C1 changes very little. As a consequence, the voltage across L becomes very high. i L drops quickly until it reaches zero. It can be observed that high di/dt will be generated if the L value is small. Therefore, this region is not preferred with the design of a small L. The point at which the switching frequency equals the resonant frequency is very important. This point is the optimal point of the frequency range for minimal switching loss and circulating energy. Thus, at the nominal condition, the CLL resonant converter should be designed to operate close to the resonant frequency. At the resonant frequency [shown by a black dot in Fig. (b)], according to (10), the voltage gain is derived as M =1+1/L n. (11) Fig. 3. Waveforms of CLL resonant converter at each operation region. (a) ZCS region. (b) ZVS1 region. (c) ZVS region. (d) At resonant frequency with full load. (e) At resonant frequency with no load. As shown in Fig. 3(a), in the ZCS region, the primary-side switches (S 1,S ) can achieve ZCS. During [0,t r ], L 1, L, and C 1 resonate with each other. During [t r,t s /], L 1 resonates with C 1, and i C1 turns negative before S 1 is turned off. As a result, i C1 goes through D 1, which is the body diode of S 1. At T s /, S is turned on, and D 1 will be turned off. The hard turnoff of the MOSFET body diodes generates severe reverserecovery loss and high-voltage stress. Thus, this operation region should be avoided for MOSFETs. As shown in Fig. 3(b), in the ZVS1 region, the primaryside switches (S 1,S ) can achieve ZVS. During [0,T s /], V s and V o1 are positive. During [0,t r ], L 1, L, and C 1 resonate. During [t r,t s /], L 1 resonates with C 1.AtT s /, i C1 remains positive. When S 1 is turned off, i C1 charges and discharges the junction capacitors of S 1 and S, respectively. Hence, ZVS is achieved. In this region, an output rectifier can achieve ZCS. This suggests that low di/dt is beneficial for rectifiers. The waveforms of the CLL resonant converter in the ZVS region are plotted in Fig. 3(c). The primary-side switches (S 1,S ) can also achieve ZVS. During [0,T s /], V s and V o1 are positive. During [0,T s /], L 1, L, and C 1 resonate. At T s /, i C1 is still positive. When S 1 is turned off, i C1 The voltage gain value at the resonant frequency is independent of the load. The waveforms of the heavy-load and noload conditions at this point are shown in Fig. 3(d) and (e), respectively. Equation (1) is derived from the circuit drawn in Fig. 1. From Fig. 3(d) and (e), the boundary conditions are represented in (13). { C 1 d(v in V m ) dt = i C1, L 1 di L1 dt = V m d(i L C1 i L1 ) (1) dt = V m V o1 { ( il1 (0) = i Ts ) L1, ic1 (0) = i L1 (0) T s Ts 0 [i C1 (t) i L1 (t)] dt = V o n R o. (13) Thus, the current expressions at the series resonant frequency are deduced in [ ] i L1 (t) = πl V in 4ω s (L1 +L )ω s L n 1 R o sin(ω s t) cos(ω s t) + V ( ) in L 1 t T s 4 [ ] i C1 (t) = πl ω s C 1 V in 4L 1 (L1 +L )ω s n R o sin(ω s t) cos(ω s t) i C1 (t) =i L1 (t)+i L (t). (14) At the MOSFETs transition dead time, t =0, t = T s /, and i L1 =0. Thus, i C1 = i L1 and is derived in (15). This current charges and discharges the junction capacitors of the primaryside MOSFETs. During the dead time, since i C1 and i L1 are independent of the load, ZVS can be achieved for the entire load range with the proper design. i C1 (0) = i L1 (0) = i C1 = V in T o 4 ( Ts ) = i L1 ( ) Ts L 1 + L L. (15) 1 Physically speaking, all three resonant elements resonate during power delivery. When the output rectifiers are off, only two elements (L 1 and C 1 ) resonate. In contrast, for existing LLC resonant converters, two series-resonant elements

4 3464 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 011 resonate during power delivery. When the output rectifiers are off, all three resonant elements resonate. Due to the very different operation scenario for the proposed CLL resonant converter, the voltage gain at the resonant frequency is 1+ 1/L n. The voltage boost capability at the resonant frequency may be very useful for high-voltage applications. The benefits of the topology difference in the transformer design and of being SR driven are discussed in Sections IV and V. III. DESIGN METHODOLOGY FOR CLL RESONANT CONVERTERS There are many papers that present different design methods for the LLC resonant converter. In [13], LLC resonant converters are designed with a numeric processing scheme. In this scheme, resonant tank parameters are chosen based on a numerically determined minimum input power with a given output power. Nevertheless, this method relies purely on numeric analysis and is hence very complicated. It requires tremendous programming work. Furthermore, even with dedicated iterations, only the primary rms current is taken into account; the switching loss and secondary-side rms current are not considered. Thus, it is desirable to further improve the process of optimization. Reference [14] gives a design method based on start-up current, efficiency, and holdup time requirements. The combination of L n and Q impacts the efficiency, and this paper uses these variables to present a trend of achieving high efficiency. However, the suitable range that is given for L n and Q is based on observation. Thus, the precise optimal efficiency point cannot be obtained, and trial and error iterations are still necessary for this design strategy. Lu et al. [15] provide a design method based on efficiency and holdup time requirements. However, the effects of dead time and device characteristics on the system efficiency are ignored in both [14] and [15]. Thus, the L n and Q curves plotted in these papers are actually not very accurate at high switching frequencies. The optimal design methodology for CLL resonant converters presented in this paper is based on the requirement of high efficiency and the need to accommodate holdup time operation. This design achieves high efficiency over a wide load range. A. RMS Current Without Consideration of Dead-Time Period If the switching frequency is low, the dead time (t dead ) is much shorter than the switching period (T s ). For the sake of simplicity, we treat the switching period T s as approximately the resonant period T o at the resonant point. In accordance with (14) and (15), assuming there is zero dead time, the primary-side and secondary-side rms currents are derived in ( ) ( ) 4 I RMS_P = 1 4 V o Vo Vin R o Ts R o V in V o +4π L P ( ) (16) 4 I RMS_S = π V o 5π 48 Vin R o T 4 R o 1π s V o +1. π L P In (16), I RMS_P and I RMS_S are the primary-side rms current and the secondary-side rms current, respectively. V in and V o represent the input voltage and the output voltage, respectively, and R o represents the full load resistance. L P should be designed to be large to reduce device rms currents. B. RMS Current With Consideration of Dead-Time Period For high-frequency operation, the dead time t dead is so critical that it affects the design considerably. During t dead, no energy is transferred to the load. Thus, a large dead time causes less of an energy transfer interval at the same switching frequency than does a smaller dead time. This leads to higher rms current for the same energy transfer. This dead-time effect should not be ignored. Hence, (16) provides only approximate results for low frequencies or systems with very small t dead. With the consideration of t dead, the expressions of the primaryside and secondary-side rms currents can be deduced using (17) shown at the bottom of the page. C. Dead-Time Influence on RMS Current and Turnoff Current During t dead, the junction capacitor of the primary-side devices will be charged and discharged to achieve ZVS. C eq equals the junction capacitance of one primary-side MOSFET. During a short t dead, the current of L 1, i.e., i L1_ max, remains almost the same and is equal to the primary-side turnoff current I turnoff. I turnoff = i L1 (0) = i L1 = T o 8 ( ) Ts = V in T s L 1 + L 4 L 1 V in L p. (18) I turnoff helps to achieve ZVS and should be large enough to charge and discharge the junction capacitors during t dead. I turnoff t dead C eq V in. (19) I RMS_P = 1 Vo V in R o I RMS_S = 3 V o 1 R o ( Vin V o ) 4 R o T o L P ( Vin V o ) 4 (5π 48)R ot 3 o L P (T o+t dead ) + +4π + 16π (T o t dead +t dead) T o 1π4 T o T o +t dead + 48π4 (T o t dead +t dead) T o (T o +t dead ) (17)

5 HUANG et al.: HIGH-FREQUENCY HIGH-EFFICIENCY CLL RESONANT CONVERTERS WITH SRs 3465 Substituting (18) into (19), we get L p T o t dead 16C eq. (0) To achieve ZVS, L P should satisfy (0). Meanwhile, a large L P is preferred for low conduction loss. Hence, L P should be chosen as T o t dead /16C eq. Applying L P = T o t dead /16C eq to (17), we get (1) shown at the bottom of the page. T d_norm and Z C_norm are defined as follows: T d_norm = t dead /T s () /[ Z C_norm = 1 ( ) ] Vin R o. (3) C eq ω s V o Z C_norm indicates the impedance relationship of the junction capacitor of the device and the load. By substituting () and (3) into (1) and normalizing (1) by the factors P o /0.5V in and P o /V o, (4) shown at the bottom of the page can be derived. P o equals Vo /R o. Hence, it is expedient to apply normalized current to evaluate the performance. By applying (), (3), and L P = T o t dead /16C eq to (18) and normalizing by the factor P o /0.5V in, (15) can be deduced. I Turnoff_norm = 1 1. (5) π T d_norm Z C_norm Fig. 4(a) shows the difference in the primary rms current with and without the consideration of t dead. The dashed line is obtained from (16), and the dotted line is based on (17). As we can see, t dead plays a significant role in a high T d_norm range or a high-frequency range. Fig. 4(b) shows the normalized primary-side rms current I RMS_P_norm and secondary-side rms current I RMS_S_norm. T d_norm influences the primary-side rms current in two ways. On the one hand, based on () and (18), a large T d_norm means a large L p, and less I turnoff is required to achieve ZVS. Hence, Fig. 4. RMS current calculation results. (a) Primary-side rms current with and without consideration of dead-time period. (b) Normalized primary-side and secondary-side rms currents considering dead-time period. less circulating current is achieved. On the other hand, a larger T d_norm causes a smaller power delivery duty cycle. To provide the same energy to the load, higher power is required during the shorter power delivery period, which leads to higher current. Taking the aforementioned two aspects into consideration, the relationship between T d_norm and the primary-side rms current exhibits a U shape. There is an optimal dead time at which the lowest rms current can be achieved. This optimal dead time is identified in the following paragraph. With simple algebra, the normalized dead time for the minimal primary-side rms current and secondary-side rms current can be calculated using ) /(4+ 3 T d_norm_ min_prim = /( T d_norm_ min_sec =1 + π 4 π 4 Z C_norm 3 1 Z C_norm 5π 48 ). (6) D. Design Methodology The design method is based on the requirements of high efficiency and holdup time. The device losses are a major part of the system losses. Based on (4) and (5), we know that the conduction loss and switching loss of the devices are related to the output power, the characteristics of the devices, the I RMS_P = 1 Vo V in R o ( Vin I RMS_S = ( ) 4 6 V o Vin 4π R o V o ) 4 R ( ot o V o To tdead 16Ceq (5π 48)R ( ot o 3 To tdead 16Ceq ) +4π + 16π (T o t dead +t dead) T o ) (To +t dead ) + 1π4 T o T o +t dead + 48π4 (T o t dead +t dead) T o (T o +t dead ) (1) ( I RMS_P_norm = T d_norm I RMS_S_norm = ( 6 1 4π T d_norm ) 8 1 4π π + Z (1 T C_norm d_norm) 8 π ) 1 Z C_norm (5π 48)(1 T d_norm)+ 1π 4 1 T d_norm (4)

6 3466 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 011 Fig. 5. Design relationship. (a) Ratio of device loss and power versus dead time under different loads. (b) Q and L n relationship for ZVS requirement. switching frequency, and the dead time. In particular, (4) indicates that the conduction losses of the primary- and secondaryside devices are not influenced by the resonant tank design. According to (5), the turnoff loss of the primary-side device is determined by the dead-time design, but it is not affected by the resonant tank parameters. Therefore, the device losses are independent of the resonant tank design. For given output power, devices, and switching frequency, the device losses can be obtained using the dead-time design. The conduction losses of the devices can be easily calculated by (4). The losses can be normalized by the output power. P cond_loss_p and P cond_loss_s indicate the primary-side and secondary-side conduction losses, respectively. R dson_p and R dson_s indicate the turn-on resistances of the primary-side and secondary-side devices. P cond_p_norm and P cond_s_norm indicate the normalized primary-side and secondary-side conduction losses P cond_p_norm = P cond_loss_p P o = R dson_p R o ( Vo V in ) I RMS_P_norm P cond_s_norm = P cond_loss_s P o = R dson_s R o I RMS_S_norm. (7) Equation (5) shows the relationship between the dead time and turnoff current. The turnoff loss can be attained either by precise device simulation or by a circuit test. In this paper, the device turnoff loss is obtained by experimental measurement. A design example is given to show the proposed optimal design procedure. The design specifications are V in = 400 V, V o = 1 V, and P o = 50 W. The switching frequency is 800 khz for the sake of high power density. STB1NM50FD (C eq = 14 pf) and BSC014N03MSG are chosen as the primary- and secondary-side devices. Based on (5), (7), and the device test results, Fig. 5(a) shows the device loss percentage curves with variations in dead time. According to the 80 Plus requirement [1], high efficiency should be achieved at 0%, 50%, and 100% load conditions. A suitable value for the dead time should be chosen to satisfy the high efficiency requirement. Hence, a dead time that falls within the shaded area is recommended for better efficiency over a wide load range. Based on Fig. 5(a), a dead time of 170 ns is chosen. Once the optimal dead time is selected, (0) can be used to determine that L P =67.6 μh. Because the switching fre- Fig. 6. Peak gain curves of different combinations of Q and L n. (a) Peak gain for fixed L n. (b) Peak gain for different L n s. Fig. 7. Three-dimensional plots of the proposed design method. quency is 800 khz, the series resonant frequency f o is 1.1 MHz with the consideration of the dead time. For a given L P, the relationship between Q and L n can be expressed as Q (1 + L n) L n = L P ( Vo V in ) πf o R o. (8) In this case, Q (1 + L n ) /L n =.918 is obtained because L P =67.6 μh. The relationship between Q and L n is plotted in Fig. 5(b). To complete the resonant tank design, Q and L n should be determined. The holdup time operation requirement is another resonant tank design constraint. In general, for each Q, the maximum gain is achieved at the resonant ridge, as shown in Fig. 6(a). The peak gain curves of different L n s are drawn in Fig. 6(b). The peak gain decreases as Q increases when L n is fixed. Meanwhile, the peak gain increases as L n decreases for the same Q. Fig. 7 shows the peak gain surface for different values of Q and L n, as well as the gain plane of the holdup time operation constraint. In this design, the holdup time gain is adopted as 1.8. Thus, a peak gain surface higher than 1.8 can be considered. Equation (8) and Fig. 7 are determined by the high efficiency constraint, which should be recalled to finalize the resonant tank design. Fig. 7 shows the holdup time gain constraint and the high-efficiency operation constraint. The final optimal design point is located at the intersection of the three surfaces, which is where all requirements can be satisfied. If this design point moves up along the boundary line of the peak gain surface and the high-efficiency constraint surface, the voltage conversion range is enlarged and the efficiency of the converter

7 HUANG et al.: HIGH-FREQUENCY HIGH-EFFICIENCY CLL RESONANT CONVERTERS WITH SRs 3467 Fig. 8. Circuit stresses at different values of L n. (a) Primary-side peak current. (b) Peak voltage of resonant capacitor. Fig. 10. LLC resonant converter with integrated L m. Fig. 11. LLC resonant converter transformer. (a) Transformer structure. (b) FEA simulation result. Fig. 9. Design procedure of the CLL resonant converters. is kept the same. If this occurs, the impacts of design point selection should be studied further. During the holdup time operation, the primary-side peak current is normalized by the factor P o /0.5V in ; this current is plotted in Fig. 8(a). The maximum voltage gain is achieved close to the parallel resonant frequency f 0. The primary-side peak current at f 0 increases as L n increases. If L n 1, based on (3) and (7), it can be derived that L eq L and f 0 f 0 / L n. The frequency operation range during the holdup time also increases. In one switching cycle, the energy transfer period is close to T 0 due to the nature of resonance. If the switching frequency moves farther from the series resonant frequency, the effective energy transfer duty cycle is reduced, which results in a higher current. Roughly, the peak current is inversely proportional to f 0 or proportional to L n. Normalized by the factor 0.5V in, Fig. 8(b) shows how the peak voltage of the resonant capacitor changes during the holdup time operation. The peak voltage decreases as L n increases. Based on (4) (7), we know that C 1 is proportional to L n. Since the peak current is roughly proportional to L n during the holdup time, the increase in the capacitance is greater than the increase in the current going through the capacitor. Thus, the voltage stress decreases. Normally, a narrow frequency operation range and low current stress are preferred. Thus, the black dot in Fig. 7, where L n equals 17 and Q equals 0.153, is chosen as the optimal design point. According to () (8), the resonant tank parameters can be calculated as L 1 =74.06 μh, L =4.35 μh, and C 1 = 5.09 nf. Based on (11), the transformer turn ratio is 18 : 1. The optimal design procedure is summarized in Fig. 9. IV. TRANSFORMER DESIGN INVESTIGATION For the CLL resonant converter transformer design, two factors need to be taken into consideration. First, the magnetizing inductance of the transformer should be designed to be as high as possible. Second, the leakage inductance of the transformer could be utilized as L r. The basic configuration of the transformer is as follows: Litz wires are utilized as the primary-side winding for their ability to reduce the skin effect caused by high-frequency current. Printed circuit board (PCB) winding is utilized on the secondary side for the easy connection of high-current devices. As shown in Fig. 10, for a conventional LLC resonant converter, L m is usually integrated into the transformer with the insertion of an air gap. A discrete inductor is required for L r. However, the air gap will cause a high eddy current in the PCB windings and, hence, high winding loss [16]. The LLC resonant converter transformer structure is shown in Fig. 11(a), where the rounded winding is the primary-side litz wire and the center two plates are the secondary-side PCB winding. The primary-side and secondary-side windings are interleaved for lower ac winding loss. The thickness of the core is mm (from the inner side to the outer side), and the window area of the core is 50 mm. The width of the PCB copper is 7 mm, and it has a weight of 4 oz. The diameter of the litz wire is 0.5 mm (AWG 4). We chose Maxwell -D-based finite element analysis (FEA) to investigate the winding loss. The secondary PCB winding loss is.89 W (3.1% of the system loss) for a 50-W LLC transformer with an air gap. Fig. 11(b) shows a large eddy current that occurs at the edges of the copper plates near the air gaps. For the CLL resonant converter transformer design, there is no need to utilize magnetizing inductance (as shown in Fig. 1). Thus, air gaps and the associated fringing effect can be eliminated. The optimal design of the separate L 1 for small size and high efficiency can be achieved easily. The next issue

8 3468 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 011 Fig. 1. CLL resonant converter transformer without interleaving windings. (a) Transformer structure. (b) FEA simulation result. Fig. 13. CLL resonant converter transformer with interleaving windings. (a) Transformer structure. (b) FEA simulation result. is determining how to integrate L into the transformer without suffering too much loss. Fig. 1(a) shows the transformer structure without interleaving, and Fig. 1(b) shows the FEA simulation results. Without an interleaving structure, the secondary PCB conduction loss is.8 W (.6% of the system loss), and the leakage inductance is 4.14 μh. The transformer structure with interleaving is shown in Fig. 13(a), and the FEA simulation results are shown in Fig. 13(b). The conduction loss is 1.59 W (1.7% of the whole system loss), and the leakage inductance is 1.94 μh. The interleaving structure of the transformer makes the magnetomotive force (MMF) more evenly distributed but with a significant reduction of the leakage inductance. The leakage inductance is mainly generated by the magnetic energy stored in the space between the primary-side and secondary-side windings. In an interleaving structure, the energy is small due to low MMF. To increase the leakage inductance, a magnetic shunt with higher permeability is adopted. A ferrite polymer composite (FPC) film with μ r =9is used as a magnetic shunt. Fig. 14(a) shows the transformer with an interleaving structure and a magnetic shunt. The FEA simulation results are shown in Fig. 14(b). The two gray bars between the primaryside and secondary-side windings represent the magnetic shunt layers. The conduction loss of the secondary PCB winding is 1.74 W (13.9% of the system loss), and the leakage inductance is 3.89 μh. The leakage inductance of the transformer with magnetic shunts is double that of the transformer without magnetic shunts. The magnetic shunt layers attract more leakage flux. However, due to limited permeability, the induced leakage flux bends slightly. The leakage flux induces an eddy current at the edge of the copper plates. Fortunately, the leakage flux is very low. Thus, only a 0.15-W loss is added, which is acceptable for a 50-W converter. Fig. 14. CLL resonant converter transformer with interleaving windings and magnetic shunt. (a) Transformer structure. (b) FEA simulation result. Based on the aforementioned analysis and comparison, the proposed transformer structure is very suitable for the CLL resonant converter. For the planar transformer, it may not be favorable to integrate the magnetizing inductance due to the severe fringing effect. However, the leakage inductance can be easily integrated without an apparent sacrifice in performance. The proposed CLL resonant converter can fully utilize the optimal integration solution of the magnetic components, which is an inherent merit of this topology. V. S YNCHRONOUS RECTIFICATION DRIVING SCHEME For conventional LLC resonant converters, it is not easy to apply a current-drive SR. Otherwise, discrete magnetic components should be applied. Unlike existing LLC resonant converters, the magnetizing inductance of the proposed CLL resonant converter is very large. The impact of the phase mismatch between the primary-side and secondary-side currents of the transformer can be ignored. Thus, the transformer s primaryside current can be utilized directly to drive the SR. Fig. 15(a) shows a diagram of the SR driving scheme, and Fig. 15(b) shows the schematic of the SR driving circuit. A CT is used to sense the primary-side current, and comparators and simple peripheral circuits are utilized as Schmitt triggers. Unlike the conventional LLC resonant converter, there is no conflict between the current-driven SR and the integration of magnetic components. This is another inherent benefit of the proposed CLL resonant converter. VI. EXPERIMENTAL RESULTS A 50-W 800-kHz 400-V/1-V CLL resonant converter prototype is built to verify the theoretical analysis and the proposed design strategies. The resonant parameters are designed as follows: L 1 =73μH, L =4.4 μh, and C 1 =5nF. The transformer turn ratio is 18 : 1 : 1. The core material is 3F45. L is integrated with the transformer. The relative permeability of the FPC is nine. For L 1 [17], an RM8/ILP with 3F45 is chosen, and 4-turn AWG-6 litz wires are used. The power density of the prototype is 94.6 W/in 3. The part number of the primary-side and secondary-side devices are STB1NM50FD and BSC014N03MSG, respectively. Fig. 16(a) shows the experimental results of the CLL resonant converter at a no-load condition. ZVS is achieved during the dead time between the marked lines. V ds_s1 and V ds_s are the drain source voltages of S 1 and S, respectively. V gs_s1 and V gs_s are the gate source voltages of S 1 and S, respectively.

9 HUANG et al.: HIGH-FREQUENCY HIGH-EFFICIENCY CLL RESONANT CONVERTERS WITH SRs 3469 Fig. 15. CLL resonant converter with SR driving scheme. (a) CLL resonant converter. (b) Schematic of SR driving scheme. Fig. 16. Experimental waveforms of prototype. (a) 400 V/1 V, no load. (b) 400 V/1 V, 50-W full load. When the drain source voltage drops to zero, the gate signal starts to drive. The dead time is 160 ns, and the turnoff current is around 0.68 A. Fig. 16(b) shows the experimental results of the CLL resonant converter at the full-load condition. V Q is the driving signal of Q. V dsq represents the drain source voltage of Q. The primary-side current i L has the same shape as the secondary-side current, but it has a different amplitude due to the turn ratio. i L is in a sinusoidal shape. As the dotted line indicates, V dsq begins to rise just at the zero-cross point of the sinusoidal current. Hence, ZCS is achieved. It can also be observed that the SR body-diode conduction time is almost eliminated. The experimental efficiency curve of the prototype is shown in Fig. 17. The efficiency at a half load is 96.7%, and at a full load, it is 96.1%. The holdup time capacitor is 56 μf fora 50-W converter, and the input voltage range is V. The voltage ripple is around ±15 V. Based on this voltage ripple, the switching frequency range is khz. Based on calculation, the efficiency at 75, 800, and 900 khz (fixed frequency) is 95.9%, 96.3%, and 95.7%, respectively. As the frequency variation is not significant, the efficiency of the converter will change little. The proposed optimal design procedure is valid. A detailed loss breakdown under full-load conditions is shown in Table I. VII. CONCLUSION This paper has proposed a high-frequency high-efficiency CLL resonant converter. The characteristics of the CLL resonant converter are analyzed, and the operation regions of Fig. 17. Measured efficiency curve for the constructed CLL resonant converter. TABLE I LOSS BREAKDOWN OF THE HARDWARE UNDER FULL LOAD the CLL resonant converter are discussed. Recognizing that dead time is a critical factor that influences the entire system design and using thorough investigation, an optimal design methodology is proposed to achieve high efficiency over a wide load range. An optimal transformer structure for the CLL resonant converter is proposed to achieve low winding loss and to have the capability of magnetic integration, and an easily implemented current-type SR driving scheme is proposed to achieve low SR losses. An 800-kHz 50-W CLL resonant converter prototype is built to verify the benefits of the proposed CLLresonant converters, and over a 96% efficiency is achieved for the wide load conditions of interest. The proposed CLL resonant converter is a good candidate for next-generation highfrequency high-efficiency high-power-density power supplies.

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Nandakumar, Class D voltage-switching inverter with tapped resonant inductor, Proc. Inst. Elect. Eng. B, vol. 140, no. 3, pp , May Daocheng Huang received the B.S. and M.S. degrees from the Huazhong University of Science and Technology, Wuhan, China. He is currently working toward the Ph.D. degree at Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg. His research interests include high-frequency power conversion, soft switching techniques, magnetic design, passive integration, distributed power systems, and telecom power conversion techniques. Dianbo Fu (M 09) received the B.S. degree from the Huazhong University of Science and Technology, Wuhan, China, and the M.S. and Ph.D. degrees from Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg. Since 010, he has been with Huawei Technologies, Plano, TX, where he has been engaged in product design, research, and development. He is the holder of two U.S. patents and has three U.S. patents pending. His research interests include high-frequency power conversion, soft switching techniques, magnetic design, electromagnetic interference, distributed power systems, and telecom power conversion techniques. Fred C. Lee (S 7 M 74 SM 87 F 90) received the B.S. degree in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1968, the M.S. and Ph.D. degrees in electrical engineering from Duke University, Durham, NC, in 197 and 1974, respectively. He is a University Distinguished Professor with Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg. He directs the Center for Power Electronics Systems, a National Science Foundation engineering research center. He is the holder of 35 U.S. patents and has published over 00 journal articles and more than 500 technical papers in conference proceedings. His research interests include high-frequency power conversion, distributed power systems, electronics packaging, and modeling and control. Pengju Kong (M 08) received the B.S.E.E. and Ph.D. degrees from Tsinghua University, Beijing, China, in 003 and 009, respectively. He is currently a Postdoctoral Associate with the Center for Power Electronics Systems, Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg. His research interests include electromagnetic interference/electromagnetic compatibility in power electronics systems, magnetics, and micro grid.