Module 2.B. 9S12C Multiplexed Bus Expansion. Tim Rogers 2017

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1 Module 2.B 9S12C Multiplexed Bus Expansion Tim Rogers 2017

Learning Outcome #2 An ability to interface a microcontroller to various devices How? A+B are the most complex interface we will study in 362 A. Bus Timing Analysis B.

2 Learning Outcome #2 An ability to interface a microcontroller to various devices How? A+B are the most complex interface we will study in 362 A. Bus Timing Analysis B. 9S12C Multiplexed Bus Expansion C. General-Purpose I/O Ports D. Buffered I/O Handling E. Interrupt Handling F. Buffered, Interrupt-Driven Printer Design Example [2.B]-2

3 Some Introduction Single Chip Mode (just use internal SRAM). Expanded Mode (Can hook up external SRAM and turn on internal visibility ) The expanded data bus can be 8-bits ( narrow mode ) or 16- bits ( wide mode ) Signals of interest include the following: Port A high byte of address/data (wide mode) or high byte of address/8-bit data (narrow mode) Port B low byte of address/data (wide mode) Port E bus control signals E bus clock (used to de-multiplex the address and data) R/W read/write enable LSTRB low byte strobe (used to distinguish word writes from byte writes in wide mode) By Default: 9S12 is Normal Single Chip Mode (no signals visible) For HW 5 Q 3 and 4: Normal Expanded Narrow Mode used. With internal visibility turned on. Internal visibility: We can see what is happening on the internal bus as well as the external one For Lab 5: Normal Expanded Wide Mode used. With internal visibility turned on. [2.B]-3

B CPU External Memory Chip R/W Output Enable (OE) CLK Write Enable (WE) 2.

4 High-level Picture of External Memory Address Bus (Abus) Data Bus (Dbus) M-bits / N-bits / Upper-most bits / Address Decode PLD Chip Enable (CE) Address (in) Data (in/out) 2.B CPU External Memory Chip R/W Output Enable (OE) CLK Write Enable (WE) 2.A Only one bus for Address and Data Bus is Multiplexed : 1 st half of clock cycle: do address 2 nd half of clock cycle: send data [2.B]-4

5 Figure 1 of AN2408 [2.B]-5

6 Schematic Based on PLD PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA7 PA6 PA5 PA4 PA3 PA2 ECLK RW I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 TDI CLK0/I0 CLK1/I1 TCK TMS M4_32/FP44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O TDO 29 PA1 PA A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 OE WE CE VCC CY7C 199 D0 D1 D2 D3 D4 D5 D6 D PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Note: Schematic is based on pin assignments generated automatically by the fitter for this PLD. [2.B]-6

7 Interface Logic ABEL source file available on Homework page Port A will be used for data on 2 nd half of clock cycle. Latch it on the 1 st half. Same logic for OE and WE that we saw in simple examples MODULE mem9s12c TITLE '9S12C Memory Interface' DECLARATIONS PA0..PA7 pin; " MCU Port A ECLK pin; " MCU E-clock RW pin; " MCU Read/Write!CS,!OE,!WE pin istype 'com'; LA8..LA15 pin istype 'reg_d'; " demultiplexed address EQUATIONS [LA8..LA15].D = [PA0..PA7]; [LA8..LA15].CLK = ECLK; CS =!LA15.Q & ECLK; " map SRAM into lower half of address space OE = RW & ECLK; WE =!RW & ECLK; END CS = CE: Only asserted when uppermost bit is 0. [2.B]-7

8 Fitter Report (Summary) [2.B]-8

9 Critical Path Analysis: OE and WE These are the combinational output delay paths (pertinent for OE and WE). [2.B]-9

10 Critical Path Analysis: Latched Address These are the clock edge to latched output delay paths (where ECLK provides the clock edge). Note that the latched (de-multiplexed) address bus is valid 4 ns following the low-to-high ECLK transition; the CS signal, which here is dependent on LA15 and being gated with ECLK, is valid 7.5 ns following the low-to-high ECLK transition. [2.B]-10

11 9S12C Bus Signals Note: These signals are not available on the 9S12C32 [2.B]-11

12 9S12C A.C. Specifications (Sample) [2.B]-12

13 9S12C General External Bus Timing This figure combines what happens read and write diagrams Bus on Read Bus on Write address phase [2.B]-13

14 9S12C General External Bus Timing address phase [2.B]-14

15 9S12C General External Bus Timing address phase data phase [2.B]-15

16 9S12C General External Bus Timing point at which address is externally latched address phase data phase [2.B]-16

17 9S12C A.C. Specifications (Sample) [2.B]-17

18 9S12C General External Bus Timing t CY [2.B]-18

19 9S12C A.C. Specifications (Sample) [2.B]-19

20 9S12C General External Bus Timing t CY t AD [2.B]-20

21 9S12C A.C. Specifications (Sample) [2.B]-21

22 9S12C General External Bus Timing t CY t AD t MAH [2.B]-22

23 9S12C A.C. Specifications (Sample) [2.B]-23

24 9S12C General External Bus Timing t CY t AD t DSR t DHR t MAH [2.B]-24

25 9S12C A.C. Specifications (Sample) [2.B]-25

26 9S12C General External Bus Timing t CY t AD t DSR t DHR t MAH t DDW [2.B]-26

27 9S12C A.C. Specifications (Sample) [2.B]-27

28 9S12C General External Bus Timing t CY t AD t DSR t DHR t MAH t DDW t DHW [2.B]-28

29 9S12C A.C. Specifications (Sample) [2.B]-29

30 9S12C General External Bus Timing t CY t AD t DSR t DHR t MAH t DDW t DSW t DHW input setup time (t IS ) available on write [2.B]-30

31 9S12C A.C. Specifications (Sample) [2.B]-31

32 9S12C General External Bus Timing t CY t AD t ACCA t DSR t DHR t MAH t DDW t DSW t DHW input setup time (t IS ) available on write address access time (t AA ) available on read [2.B]-32

33 9S12C A.C. Specifications (Sample) [2.B]-33

34 9S12C General External Bus Timing t CY t AD t ACCA t DSR t DHR t MAH t DDW t DSW t DHW Note: trwd!= tad For expanded bus t RWD input setup time (t IS ) available on write address access time (t AA ) available on read [2.B]-34

35 9S12C A.C. Specifications (Sample) [2.B]-35

36 9S12C General External Bus Timing t CY t AD t ACCA t DSR t DHR t MAH t DDW t DSW t DHW t RWD t RWH input setup time (t IS ) available on write address access time (t AA ) available on read [2.B]-36

37 9S12C CPU Read/Write Timing Diagram t CYC = 40 ns [2.B]-37

38 9S12C CPU Read/Write Timing Diagram t CYC = 40 ns t AD = 8 ns Addr t MAH = 2 ns Addr Addr [2.B]-38

39 9S12C CPU Read/Write Timing Diagram t CYC = 40 ns Read Data t AD = 8 ns Addr t MAH = 2 ns Read Data t DSR = 13 ns Addr t DHR = 0 ns Addr [2.B]-39

40 9S12C CPU Read/Write Timing Diagram t CYC = 40 ns t AD = 8 ns t DSR = 13 ns t DDW = 7 ns Read Data Addr t MAH = 2 ns Read Data Addr t DHR = 0 ns Write Data Addr t DHW = 2 ns [2.B]-40

41 9S12C CPU Read/Write Timing Diagram t CYC = 40 ns Read Data t AD = 8 ns Addr t MAH = 2 ns Read Data t DSR = 13 ns Addr t DHR = 0 ns t DDW = 7 ns Write Data??? t RWD = 7 ns t RWH = 2 ns Addr t DHW = 2 ns Spoiler alert this is the solution to problem 2 on homework 5 [2.B]-41

42 MSO Display for Experiment 5 Demo Code ECLK R/W LSTRB PB0 LA15-LA0 PA0-7 PB0-7 [2.B]-42

43 Potential Design Question Given: 9S12 operating with/without stretch A specific PLD you can get timings for + abel file with associated with with logic A specific SRAM part with the data sheet Determine: Does this setup violate setup/hold times What is the read margin What is the maximum clock rate you can sustain and still achieve 10% margin. When calculating margin as a percent, it is a percent of what? The SRAM timing parameter that is determining the critical path [2.B]-43

44 Example Timing Diagram [2.B]-44

45 9S12 Configurable Memory Map Out of reset, SRAM is mapped to 800-FFF Out of reset, Flash is mapped to 8000-FFFF [2.B]-45

46 Configuration Registers 9212 CPU registers are A, B, D, SP, PC, X and Y THESE HAVE NOTHING TO DO WITH THE CONFIGURATION REGISTERS There when we use the microcontroller there is a lot of setup/initialization of the CPU/Peripherals/Pins etc We control these via memory mapped registers or configuration registers A portion of the address space is devoted to these registers and when you write to these locations the value doesn t actually go to memory is goes to a configuration register [2.B]-46

47 9S12 Configurable Memory Map This is the space devoted to configuration registers To maximize space, configuration is often done on a bit-by-bit basis. [2.B]-47

48 Our first (of many) configuration registers INITRM Register (initializes SRAM position in memory) INITRM Register (8-bits) Memory location: $11 Bits 7-3 named: RAM15-RAM11 Recall: only 2k (11-bits) worth of internal SRAM on the 9S12 These bits specify the upper 5 bits of the SRAM address. Out of reset these bits are 00001b So by default - SRAM mapped to: b to b or $800 to $FFF [2.B]-48

49 Can use other confirmation registers to remap all regions If conflicts occur, the following precedence applies: register space internal SRAM byte-erasable EEPROM (not on 9S12C32) flash external memory [2.B]-49

HD44102D. (Dot Matrix Liquid Crystal Graphic Display Column Driver) Features. Description. Ordering Information

HD44102D. (Dot Matrix Liquid Crystal Graphic Display Column Driver) Features. Description. Ordering Information HD442 (Dot Matrix Liquid Crystal Graphic Display Column Driver) Description The HD442 is a column (segment) driver for dot matrix liquid crystal graphic display systems, storing the display data transferred