Double Data Rate (DDR) SDRAM MT46V128M4 32 Meg x 4 x 4 Banks MT46V64M8 16 Meg x 8 x 4 Banks MT46V32M16 8 Meg x 16 x 4 Banks

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1 Double Data Rate DDR SDRAM MT46V28M4 32 Meg x 4 x 4 Banks MT46V64M8 6 Meg x 8 x 4 Banks MT46V32M6 8 Meg x 6 x 4 Banks 52Mb: x4, x8, x6 DDR SDRAM Features Features VDD = +2.5V ±.2V, VD = +2.5V ±.2V VDD = +2.6V ±.V, VD = +2.6V ±.V DDR4 Bidirectional data strobe transmitted/ received with data, i.e., source-synchronous data capture x6 has two one per byte Internal, pipelined double-data-rate DDR architecture; two data accesses per clock cycle Differential clock inputs and # Commands entered on each positive edge edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align and transitions with Four internal banks for concurrent operation Data mask DM for masking write data x6 has two one per byte Programmable burst lengths: 2, 4, or 8 Auto refresh and self refresh modes Longer-lead TSOP for improved reliability OCPL 2.5V I/O SSTL_2 compatible Concurrent auto precharge option is supported t RAS lockout supported t RAP = t RCD Options Notes:. End of life. Marking Configuration 28 Meg x 4 32 Meg x 4 x 4 banks 28M4 64 Meg x 8 6 Meg x 8 x 4 banks 64M8 32 Meg x 6 8 Meg x 6 x 4 banks 32M6 Plastic package 66-pin TSOP TG 66-pin TSOP Pb-free P 6-ball FBGA mm x 2.5mm FN 6-ball FBGA mm x 2.5mm Pb-free BN Timing cycle time CL = 3 DDR4B -5B CL = 2.5 DDR333 FBGA only -6 CL = 2.5 DDR333 TSOP only -6T CL = 2 DDR266-75E CL = 2 DDR266A -75Z CL = 2.5 DDR266B -75 Self refresh Standard None Low-power self refresh L Temperature rating Commercial C to +7 C None Industrial 4 C to +85 C IT Revision x4, x8 :D x4, x8, x6 :F Table : Key Timing Parameters CL = CAS READ latency; data-out window is MIN clock rate with 5% duty cycle at CL = 2, CL = 2.5, or CL = 3 Speed Grade Clock Rate MHz CL = 2 CL = 2.5 CL = 3 Data-Out Window Access Window Skew -5B ns ±.7ns +.4ns n/a 2.ns ±.7ns +.4ns 6T n/a 2.ns ±.7ns +.45ns -75E/-75Z n/a 2.5ns ±.75ns +.5ns n/a 2.5ns ±.75ns +.5ns 52Mb_DDR_x4x8x6_D.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 2 Micron Technology, Inc. All rights reserved.

2 Features Table 2: Addressing Parameter 28 Meg x 4 64 Meg x 8 32 Meg x 6 Configuration 32 Meg x 4 x 4 banks 6 Meg x 8 x 4 banks 8 Meg x 6 x 4 banks Refresh count 8K 8K 8K Row address 8K A A2 8K A A2 8K A A2 Bank address 4 BA, BA 4 BA, BA 4 BA, BA Column address 4K A A9, A, A2 2K A-A9, A K A A9 Table 3: Speed Grade Compatibility Marking PC PC PC PC PC PC B Yes Yes Yes Yes Yes Yes -6 Yes Yes Yes Yes Yes -6T Yes Yes Yes Yes Yes -75E Yes Yes Yes Yes -75Z Yes Yes Yes -75 Yes Yes -5B -6/-6T -75E -75Z Notes:. The -5B device is backward compatible with all slower speed grades. The voltage range of -5B device operating at slower speed grades is Vdd = VddQ = 2.5V ±.2V. Figure : 52Mb DDR SDRAM Part Numbers Example Part Number: MT46V32M6P-6T:F - : Sp. MT46V Configuration Package Speed Op. Temp. Revision Revision :D x4, x8 Configuration 28 Meg x 4 28M4 64 Meg x 8 64M8 32 Meg x 6 32M6 Package 4-mil TSOP 4-mil TSOP Pb-free mm x 2.5mm FBGA mm x 2.5mm FBGA Pb-free TG P FN BN -5B L IT :F Special Options Standard Low power Speed Grade t = 5ns, CL = 3 x4, x8, x6 Operating Temp Commercial Industrial temp -6 t = 6ns, CL = 2.5-6T t = 6ns, CL = E t = 7.5ns, CL = 2-75Z t = 7.5ns, CL = 2-75 t = 7.5ns, CL = 2.5 FBGA Part Number System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron s Web site: 52Mb_DDR_x4x8x6_D.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 2 2 Micron Technology, Inc. All rights reserved.

3 Table of Contents Table of Contents State Diagram Functional Description General Notes Functional Block Diagrams Pin and Ball Assignments and Descriptions Package Dimensions Electrical Specifications IDD Electrical Specifications DC and AC Notes Commands DESELECT NO OPERATION NOP LOAD MODE REGISTER LMR ACTIVE ACT READ WRITE PRECHARGE PRE BURST TERMINATE BST AUTO REFRESH AR SELF REFRESH Operations INITIALIZATION REGISTER DEFINITION ACTIVE READ WRITE PRECHARGE AUTO REFRESH SELF REFRESH Power-down E Not Active Mb_DDRTOC.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 3 2 Micron Technology, Inc. All rights reserved.

4 State Diagram State Diagram Figure 2: Simplified State Diagram Power applied Power on PRE Precharge all banks LMR REFS Self refresh MR EMR LMR Idle all banks precharged REFSX REFA EL Auto refresh EH Active powerdown E HIGH ACT Precharge powerdown E LOW Row active Burst stop WRITE Write WRITE WRITE A READ A READ READ BST Read READ WRITE A READ A READ A Write A PRE PRE PRE Read A PRE Precharge PREALL Automatic sequence Command sequence ACT = ACTIVE BST = BURST TERMINATE EH = Exit power-down EL = Enter power-down EMR = Extended mode register LMR = LOAD MODE REGISTER MR = Mode register PRE = PRECHARGE PREALL = PRECHARGE all banks READ A = READ with auto precharge REFA = AUTO REFRESH REFS = Enter self refresh REFSX = Exit self refresh WRITE A = WRITE with auto precharge Note: This diagram represents operations within a single bank only and does not capture concurrent operations in other banks. DDR_x4x8x6_Core.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 4 2 Micron Technology, Inc. All rights reserved.

5 Functional Description 52Mb: x4, x8, x6 DDR SDRAM Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. A bidirectional data strobe is transmitted externally, along with data, for use in data capture at the receiver. is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. is edge-aligned with data for READs and center-aligned with data for WRITEs. The x6 offering has two data strobes, one for the lower byte and one for the upper byte. The DDR SDRAM operates from a differential clock and #; the crossing of going HIGH and # going LOW will be referred to as the positive edge of. Commands address and control signals are registered at every positive edge of. Input data is registered on both edges of, and output data is referenced to both edges of, as well as to both edges of. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which may then be followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs are SSTL_2, Class II compatible. General Notes The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. Throughout the data sheet, the various figures and text refer to s as. The term is to be interpreted as any and all collectively, unless specifically stated otherwise. Additionally, the x6 is divided into two bytes, the lower byte and upper byte. For the lower byte 7 DM refers to LDM and refers to L. For the upper byte 8 5 DM refers to UDM and refers to U. Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. Any specific requirement takes precedence over a general statement. DDR_x4x8x6_Core.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 5 2 Micron Technology, Inc. All rights reserved.

6 Functional Block Diagrams 52Mb: x4, x8, x6 DDR SDRAM Functional Block Diagrams The 52Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,87,92 bits. It is internally configured as a 4-bank DRAM. Figure 3: 28 Meg x 4 Functional Block Diagram E # CS# WE# CAS# RAS# COMMAND DECODE CONTROL LOGIC BANK3 BANK2 BANK MODE REGISTERS 5 REFRESH COUNTER 3 3 ROW- ADDRESS MUX 3 BANK ROW- ADDRESS 892 LATCH & DECODER BANK MEMORY ARRAY 8,92 x 2,48 x 8 4 DATA DLL SENSE AMPLIFIERS 8 READ LATCH 4 MUX 4 DRVRS A A2, BA, BA 5 ADDRESS REGISTER BANK CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH I/O GATING DM MASK LOGIC 248 x8 COLUMN DECODER WRITE FIFO & DRIVERS Out In COL MASK 2 8 DATA COL GENERATOR INPUT REGISTERS RCVRS 3 DM 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 6 2 Micron Technology, Inc. All rights reserved.

7 Functional Block Diagrams Figure 4: 64 Meg x 8 Functional Block Diagram E # CS# WE# CAS# RAS# COMMAND DECODE CONTROL LOGIC BANK3 BANK2 BANK MODE REGISTERS 5 REFRESH 3 COUNTER 3 ROW- ADDRESS MUX 3 BANK ROW- ADDRESS 892 LATCH & DECODER BANK MEMORY ARRAY 8,92 x,24 x 6 8 DATA DLL SENSE AMPLIFIERS 6 READ LATCH 8 MUX 8 DRVRS A A2, BA, BA 5 ADDRESS REGISTER 2 2 BANK CONTROL LOGIC 6384 I/O GATING DM MASK LOGIC 24 x6 COLUMN DECODER 6 6 COL MASK WRITE FIFO 2 & DRIVERS 6 Out In DATA GENERATOR INPUT REGISTERS RCVRS 7 DM COLUMN- ADDRESS COUNTER/ LATCH COL Figure 5: 32 Meg x 6 Functional Block Diagram E # CS# WE# CAS# RAS# COMMAND DECODE CONTROL LOGIC REFRESH COUNTER BANK BANK2 BANK3 3 MODE REGISTERS 5 3 ROW- ADDRESS MUX 3 BANK ROW- ADDRESS 892 LATCH & DECODER BANK MEMORY ARRAY 8,92 x 52 x 32 6 DATA DLL SENSE AMPLIFIERS 32 READ LATCH 6 MUX 6 DRVRS 6384 GENERATOR 2 5 A A2, BA, BA 5 ADDRESS REGISTER 2 2 BANK CONTROL LOGIC I/O GATING DM MASK LOGIC 52 x32 COLUMN DECODER COL MASK WRITE FIFO 4 & DRIVERS 32 Out In DATA INPUT REGISTERS RCVRS L, U LDM, UDM COLUMN- ADDRESS COUNTER/ LATCH 9 COL 2 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 7 2 Micron Technology, Inc. All rights reserved.

8 Pin and Ball Assignments and Descriptions 52Mb: x4, x8, x6 DDR SDRAM Pin and Ball Assignments and Descriptions Figure 6: 66-Pin TSOP Pin Assignment Top View x4 x8 x6 x6 x8 x4 VDD VD VSSQ 2 VD 3 VSSQ VD VDD DNU WE# CAS# RAS# CS# BA BA VDD VD 2 VSSQ 3 4 VD 5 6 VSSQ 7 VD L VDD DNU LDM WE# CAS# RAS# CS# BA BA VSS 5 VSSQ 4 3 VD 2 VSSQ 9 VD 8 VSSQ U DNU VREF VSS UDM # E A2 A A9 VSS 7 VSSQ 6 VD 5 VSSQ 4 VD VSSQ DNU VREF VSS DM # E A2 A A9 A/AP A/AP A8 A8 A A A2 A3 VDD A A A2 A3 VDD A7 A6 A5 A4 VSS A7 A6 A5 A4 VSS VSS VDD NF VD VSSQ NF VD VSSQ VD VDD DNU WE# CAS# RAS# CS# BA BA A/AP A A A2 A3 VDD VSS NF VSSQ 3 VD NF VSSQ 2 VD VSSQ DNU VREF VSS DM # E A2 A A9 A8 A7 A6 A5 A4 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 8 2 Micron Technology, Inc. All rights reserved.

9 Pin and Ball Assignments and Descriptions Figure 7: 6-Ball FBGA Ball Assignment Top View VSSQ VREF NF VD VSSQ VD VSSQ VSS A2 A A8 A6 A4 VSS 3 NF 2 DM # E A9 A7 A5 VSS x4 Top View A B C D E F G H J K L M VDD NF WE# RAS# BA A A2 VDD NF VSSQ VD VSSQ VD VDD CAS# CS# BA A A A3 VD DNU VSSQ VREF x8 Top View VD VSSQ VD VSSQ VSS A2 A A8 A6 A4 VSS DM # E A9 A7 A5 VSS A B C D E F G H J K L M VDD 2 3 WE# RAS# BA A A2 VDD VSSQ VD VSSQ VD VDD CAS# CS# BA A A A3 VD DNU VSSQ VSS A2 A A8 A6 A4 x6 Top View VD VSSQ VD VSSQ VSS 3 9 U A B C D E VDD L VSSQ VD VSSQ VD VREF UDM F LDM # G WE# E H RAS# A9 J BA A7 K A A5 L A2 VSS M VDD VDD CAS# CS# BA A A A3 VD DNU 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 9 2 Micron Technology, Inc. All rights reserved.

10 Pin and Ball Assignments and Descriptions Table 4: Pin and Ball Descriptions FBGA Numbers K7, L8, L7, M8, M2, L3, L2, K3, K2, J3, K8, J2, H2 TSOP Numbers Symbol Type Description 29, 3, 3, 32, 35, 36, 37, 38, 39, 4, 28 4, 42 A, A, A2, A3, A4, A5, A6, A7, A8, A9, A, A, A2 Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit A for READ/WRITE commands, to select one location out of the memory array in the respective bank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A LOW, bank selected by BA, BA or all banks A HIGH. The address inputs also provide the op-code during a LOAD MODE REGISTER command. J8, J7 26, 27 BA, BA Input Bank address inputs: BA and BA define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA and BA also define which mode register mode register or extended mode register is loaded during the LOAD MODE REGISTER LMR command. G2, G3 45, 46, # Input Clock: and # are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of and negative edge of #. Output data and is referenced to the crossings of and #. H3 44 E Input Clock enable: E HIGH activates and E LOW deactivates the internal clock, input buffers, and output drivers. Taking E LOW provides PRECHARGE POWER-WN and SELF REFRESH operations all banks idle, or ACTIVE POWER-WN row ACTIVE in any bank. E is synchronous for POWER-WN entry and exit, and for SELF REFRESH entry. E is asynchronous for SELF REFRESH exit and for disabling the outputs. E must be maintained HIGH throughout read and write accesses. Input buffers excluding, #, and E are disabled during POWER-WN. Input buffers excluding E are disabled during SELF REFRESH. E is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until E is first brought HIGH, after which it becomes a SSTL_2 input only. H8 24 CS# Input Chip select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. F3 F7, F3 H7, G8, G7 A8, B9, B7, C9, C7, D9, D7, E9, E, D3, D, C3, C, B3, B, A2 A8, B7, C7, D7, D3, C3, B3, A2 B7, D7, D3, B3 47 2,47 23, 22, 2 2, 4, 5, 7, 8,,, 3, 54, 56, 57, 59, 6, 62, 63, 65 2, 5, 8,, 56, 59, 62, 65 5,, 56, 62 DM LDM, UDM RAS#, CAS#, WE# , Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a write access. DM is sampled on both edges of. Although DM pins are input-only, the DM loading is designed to match that of and pins. For the x6, LDM is DM for 7 and UDM is DM for 8 5. Pin 2 is a on x4 and x8. Input Command inputs: RAS#, CAS#, and WE# along with CS# define the command being entered. I/O Data input/output: Data bus for x6. I/O Data input/output: Data bus for x8. I/O Data input/output: Data bus for x4. 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 2 Micron Technology, Inc. All rights reserved.

11 Pin and Ball Assignments and Descriptions Table 4: Pin and Ball Descriptions continued FBGA Numbers E3 E7 E L U I/O Data strobe: Output with read data, input with write data. is edgealigned with read data, centered in write data. It is used to capture data. For the x6, L is for 7 and U is for 8 5. Pin 6 E7 is on x4 and x8. F8, M7, A7, 8, 33 VDD Supply Power supply: +2.5V ±.2V. +2.6V ±.V for DDR4. B2, D2, C8, E8, A9 3, 9, 5, 55, 6 VD Supply power supply: +2.5V ±.2V +2.6V ±.V for DDR4. Isolated on the die for improved noise immunity. F 49 VREF Supply SSTL_2 reference voltage. A3, F2, M3 34, 48, 66 VSS Supply Ground. A, C2, E2, 6, 2, 52, VSSQ Supply ground: Isolated on the die for improved noise immunity. B8, D8 58, 64 4, 7, 25, 43, 53 No connect for x6: These pins should be left unconnected. B, B9, C, C9, D, D9, E, E7, E9, F7 B, B9, C, C9, D, D9, E, E7, E9, F7 A2, A8, C3, C7 TSOP Numbers Symbol Type Description 4, 7,, 3, 4, 6, 7, 2, 25, 43, 53, 54, 57, 6, 63 No connect for x8: These pins should be left unconnected. 4, 7,, 3, No connect for x4: These pins should be left unconnected. 4, 6, 7, 2, 25, 43, 53, 54, 57, 6, 63 2, 8, 59, 65 NF No function for x4: These pins should be left unconnected. F9 9, 5 DNU Do not use: Must float to minimize noise on VREF. Table 5: Reserved Pin and Ball Descriptions pins not listed may also be reserved for other uses; this table defines pins of importance TSOP Numbers Symbol Type Description 7 A3 Input Address input A3 for Gb devices. 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 2 Micron Technology, Inc. All rights reserved.

12 Package Dimensions Package Dimensions Figure 8: 66-Pin Plastic TSOP 4 mil ±.8 SEE DETAIL A.65 TYP.7. 2X.32 ±.75 TYP.76 ±.2.6 ±.8 PIN # ID GAGE PLANE.25.2 MAX TYP.5 ±. DETAIL A Notes:. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is.25mm per side. 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 2 2 Micron Technology, Inc. All rights reserved.

13 Package Dimensions Figure 9: 6-Ball FBGA mm x 2.5mm.85 ±.5 SEATING PLANE. C C 6X Ø.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø TYP.8 CTR BALL A BALL A ID SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3% Ag,.5% Cu SOLDER BALL PAD: Ø.33 NON SOLDER MASK DEFINED SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL A9. TYP 6.25 ±.5 BALL # ID. 5.5 ±.5 C L 2.5 ±. C L 3.2 ±.5 5. ±.5. ±..2 MAX Notes:. All dimensions are in millimeters. 2. Topside part marking decoder can be found on Micron s Web site. 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 3 2 Micron Technology, Inc. All rights reserved.

14 Electrical Specifications IDD Electrical Specifications IDD Table 6: IDD Specifications and Conditions x4, x8 VD = +2.6V ±.V, VDD = +2.6V ±.V -5B; VD = +2.5V ±.2V, VDD = +2.5V ±.2V -6, -6T, -75E, -75Z, -75; C T A +7 C; Notes: 5,, 3, 5, 47; Notes appear on pages 28 33; See also Table 8 on page 6 Parameter/Condition Symbol -5B -6/6T -75E -75Z/-75 Units Notes Operating one-bank active-precharge current: IDD ma 23, 48 t RC = t RC MIN; t = t MIN;, DM, and inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Operating one-bank active-read-precharge current: IDD ma 23, 48 Burst = 4; t RC = t RC MIN; t = t MIN; IOUT = ma; Address and control inputs changing once per clock cycle Precharge power-down standby current: All banks idle; IDD2P ma 24, 33 Power-down mode; t = t MIN; E = LOW Idle standby current: CS# = HIGH; All banks are idle; IDD2F ma 5 t = t MIN; E = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for,, and DM Active power-down standby current: One bank active; IDD3P ma 24, 33 Power-down mode; t = t MIN; E = LOW Active standby current: CS# = HIGH; E = HIGH; One bank IDD3N ma 23 active; t RC = t RAS MAX; t = t MIN;, DM, and inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating burst read current: Burst = 2; Continuous burst IDD4R ma 23, 48 reads; One bank active; Address and control inputs changing once per clock cycle; t = t MIN; IOUT = ma Operating burst write current: Burst = 2; Continuous burst writes; One bank active; Address and control inputs changing once per clock cycle; t = t MIN;, DM, and inputs changing twice per clock cycle IDD4W ma 23 Auto refresh burst current: t RFC = t RFC MIN IDD ma 5 t RFC = 7.8µs IDD5A ma 28, 5 Self refresh current: E.2V Standard IDD ma 2 Low power L IDD6A ma 2 Operating bank interleave read current: Four bank interleaving READs burst = 4 with auto precharge, RC = minimum t RC allowed; t = t MIN; Address and control inputs change only during active READ or WRITE commands IDD ma 23, 49 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 4 2 Micron Technology, Inc. All rights reserved.

15 Electrical Specifications IDD Table 7: IDD Specifications and Conditions x6 VD = +2.6V ±.V, VDD = +2.6V ±.V -5B; VD = +2.5V ±.2V, VDD = +2.5V ±.2V -6, -6T, -75E, -75Z, -75; C T A +7 C; Notes: 5,, 3, 5, 47; Notes appear on pages 28 33; See also Table 8 on page 6 Parameter/Condition Symbol -5B -6/6T -75E -75Z/-75 Units Notes Operating one-bank active-precharge current: IDD ma 23, 48 t RC = t RC MIN; t = t MIN;, DM, and inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Operating one-bank active-read-precharge current: IDD ma 23, 48 Burst = 4; t RC = t RC MIN; t = t MIN; IOUT = ma; Address and control inputs changing once per clock cycle Precharge power-down standby current: All banks idle; IDD2P ma 24, 33 Power-down mode; t = t MIN; E = LOW Idle standby current: CS# = HIGH; All banks are idle; IDD2F ma 5 t = t MIN; E = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for,, and DM Active power-down standby current: One bank active; IDD3P ma 24, 33 Power-down mode; t = t MIN; E = LOW Active standby current: CS# = HIGH; E = HIGH; One bank IDD3N ma 23 active; t RC = t RAS MAX; t = t MIN;, DM, and inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating burst read current: Burst = 2; Continuous IDD4R ma 23, 48 burst reads; One bank active; Address and control inputs changing once per clock cycle; t = t MIN; IOUT = ma Operating burst write current: Burst = 2; Continuous burst writes; One bank active; Address and control inputs changing once per clock cycle; t = t MIN;, DM, and inputs changing twice per clock cycle IDD4W ma 23 Auto refresh burst current: t RFC = t RFC MIN IDD ma 5 t RFC = 7.8µs IDD5A ma 28, 5 Self refresh current: E.2V Standard IDD ma 2 Low power L IDD6A ma 2 Operating bank interleave read current: Four bank interleaving READs burst = 4 with auto precharge, RC = minimum t RC allowed; t = t MIN; Address and control inputs change only during active READ or WRITE commands IDD ma 23, 49 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 5 2 Micron Technology, Inc. All rights reserved.

16 Electrical Specifications IDD Table 8: IDD Test Cycle Times Values reflect number of clock cycles for each test IDD Test Speed Grade Clock Cycle Time t RRD t RCD t RAS IDD -75/75Z 7.5ns n/a n/a n/a n/a n/a -75E 7.5ns n/a n/a n/a n/a n/a -6/-6T 6ns n/a n/a 7 3 n/a n/a n/a -5B 5ns n/a n/a 8 3 n/a n/a n/a IDD ns n/a n/a n/a n/a Z 7.5ns n/a n/a n/a n/a 2-75E 7.5ns n/a n/a n/a n/a 2-6/-6T 6ns n/a n/a 7 3 n/a n/a 2.5-5B 5ns n/a n/a n/a n/a n/a n/a n/a 3 IDD4R ns n/a n/a n/a n/a n/a n/a n/a Z 7.5ns n/a n/a n/a n/a n/a n/a n/a 2-75E 7.5ns n/a n/a n/a n/a n/a n/a n/a 2-6/-6T 6ns n/a n/a n/a n/a n/a n/a n/a 2.5-5B 5ns n/a n/a n/a n/a n/a n/a n/a 3 IDD4W ns n/a n/a n/a n/a n/a n/a n/a n/a -75Z 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a -75E 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a -6/-6T 6ns n/a n/a n/a n/a n/a n/a n/a n/a -5B 5ns n/a n/a n/a n/a n/a n/a n/a n/a IDD5-75/75Z 7.5ns n/a n/a n/a n/a n/a n/a -75E 7.5ns n/a n/a n/a n/a n/a 9 9 n/a -6/-6T 6ns n/a n/a n/a n/a n/a 2 2 n/a -5B 5ns n/a n/a n/a n/a n/a 4 4 n/a IDD5A -75/75Z 7.5ns n/a n/a n/a n/a n/a,29 n/a -75E 7.5ns n/a n/a n/a n/a n/a,29 n/a -6/-6T 6ns n/a n/a n/a n/a n/a 2,288 n/a -5B 5ns n/a n/a n/a n/a n/a 4,546 n/a IDD ns 2 3 n/a 3 n/a n/a Z 7.5ns 2 3 n/a 3 n/a n/a 2-75E 7.5ns 2 3 n/a 2 8 n/a n/a 2-6/-6T 6ns 2 3 n/a 3 n/a n/a 2.5-5B 5ns 2 3 n/a 3 n/a n/a 3 t RP t RC t RFC t REFI CL 52Mb_DDR_x4x8x6_D2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 6 2 Micron Technology, Inc. All rights reserved.

17 Electrical Specifications DC and AC 52Mb: x4, x8, x6 DDR SDRAM Electrical Specifications DC and AC Stresses greater than those listed in Table 9 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 9: Absolute Maximum Ratings Parameter Min Max Units VDD supply voltage relative to VSS V +3.6V V VD supply voltage relative to VSS V +3.6V V VREF and inputs voltage relative to VSS V +3.6V V I/O pins voltage relative to VSS.5V VD +.5V V Storage temperature plastic C Short circuit output current 5 ma Table : DC Electrical Characteristics and Operating Conditions -5B Notes: 5 and 7 apply to the entire table; Notes appear on page 34; VD = +2.6V ±.V, VDD = +2.6V ±.V Parameter/Condition Symbol Min Max Units Notes Supply voltage VDD V 37, 42 I/O supply voltage VD V 37, 42, 45 I/O reference voltage VREF.49 VD.5 VD V 7, 45 I/O termination voltage system VTT VREF -.4 VREF +.4 V 8, 45 Input high logic voltage VIHDC VREF +.5 VDD +.3 V 29 Input low logic voltage VILDC.3 VREF -.5 V 29 Input leakage current: II 2 +2 µa Any input V VIN VDD, VREF pin V VIN.35V All other pins not under test = V Output leakage current: are disabled; V VOUT VD IOZ 5 +5 µa Full-drive option output High current VOUT = IOH 6.8 ma 38, 4 levels x4, x8, x6: VD -.373V, minimum VREF, minimum VTT Low current VOUT =.373V, maximum VREF, maximum VTT IOL +6.8 ma Reduced-drive option output levels Design Revision F and K only: Ambient operating temperatures High current VOUT = VD -.373V, minimum VREF, minimum VTT Low current VOUT =.763V, maximum VREF, maximum VTT IOHR 9 ma 39, 4 IOLR +9 ma Commercial T A +7 C Industrial T A C DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 7 2 Micron Technology, Inc. All rights reserved.

18 Electrical Specifications DC and AC Table : DC Electrical Characteristics and Operating Conditions -6, -6T, -75E, -75Z, -75 Notes: 5, 7 apply to the entire table; Notes appear on page 34; VD = +2.5V ±.2V, VDD = +2.5V ±.2V Parameter/Condition Symbol Min Max Units Notes Supply voltage VDD V 37, 42 I/O supply voltage VD V 37, 42, 45 I/O reference voltage VREF.49 VD.5 VD V 7, 45 I/O termination voltage system VTT VREF -.4 VREF +.4 V 8, 45 Input high logic voltage VIHDC VREF +.5 VDD +.3 V 29 Input low logic voltage VILDC.3 VREF -.5 V 29 Input leakage current: II 2 +2 µa Any input V VIN VDD, VREF pin V VIN.35V All other pins not under test = V Output leakage current: are disabled; V VOUT VD IOZ 5 +5 µa Full-drive option output High current VOUT = IOH 6.8 ma 38, 4 levels x4, x8, x6: VD -.373V, minimum VREF, minimum VTT Low current VOUT =.373V, maximum VREF, maximum VTT IOL +6.8 ma Reduced-drive option output levels Design Revision F and K only: Ambient operating temperatures High current VOUT = VD -.763V, minimum VREF, minimum VTT Low current VOUT =.763V, maximum VREF, maximum VTT IOHR 9 ma 39, 4 IOLR +9 ma Commercial T A +7 C Industrial T A C Table 2: AC Input Operating Conditions Notes: 5, 7 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V VD = +2.6V ±.V, VDD = +2.6V ±.V for -5B Parameter/Condition Symbol Min Max Units Notes Input high logic voltage VIHAC VREF +.3 V 5, 29, 4 Input low logic voltage VILAC VREF -.3 V 5, 29, 4 I/O reference voltage VREFAC.49 VD.5 VD V 7 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 8 2 Micron Technology, Inc. All rights reserved.

19 Electrical Specifications DC and AC Figure : Input Voltage Waveform VD 2.3V MIN VOH MIN.67V for SSTL_2 termination System noise margin power/ground, crosstalk, signal integrity attenuation.56v VIHAC.4V VIHDC.3V.275V.25V.225V.2V VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise.v VILDC.94V VINAC - provides margin between VOL MAX and VILAC VOL MAX.83V 2 for SSTL_2 termination Receiver VILAC Transmitter Notes: VssQ. VOH MIN with test load is.927v. 2. VOL MAX with test load is.373v. 3. Numbers in diagram reflect nominal values utilizing circuit below for all devices other than -5B. VTT 25Ω 25Ω Reference point DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 9 2 Micron Technology, Inc. All rights reserved.

20 Electrical Specifications DC and AC Table 3: Clock Input Operating Conditions Notes: 5, 6, 7, 3 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V VD = +2.6V ±.V, VDD = +2.6V ±.V for -5B Parameter/Condition Symbol Min Max Units Notes Clock input mid-point voltage: and # VMPDC.5.35 V 7, Clock input voltage level: and # VINDC.3 VD +.3 V 7 Clock input differential voltage: and # VIDDC.36 VD +.6 V 7, 9 Clock input differential voltage: and # VIDAC.7 VD +.6 V 9 Clock input crossing point voltage: and # VIXAC.5 VD VD +.2 V Figure : SSTL_2 Clock Input 2.8V Maximum clock level #.45V.25V.5V X X VMPDC 2 VIXAC 3 VIDDC 4 VIDAC 5.3V Minimum clock level Notes:. or # may not be more positive than VD +.3V or more negative than VSS -.3V. 2. This provides a minimum of.5v to a maximum of.35v and is always half of VD. 3. and # must cross in this region. 4. and # must meet at least VIDDC MIN when static and is centered around VMPDC. 5. and # must have a minimum 7mV peak-to-peak swing. 6. For AC operation, all DC clock requirements must also be satisfied. 7. Numbers in diagram reflect nominal values for all devices other than -5B. DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 2 2 Micron Technology, Inc. All rights reserved.

21 Electrical Specifications DC and AC Table 4: Capacitance x4, x8 TSOP Note: 4 applies to the entire table; Notes appear on page 34 Parameter Symbol Min Max Units Notes Delta input/output capacitance: 3 x4, 7 x8 DCIO.5 pf 25 Delta input capacitance: Command and address DCI.5 pf 3 Delta input capacitance:, # DCI2.25 pf 3 Input/output capacitance:,, DM CIO pf Input capacitance: Command and address CI pf Input capacitance:, # CI pf Input capacitance: E CI pf Table 5: Capacitance x4, x8 FBGA Note: 4 applies to the entire table; Notes appear on page 34 Parameter Symbol Min Max Units Notes Delta input/output capacitance:,, DM DCIO.5 pf 25 Delta input capacitance: Command and address DCI.5 pf 3 Delta input capacitance:, # DCI2.25 pf 3 Input/output capacitance:,, DM CIO pf Input capacitance: Command and address CI pf Input capacitance:, # CI pf Input capacitance: E CI pf Table 6: Capacitance x6 TSOP Note: 4 applies to the entire table; Notes appear on page 34 Parameter Symbol Min Max Units Notes Delta input/output capacitance: 7, L, LDM DCIOL.5 pf 25 Delta input/output capacitance: 8 5, U, UDM DCIOU.5 pf 25 Delta input capacitance: Command and address DCI.5 pf 3 Delta input capacitance:, # DCI2.25 pf 3 Input/output capacitance:, L, U, LDM, UDM CIO pf Input capacitance: Command and address CI pf Input capacitance:, # CI pf Input capacitance: E CI pf Table 7: Capacitance x6 FBGA Note: 4 applies to the entire table; Notes appear on page 34 Parameter Symbol Min Max Units Notes Delta input/output capacitance: 7, L, LDM DCIOL.5 pf 25 Delta input/output capacitance: 8 5, U, UDM DCIOU.5 pf 25 Delta input capacitance: Command and address DCI.5 pf 3 Delta input capacitance:, # DCI2.25 pf 3 Input/output capacitance:, L, U, LDM, UDM CIO pf Input capacitance: Command and address CI pf Input capacitance:, # CI pf Input capacitance: E CI pf DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 2 2 Micron Technology, Inc. All rights reserved.

22 Electrical Specifications DC and AC Table 8: Electrical Characteristics and Recommended AC Operating Conditions -5B Notes 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.6V ±.V, VDD = +2.6V ±.V AC Characteristics -5B Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 3 Clock cycle time CL = 3 t ns 52 CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 3 and DM input hold time relative to t DH.4 ns 27, 32 and DM input pulse width for each input t DIPW.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.4 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.4 ns 27, 32 falling edge from rising hold time t DSH.2 t falling edge to rising setup time t DSS.2 t Half-clock period t HP t CH, t CL ns 35 Data-out High-Z window from /# t HZ +.7 ns 9, 43 Address and control input hold time slew rate.5 V/ns t IH F.6 ns 5 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time slew rate.5 V/ns t IS F.6 ns 5 Data-out Low-Z window from /# t LZ.7 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD ns hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.5 ns ACTIVE-to-READ with auto precharge command t RAP 5 ns ACTIVE-to-PRECHARGE command t RAS 4 7, ns 36 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 55 ns ACTIVE-to-READ or WRITE delay t RCD 5 ns REFRESH-to-REFRESH command 256Mb t REFC 7.3 µs 24 interval AUTO REFRESH command period 256Mb t RFC 7 ns 5 Average periodic refresh interval 256Mb t REFI 7.8 µs 24 PRECHARGE command period t RP 5 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD ns Terminating voltage delay to VDD t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 write postamble t WPST.4.6 t 2 Write recovery time t WR 5 ns DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 22 2 Micron Technology, Inc. All rights reserved.

23 Electrical Specifications DC and AC Table 8: Electrical Characteristics and Recommended AC Operating Conditions -5B continued Notes 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.6V ±.V, VDD = +2.6V ±.V AC Characteristics -5B Parameter Symbol Min Max Units Notes Internal WRITE-to-READ command delay t WTR 2 t Exit SELF REFRESH-to-non-READ 256Mb t XSNR 7 ns command Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 23 2 Micron Technology, Inc. All rights reserved.

24 Electrical Specifications DC and AC Table 9: Electrical Characteristics and Recommended AC Operating Conditions -6 Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V AC Characteristics -6 FBGA Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 3 Clock cycle time CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 3 and DM input hold time relative to t DH.45 ns 27, 32 and DM input pulse width for each input t DIPW.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.4 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.45 ns 27, 32 falling edge from rising - hold time t DSH.2 t falling edge to rising - setup time t DSS.2 t Half-clock period t HP t CH, ns 35 t CL Data-out High-Z window from /# t HZ +.7 ns 9, 43 Address and control input hold time fast slew rate t IH F.75 ns Address and control input hold time slow slew rate t IH S.8 ns 5 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.75 ns Address and control input setup time slow slew rate t IS S.8 ns 5 Data-out Low-Z window from /# t LZ.7 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD 2 ns - hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.5 ns ACTIVE-to-READ with auto precharge command t RAP 5 ns ACTIVE-to-PRECHARGE command t RAS 42 7, ns 36, 54 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 6 ns ACTIVE-to-READ or WRITE delay t RCD 5 ns REFRESH-to-REFRESH command 256Mb t REFC 7.3 µs 24 interval Average periodic refresh interval 256Mb t REFI 7.8 µs 24 AUTO REFRESH command period 256Mb t RFC 72 ns 5 PRECHARGE command period t RP 5 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 2 ns Terminating voltage delay to VSS t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 24 2 Micron Technology, Inc. All rights reserved.

25 Electrical Specifications DC and AC Table 9: Electrical Characteristics and Recommended AC Operating Conditions -6 continued Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V AC Characteristics -6 FBGA Parameter Symbol Min Max Units Notes write postamble t WPST.4.6 t 2 Write recovery time t WR 5 ns Internal WRITE-to-READ command delay t WTR t Exit SELF REFRESH-to-non-READ 256Mb t XSNR 75 ns command Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 25 2 Micron Technology, Inc. All rights reserved.

26 Electrical Specifications DC and AC Table 2: Electrical Characteristics and Recommended AC Operating Conditions -6T Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V AC Characteristics -6T TSOP Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 3 Clock cycle time CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 3 and DM input hold time relative to t DH.45 ns 27, 32 and DM input pulse width for each input t DIPW.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.45 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.45 ns 27, 32 falling edge from rising - hold time t DSH.2 t falling edge to rising - setup time t DSS.2 t Half-clock period t HP t CH, ns 35 t CL Data-out High-Z window from /# t HZ +.7 ns 9, 43 Address and control input hold time fast slew rate t IH F.75 ns Address and control input hold time slow slew rate t IH S.8 ns 5 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.75 ns Address and control input setup time slow slew rate t IS S.8 ns 5 Data-out Low-Z window from /# t LZ.7 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD 2 ns - hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.55 ns ACTIVE-to-READ with auto precharge command t RAP 5 ns ACTIVE-to-PRECHARGE command t RAS 42 7, ns 36, 54 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 6 ns ACTIVE-to-READ or WRITE delay t RCD 5 ns REFRESH-to-REFRESH command 256Mb t REFC 7.3 µs 24 interval Average periodic refresh interval 256Mb t REFI 7.8 µs 24 AUTO REFRESH command period 256Mb t RFC 72 ns 5 PRECHARGE command period t RP 5 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 2 ns Terminating voltage delay to VSS t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 26 2 Micron Technology, Inc. All rights reserved.

27 Electrical Specifications DC and AC Table 2: Electrical Characteristics and Recommended AC Operating Conditions -6T continued Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V AC Characteristics -6T TSOP Parameter Symbol Min Max Units Notes write postamble t WPST.4.6 t 2 Write recovery time t WR 5 ns Internal WRITE-to-READ command delay t WTR t Exit SELF REFRESH-to-non-READ 256Mb t XSNR 75 ns command Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 27 2 Micron Technology, Inc. All rights reserved.

28 Electrical Specifications DC and AC Table 2: Electrical Characteristics and Recommended AC Operating Conditions -75E Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V AC Characteristics -75E Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 3 Clock cycle time CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 3 and DM input hold time relative to t DH.5 ns 27, 32 and DM input pulse width for each input t DIPW.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.5 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.5 ns 27, 32 falling edge from rising - hold time t DSH.2 t falling edge to rising - setup time t DSS.2 t Half-clock period t HP t CH, ns 35 t CL Data-out High-Z window from /# t HZ +.75 ns 9, 43 Address and control input hold time fast slew rate t IH F.9 ns Address and control input hold time slow slew rate t IH S ns 5 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.9 ns Address and control input setup time slow slew rate t IS S ns 5 Data-out Low-Z window from /# t LZ.75 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD 5 ns - hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.75 ns ACTIVE-to-READ with auto precharge command t RAP 5 ns ACTIVE-to-PRECHARGE command t RAS 4 2, ns 36, 54 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 6 ns ACTIVE-to-READ or WRITE delay t RCD 5 ns REFRESH-to-REFRESH command 256Mb t REFC 7.3 µs 24 interval Average periodic refresh interval 256Mb t REFI 7.8 µs 24 AUTO REFRESH command period 256Mb t RFC 75 ns 5 PRECHARGE command period t RP 5 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 5 ns Terminating voltage delay to VSS t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 28 2 Micron Technology, Inc. All rights reserved.

29 Electrical Specifications DC and AC Table 2: Electrical Characteristics and Recommended AC Operating Conditions -75E continued Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V AC Characteristics -75E Parameter Symbol Min Max Units Notes write postamble t WPST.4.6 t 2 Write recovery time t WR 5 ns Internal WRITE-to-READ command delay t WTR t Exit SELF REFRESH-to-non-READ 256Mb t XSNR 75 ns command Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 29 2 Micron Technology, Inc. All rights reserved.

30 Electrical Specifications DC and AC Table 22: Electrical Characteristics and Recommended AC Operating Conditions -75Z Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V AC Characteristics -75Z Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 3 Clock cycle time CL = 2.5 t ns 46 CL = 2 t ns 46 low-level width t CL t 3 and DM input hold time relative to t DH.5 ns 27, 32 and DM input pulse width for each input t DIPW.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.5 ns 26, 27 WRITE command-to-first latching transition t S t and DM input setup time relative to t DS.5 ns 27, 32 falling edge from rising hold time t DSH.2 t falling edge to rising setup time t DSS.2 t Half-clock period t HP t CH, t CL ns 35 Data-out High-Z window from /# t HZ +.75 ns 9, 43 Address and control input hold time fast slew rate t IH F.9 ns Address and control input hold time slow slew rate t IH S ns 5 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.9 ns Address and control input setup time slow slew rate t IS S ns 5 Data-out Low-Z window from /# t LZ.75 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD 5 ns hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.75 ns ACTIVE-to-READ with auto precharge command t RAP 2 ns ACTIVE-to-PRECHARGE command t RAS 4 2, ns 36 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 65 ns ACTIVE-to-READ or WRITE delay t RCD 2 ns REFRESH-to-REFRESH command 256Mb t REFC 7.3 µs 24 interval Average periodic refresh interval 256Mb t REFI 7.8 µs 24 AUTO REFRESH command period 256Mb t RFC 75 ns 5 PRECHARGE command period t RP 2 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 5 ns Terminating voltage delay to VDD t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 write postamble t WPST.4.6 t 2 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 3 2 Micron Technology, Inc. All rights reserved.

31 Electrical Specifications DC and AC Table 22: Electrical Characteristics and Recommended AC Operating Conditions -75Z continued Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V AC Characteristics -75Z Parameter Symbol Min Max Units Notes Write recovery time t WR 5 ns Internal WRITE-to-READ command delay t WTR t Exit SELF REFRESH-to-non-READ 256Mb t XSNR 75 ns command Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 3 2 Micron Technology, Inc. All rights reserved.

32 Electrical Specifications DC and AC Table 23: Electrical Characteristics and Recommended AC Operating Conditions -75 Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 34; C T A +7 C; VD = +2.5V ±.2V, VDD = +2.5V ±.2V AC Characteristics -75 Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 3 Clock cycle time CL = 2.5 t ns 46 CL = 2 t 2 3 ns 46 low-level width t CL t 3 and DM input hold time relative to t DH.5 ns 27, 32 and DM input pulse width for each input t DIPW.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.5 ns 26, 27 WRITE command-to-first latching transition t S t and DM input setup time relative to t DS.5 ns 27, 32 falling edge from rising hold time t DSH.2 t falling edge to rising setup time t DSS.2 t Half-clock period t HP t CH, t CL ns 35 Data-out High-Z window from /# t HZ +.75 ns 9, 43 Address and control input hold time fast slew rate t IH F.9 ns Address and control input hold time slow slew rate t IH S ns 5 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.9 ns Address and control input setup time slow slew rate t IS S ns 5 Data-out Low-Z window from /# t LZ.75 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD 5 ns hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.75 ns ACTIVE-to-READ with auto precharge command t RAP 2 ns ACTIVE-to-PRECHARGE command t RAS 4 2, ns 36 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 65 ns ACTIVE-to-READ or WRITE delay t RCD 2 ns REFRESH-to-REFRESH command 256Mb t REFC 7.3 µs 24 interval Average periodic refresh interval 256Mb t REFI 7.8 µs 24 AUTO REFRESH command period 256Mb t RFC 75 ns 5 PRECHARGE command period t RP 2 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 5 ns Terminating voltage delay to VDD t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 write postamble t WPST.4.6 t 2 DDR_x4x8x6_Core2.fm - 52Mb DDR: Rev. M; Core DDR Rev. A /8 EN 32 2 Micron Technology, Inc. All rights reserved.