Double Data Rate (DDR) SDRAM MT46V64M4 16 Meg x 4 x 4 banks MT46V32M8 8 Meg x 8 x 4 banks MT46V16M16 4 Meg x 16 x 4 banks

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1 Double Data Rate DDR SDRAM MT46V64M4 6 Meg x 4 x 4 banks MT46V32M8 8 Meg x 8 x 4 banks MT46V6M6 4 Meg x 6 x 4 banks 256Mb: x4, x8, x6 DDR SDRAM Features Features V DD = 2.5V ±.2V; V D = 2.5V ±.2V V DD = 2.6V ±.V; V D = 2.6V ±.V DDR4 Bidirectional data strobe transmitted/ received with data, that is, source-synchronous data capture x6 has two one per byte Internal, pipelined double data rate DDR architecture; two data accesses per clock cycle Differential clock inputs and # Commands entered on each positive edge edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align and transitions with Four internal banks for concurrent operation Data mask DM for masking write data x6 has two one per byte Programmable burst lengths BL: 2, 4, or 8 Auto refresh 64ms, 892-cycle Longer-lead TSOP for improved reliability OCPL 2.5V I/O SSTL_2-compatible Concurrent auto precharge option supported t RAS lockout supported t RAP = t RCD Table : Speed Grade Options Marking Configuration 64 Meg x 4 6 Meg x 4 x 4 banks 64M4 32 Meg x 8 8 Meg x 8 x 4 banks 32M8 6 Meg x 6 4 Meg x 6 x 4 banks 6M6 Plastic package OCPL 66-pin TSOP TG 66-pin TSOP Pb-free P Plastic package 6-ball FBGA 8mm x 2.5mm CV 6-ball FBGA 8mm x 2.5mm CY Pb-free Timing cycle time CL = 3 DDR4-5B 3 CL = 2.5 DDR333 FBGA only -6 2 CL = 2.5 DDR333 TSOP only -6T 2 Self refresh Standard None Low-power self refresh L Temperature rating Commercial C to +7 C None Industrial 4 C to +85 C IT Revision x4, x8, x6 :K 4 x4, x8, x6 :M Notes:. DDR4 devices operating at < DDR333 conditions can use V DD /V D = 2.5V +.2V. 2. Available only on Revision K. 3. Available only on Revision M. 4. Not recommended for new designs. Key Timing Parameters CL = CAS READ latency; MIN clock rate with 5% duty cycle at CL = 2-75E, -75Z, CL = 2.5-6, -6T, -75, and CL = 3-5B Clock Rate MHz CL = 2 CL = 2.5 CL = 3 Data-Out Window Access Window Skew -5B ns ±.7ns.4ns n/a 2.ns ±.7ns.4ns 6T n/a 2.ns ±.7ns.45ns -75E/-75Z n/a 2.5ns ±.75ns.5ns n/a 2.5ns ±.75ns.5ns 256Mb_DDR_x4x8x6_D.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 23 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

2 Features Table 2: Addressing Parameter 64 Meg x 4 32 Meg x 8 6 Meg x 6 Configuration 6 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 6 x 4 banks Refresh count 8K 8K 8K Row address 8K A[2:] 8K A[2:] 8K A[2:] Bank address 4 BA[:] 4 BA[:] 4 BA[:] Column address 2K A[9:], A K A[9:] 52 A[8:] Table 3: Speed Grade Compatibility Marking PC PC PC PC PC PC B Yes Yes Yes Yes Yes Yes -6 Yes Yes Yes Yes Yes -6T Yes Yes Yes Yes Yes -75E Yes Yes Yes Yes -75Z Yes Yes Yes -75 Yes Yes -5B -6/-6T -75E -75Z Notes:. The -5B device is backward compatible with all slower speed grades. The voltage range of -5B device operating at slower speed grades is V DD = V D = 2.5V ±.2V. Figure : 256Mb DDR SDRAM Part Numbers Example Part Number: MT46V6M6P-6T:M - MT46V Configuration Package Speed Sp. Op. Temp. : Revision Configuration 64 Meg x 4 32 Meg x 8 6 Meg x 6 64M4 32M8 6M6 :K :M Revision x4, x8, x6 x4, x8, x6 Package 4-mil TSOP 4-mil TSOP Pb-free 8mm x 2.5mm FBGA 8mm x 2.5mm FBGA Pb-free TG P CV CY L Operating Temp. Commercial IT Industrial Special Options Standard Low power -5B -6-6T Speed Grade t = 5ns, CL = 3 t = 6ns, CL = 2.5 t = 6ns, CL = Mb_DDR_x4x8x6_D.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 2 23 Micron Technology, Inc. All rights reserved.

3 Features FBGA Part Marking System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron s Web site: 256Mb_DDR_x4x8x6_D.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 3 23 Micron Technology, Inc. All rights reserved.

4 Table of Contents 256Mb: x4, x8, x6 DDR SDRAM Table of Contents Features State Diagram Functional Description General Notes Functional Block Diagrams Pin and Ball Assignments and Descriptions Package Dimensions Electrical Specifications IDD Electrical Specifications DC and AC Notes Commands DESELECT NO OPERATION NOP LOAD MODE REGISTER LMR ACTIVE ACT READ WRITE PRECHARGE PRE BURST TERMINATE BST AUTO REFRESH AR SELF REFRESH Operations INITIALIZATION REGISTER DEFINITION ACTIVE READ WRITE PRECHARGE AUTO REFRESH SELF REFRESH Power-down E Not Active Mb_DDRTOC.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 4 23 Micron Technology, Inc. All rights reserved.

5 List of Figures 256Mb: x4, x8, x6 DDR SDRAM List of Figures Figure : 256Mb DDR SDRAM Part Numbers Figure 2: Simplified State Diagram Figure 6: 66-Pin TSOP Pin Assignments Top View Figure 8: 66-Pin Plastic TSOP 4 mil Figure 9: 6-Ball FBGA 8mm x 2.5mm Figure : Input Voltage Waveform Figure : SSTL_2 Clock Input Figure 2: Derating Data Valid Window t QH t Q Figure 3: Full Drive Pull-Down Characteristics Figure 4: Full Drive Pull-Up Characteristics Figure 5: Reduced Drive Pull-Down Characteristics Figure 6: Reduced Drive Pull-Up Characteristics Figure 7: Activating a Specific Row in a Specific Bank Figure 8: READ Command Figure 9: WRITE Command Figure 2: PRECHARGE Command Figure 2: INITIALIZATION Flow Diagram Figure 22: INITIALIZATION Timing Diagram Figure 23: Mode Register Definition Figure 24: CAS Latency Figure 25: Extended Mode Register Definition Figure 26: Example: Meeting t RCD t RRD MIN When 2 < t RCD t RRD MIN/ t Figure 29: Nonconsecutive READ Bursts Figure 3: Random READ Accesses Figure 3: Terminating a READ Burst Figure 32: READ-to-WRITE Figure 33: READ-to-PRECHARGE Figure 34: Bank READ Without Auto Precharge Figure 35: x4, x8 Data Output Timing t Q, t QH, and Data Valid Window Figure 36: x6 Data Output Timing t Q, t QH, and Data Valid Window Figure 37: Data Output Timing t AC and t Figure 38: WRITE Burst Figure 39: Consecutive WRITE-to-WRITE Figure 4: Random WRITE Cycles Figure 42: WRITE-to-READ Uninterrupting Figure 43: WRITE-to-READ Interrupting Figure 44: WRITE-to-READ Odd Number of Data, Interrupting Figure 45: WRITE-to-PRECHARGE Uninterrupting Figure 46: WRITE-to-PRECHARGE Interrupting Figure 47: WRITE-to-PRECHARGE Odd Number of Data, Interrupting Figure 48: Bank WRITE Without Auto Precharge Figure 49: WRITE DM Operation Figure 5: Data Input Timing Figure 5: Bank READ with Auto Precharge Figure 52: Bank WRITE with Auto Precharge Figure 53: Auto Refresh Mode Figure 54: Self Refresh Mode Mb_DDRLOF.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 5 23 Micron Technology, Inc. All rights reserved.

6 List of Tables 256Mb: x4, x8, x6 DDR SDRAM List of Tables Table : Key Timing Parameters Table 2: Addressing Table 3: Speed Grade Compatibility Table 4: Pin and Ball Descriptions Table 5: I DD Specifications and Conditions x4, x8, x6: -5B, -6, -6T Die Revision K Table 6: I DD Specifications and Conditions x4, x8, x6: -5B, -6, -6T Die Revision M Table 7: Absolute Maximum Ratings Table 8: DC Electrical Characteristics and Operating Conditions -5B Table 9: DC Electrical Characteristics and Operating Conditions -6, -6T, -75E, -75Z, Table : AC Input Operating Conditions Table : Clock Input Operating Conditions Table 2: Capacitance x4, x8 TSOP Table 3: Capacitance x4, x8 FBGA Table 4: Capacitance x6 TSOP Table 5: Capacitance x6 FBGA Table 6: Electrical Characteristics and Recommended AC Operating Conditions -5B Table 7: Electrical Characteristics and Recommended AC Operating Conditions Table 8: Electrical Characteristics and Recommended AC Operating Conditions -6T Table 9: Electrical Characteristics and Recommended AC Operating Conditions -75E Table 2: Electrical Characteristics and Recommended AC Operating Conditions -75Z Table 2: Electrical Characteristics and Recommended AC Operating Conditions Table 22: Input Slew Rate Derating Values for Addresses and Commands Table 23: Input Slew Rate Derating Values for,, and DM Table 24: Normal Output Drive Characteristics Table 25: Reduced Output Drive Characteristics Table 26: Truth Table Commands Table 27: Truth Table 2 DM Operation Table 28: Truth Table 3 Current State Bank n Command to Bank n Table 29: Truth Table 4 Current State Bank n Command to Bank m Table 3: Command Delays Table 3: Truth Table 5 E Table 32: Burst Definition Table 33: CAS Latency Mb_DDRLOT.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 6 23 Micron Technology, Inc. All rights reserved.

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8 State Diagram State Diagram Figure 2: Simplified State Diagram Power applied Power on PRE Precharge all banks LMR REFS Self refresh MR EMR LMR Idle all banks precharged REFSX REFA EL Auto refresh EH Active powerdown E HIGH ACT Precharge powerdown E LOW Row active Burst stop WRITE Write WRITE WRITE A READ A READ READ BST Read READ WRITE A READ A READ A Write A PRE PRE PRE Read A PRE Precharge PREALL Automatic sequence Command sequence ACT = ACTIVE BST = BURST TERMINATE EH = Exit power-down EL = Enter power-down EMR = Extended mode register LMR = LOAD MODE REGISTER MR = Mode register PRE = PRECHARGE PREALL = PRECHARGE all banks READ A = READ with auto precharge REFA = AUTO REFRESH REFS = Enter self refresh REFSX = Exit self refresh WRITE A = WRITE with auto precharge Note: This diagram represents operations within a single bank only and does not capture concurrent operations in other banks. DDR_x4x8x6_Core.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 7 23 Micron Technology, Inc. All rights reserved.

9 Functional Description 256Mb: x4, x8, x6 DDR SDRAM Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. A bidirectional data strobe is transmitted externally, along with data, for use in data capture at the receiver. is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. is edge-aligned with data for READs and center-aligned with data for WRITEs. The x6 offering has two data strobes, one for the lower byte and one for the upper byte. The DDR SDRAM operates from a differential clock and #; the crossing of going HIGH and # going LOW will be referred to as the positive edge of. Commands address and control signals are registered at every positive edge of. Input data is registered on both edges of, and output data is referenced to both edges of, as well as to both edges of. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which may then be followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs are SSTL_2, Class II compatible. General Notes The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. Throughout the data sheet, the various figures and text refer to s as. The term is to be interpreted as any and all collectively, unless specifically stated otherwise. Additionally, the x6 is divided into two bytes, the lower byte and upper byte. For the lower byte [7:] DM refers to LDM and refers to L. For the upper byte [5:8] DM refers to UDM and refers to U. Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. Any specific requirement takes precedence over a general statement. DDR_x4x8x6_Core.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 8 23 Micron Technology, Inc. All rights reserved.

10 Functional Block Diagrams 256Mb: x4, x8, x6 DDR SDRAM Functional Block Diagrams The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a 4-bank DRAM. Figure 3: 64 Meg x 4 Functional Block Diagram E # CS# Control logic WE# CAS# RAS# Command decode Bank 3 Bank 2 Bank Mode registers 5 Refresh counter 3 3 Rowaddress MUX 3 Bank rowaddress latch and decoder 892 Bank memory array 892 x 24 x 8 4 Data DLL A[2:], BA[:] 5 Address register 2 2 Bank control logic Sense amplifiers 892 I/O gating DM mask logic 24 x8 Column decoder READ latch out 4 WRITE FIFO and drivers in MUX Column Mask 2 8 Data generator Input registers Drivers Rcvrs [3:] DM Columnaddress counter/ latch Column 256Mb_DDR_x4x8x6_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 9 23 Micron Technology, Inc. All rights reserved.

11 Functional Block Diagrams Figure 4: 32 Meg x 8 Functional Block Diagram E # CS# WE# CAS# RAS# COMMAND DECODE CONTROL LOGIC BANK3 BANK2 BANK MODE REGISTERS 5 REFRESH 3 COUNTER 3 ROW- ADDRESS MUX 3 BANK ROW- ADDRESS 892 LATCH & DECODER BANK MEMORY ARRAY 892 x 52 x 6 8 DATA DLL SENSE AMPLIFIERS 6 READ LATCH 8 MUX 8 DRVRS 892 GENERATOR [7:] A[2:], BA[:] 5 ADDRESS REGISTER 2 2 BANK CONTROL LOGIC I/O GATING DM MASK LOGIC 52 x6 COLUMN DECODER 6 6 COL MASK WRITE FIFO 2 & DRIVERS 6 Out In DATA INPUT REGISTERS RCVRS DM COLUMN- ADDRESS COUNTER/ LATCH 9 COL Figure 5: 6 Meg x 6 Functional Block Diagram E # CS# WE# CAS# RAS# COMMAND DECODE CONTROL LOGIC REFRESH COUNTER BANK3 BANK BANK2 3 MODE REGISTERS 5 3 ROW- ADDRESS MUX 3 BANK ROW- ADDRESS 892 LATCH & DECODER BANK MEMORY ARRAY 892 x 256 x 32 6 DATA DLL SENSE AMPLIFIERS 32 READ LATCH 6 MUX 6 DRVRS 892 GENERATOR 2 [5:] A[2:], BA[:] 5 ADDRESS REGISTER 2 2 BANK CONTROL LOGIC I/O GATING DM MASK LOGIC 256 x32 COLUMN DECODER COL MASK WRITE FIFO 4 & DRIVERS 32 Out In DATA INPUT REGISTERS RCVRS L U LDM, UDM 9 COLUMN- ADDRESS COUNTER/ LATCH 8 COL 2 256Mb_DDR_x4x8x6_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 23 Micron Technology, Inc. All rights reserved.

12 Pin and Ball Assignments and Descriptions 256Mb: x4, x8, x6 DDR SDRAM Pin and Ball Assignments and Descriptions Figure 6: 66-Pin TSOP Pin Assignments Top View x4 x8 x6 x6 x8 x4 V DD V D V SSQ 2 V D 3 V SSQ V D V DD DNU WE# CAS# RAS# CS# BA BA A/AP V DD V D 2 V SSQ 3 4 V D 5 6 V SSQ 7 V D L V DD DNU LDM WE# CAS# RAS# CS# BA BA V SS 5 V SSQ 4 3 V D 2 V SSQ 9 V D 8 V SSQ U DNU V REF V SS UDM # E A2 A A9 V SS 7 V SSQ 6 V D 5 V SSQ 4 V D V SSQ DNU V REF V SS DM # E A2 A A9 A A/AP A8 A8 A A2 A3 V DD A A A2 A3 V DD A7 A6 A5 A4 V SS A7 A6 A5 A4 V SS V DD NF V D V SSQ NF V D V SSQ V D V DD DNU WE# CAS# RAS# CS# BA BA A/AP A A A2 A3 V DD V SS NF V SSQ 3 V D NF V SSQ 2 V D V SSQ DNU V REF V SS DM # E A2 A A9 A8 A7 A6 A5 A4 V SS 256Mb_DDR_x4x8x6_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 23 Micron Technology, Inc. All rights reserved.

13 Pin and Ball Assignments and Descriptions Figure 7: 6-Ball FBGA Ball Assignments Top View V SSQ V REF NF V D V SSQ V D V SSQ V SS A2 A A8 A6 A4 V SS 3 NF 2 DM # E A9 A7 A5 V SS x4 Top View A B C D E F G H J K L M V DD NF WE# RAS# BA A A2 V DD NF V SSQ V D V SSQ V D V DD CAS# CS# BA A A A3 V D DNU V SSQ V REF 7 V D V SSQ V D V SSQ V SS A2 A A8 A6 A4 V SS DM # E A9 A7 A5 V SS x8 Top View A B C D E F G H J K L M V DD 2 3 WE# RAS# BA A A2 V DD V SSQ V D V SSQ V D V DD CAS# CS# BA A A A3 V D DNU V SSQ V REF 5 V D V SSQ V D V SSQ V SS A2 A A8 A6 A4 V SS 3 9 U UDM # E A9 A7 A5 V SS x6 Top View A B C D E F G H J K L M V DD L LDM WE# RAS# BA A A2 V DD V SSQ V D V SSQ V D VDD CAS# CS# BA A A A3 V D DNU 256Mb_DDR_x4x8x6_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 2 23 Micron Technology, Inc. All rights reserved.

14 Pin and Ball Assignments and Descriptions Table 4: Pin and Ball Descriptions Symbol Type Description A[2:] Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit A for READ/WRITE commands, to select one location out of the memory array in the respective bank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A LOW, bank selected by BA[:] or all banks A HIGH. The address inputs also provide the op-code during a LOAD MODE REGISTER command. BA[:] Input Bank address inputs: BA[:] define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA[:] also define which mode register mode register or extended mode register is loaded during the LOAD MODE REGISTER LMR command., # Input Clock: and # are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of and the negative edge of #. Output data and is referenced to the crossings of and #. E Input Clock enable: E HIGH activates and E LOW deactivates the internal clock, input buffers, and output drivers. Taking E LOW provides PRECHARGE POWER-WN and SELF REFRESH operations all banks idle or ACTIVE POWER-WN row ACTIVE in any bank. E is synchronous for POWER-WN entry and exit and for SELF REFRESH entry. E is asynchronous for SELF REFRESH exit and for disabling the outputs. E must be maintained HIGH throughout read and write accesses. Input buffers excluding, #, and E are disabled during POWER- WN. Input buffers excluding E are disabled during SELF REFRESH. E is an SSTL_2 input but will detect an LVCMOS LOW level after V DD is applied and until E is first brought HIGH, after which it becomes a SSTL_2 input only. CS# Input Chip select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. DM LDM, UDM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of. Although DM pins are input-only, the DM loading is designed to match that of and pins. For x6 devices, LDM is DM for [7:], and UDM is DM for [5:8]. Pin 2 is on x4 and x8 devices. RAS#, CAS#, Input Command inputs: RAS#, CAS#, and WE# along with CS# define the command being entered. WE# [5:] I/O Data input/output: Data bus for x6 devices. [7:] I/O Data input/output: Data bus for x8 devices. [3:] I/O Data input/output: Data bus for x4 devices. L, U I/O Data strobe: Output with read data; input with write data. is edge-aligned with read data; centered in write data. It is used to capture data. For x6 devices, L is for [7:], and U is for [5:8]. Pin 6 E7 is for x4 and x8 devices. V DD Supply Power supply. V D Supply power supply: Isolated on the die for improved noise immunity. V SS Supply Ground. V SSQ Supply ground: Isolated on the die for improved noise immunity. V REF Supply SSTL_2 reference voltage. No connect for x6, x8, x4: These pins should be left unconnected. DNU Do not use: Must float to minimize noise on V REF. 256Mb_DDR_x4x8x6_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 3 23 Micron Technology, Inc. All rights reserved.

15 Package Dimensions Package Dimensions Figure 8: 66-Pin Plastic TSOP 4 mil ±.8 SEE DETAIL A.65 TYP.7. 2X.32 ±.75 TYP.76 ±.2.6 ±.8 PIN # ID GAGE PLANE.25.2 MAX TYP.5 ±. DETAIL A Notes:. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is.25mm per side. 3. Not all packages will have the half-moon shaped notches as shown. 256Mb_DDR_x4x8x6_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 4 23 Micron Technology, Inc. All rights reserved.

16 Package Dimensions Figure 9: 6-Ball FBGA 8mm x 2.5mm Seating plane.2 A A.8 ±. 6X Ø.45 Solder ball material: eutectic or SAC35. Dimensions apply to solder balls postreflow on Ø Ball A ID NSMD ball pads. A B C D E F CTR 2.5 ±.5 G H J TYP K L M Ball A ID.8 TYP 6.4 CTR 8 ±.5.2 MAX.25 MIN Notes:. All dimensions are in millimeters. 2. Topside part marking decoder can be found on Micron s Web site. 256Mb_DDR_x4x8x6_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 5 23 Micron Technology, Inc. All rights reserved.

17 Electrical Specifications I DD Electrical Specifications I DD Table 5: I DD Specifications and Conditions x4, x8, x6: -5B, -6, -6T Die Revision K V D = 2.6V ±.V, V DD = 2.6V ±.V -5B; V D = 2.5V ±.2V, V DD = 2.5V ±.2V -6, -6T; C T A 7 C; Notes: 6 5,, 3, 5, 47; Notes appear on pages 35 4; See also Table 7 on page 8 Parameter/Condition Symbol -5B -6/6T Units Notes Operating one-bank precharge current: t RC = t RC MIN; I DD 9 ma 23, 48 t = t MIN;, DM, and inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Operating one-bank active-read-precharge current: I DD 2 5 ma 23, 48 Burst = 4; t RC = t RC MIN; t = t MIN; I OUT =ma; Address and control inputs changing once per clock cycle Precharge power-down standby current: All banks idle; I DD2P 4 4 ma 24, 33 Power-down mode; t = t MIN; E = LOW Idle standby current: CS# = HIGH; All banks are idle; I DD2F 5 5 ma 5 t = t MIN; E = HIGH; Address and other control inputs changing once per clock cycle; V IN =V REF for,, and DM Active power-down standby current: One bank active; I DD3P 35 3 ma 24, 33 Power-down mode; t = t MIN; E = LOW Active standby current: CS# = HIGH; E = HIGH; One bank I DD3N 6 55 ma 23 active; t RC = t RAS MAX; t = t MIN;, DM, and inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating burst read current: Burst = 2; Continuous I DD4R 8 6 ma 23, 48 burst reads; One bank active; Address and control inputs changing once per clock cycle; t = t MIN; I OUT =ma Operating burst write current: Burst = 2; Continuous burst writes; One bank active; Address and control inputs changing once per clock cycle; t = t MIN;, DM, and inputs changing twice per clock cycle I DD4W 8 6 ma 23 Auto refresh burst current: t REFC = t RFC MIN I DD5 6 6 ma 5 t REFC =7.8μs I DD5A 6 6 ma 28, 5 Self refresh current: E.2V Standard I DD6 4 4 ma 2 Low power L I DD6A 2 2 ma 2 Operating bank interleave read current: Four-bank interleaving READs burst = 4 with auto precharge; RC = minimum t RC allowed; t = t MIN; Address and control inputs change only during ACTIVE, READ, or WRITE commands I DD ma 23, Mb_DDR_x4x8x6_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 6 23 Micron Technology, Inc. All rights reserved.

18 Electrical Specifications I DD Table 6: I DD Specifications and Conditions x4, x8, x6: -5B, -6, -6T Die Revision M V D = 2.6V ±.V, V DD = 2.6V ±.V -5B; V D = 2.5V ±.2V, V DD = 2.5V ±.2V -6, -6T; C T A 7 C; Notes: 5,, 3, 5, 47; Notes appear on pages 35 4; See also Table 7 on page 8 Parameter/Condition Symbol -5B -6/6T Units Notes Operating one-bank precharge current: t RC = t RC MIN; I DD ma 23, 48 t = t MIN;, DM, and inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Operating one-bank active-read-precharge current: Burst = 4; I DD ma 23, 48 t RC = t RC MIN; t = t MIN; I OUT = ma; Address and control inputs changing once per clock cycle Precharge power-down standby current: All banks idle; Powerdown I DD2P 4 4 ma 24, 33 mode; t = t MIN; E = LOW Idle standby current: CS# = HIGH; All banks are idle; t = t MIN; I DD2F ma 5 E = HIGH; Address and other control inputs changing once per clock cycle; V IN =V REF for,, and DM Active power-down standby current: One bank active; Powerdown I DD3P 4 4 ma 24, 33 mode; t = t MIN; E = LOW Active standby current: CS# = HIGH; E = HIGH; One bank active; I DD3N 3 3 ma 23 t RC = t RAS MAX; t = t MIN;, DM, and inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating burst read current: Burst = 2; Continuous burst reads; I DD4R 5 95 ma 23, 48 One bank active; Address and control inputs changing once per clock cycle; t = t MIN; I OUT =ma Operating burst write current: Burst = 2; Continuous burst writes; One bank active; Address and control inputs changing once per clock cycle; t = t MIN;, DM, and inputs changing twice per clock cycle I DD4W 5 95 ma 23 Auto refresh burst current: t REFC = t RFC MIN I DD5 5 5 ma 5 t REFC = 7.8μs I DD5A 6 6 ma 28, 5 Self refresh current: E.2V Standard I DD6 4 4 ma 2 Low power L I DD6A 2 2 ma 2 Operating bank interleave read current: Four-bank interleaving READs burst = 4 with auto precharge; t RC = minimum t RC allowed; = t MIN; Address and control inputs change only during ACTIVE, READ, or WRITE commands I DD ma 23, Mb_DDR_x4x8x6_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 7 23 Micron Technology, Inc. All rights reserved.

19 Electrical Specifications DC and AC 256Mb: x4, x8, x6 DDR SDRAM Electrical Specifications DC and AC Stresses greater than those listed in Table 7 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 7: Absolute Maximum Ratings Parameter Min Max Units V DD supply voltage relative to V SS V 3.6V V V D supply voltage relative to V SS V 3.6V V V REF and inputs voltage relative to V SS V 3.6V V I/O pins voltage relative to V SS.5V V D +.5V V Storage temperature plastic 55 5 C Short circuit output current 5 ma Table 8: DC Electrical Characteristics and Operating Conditions -5B Notes: 5 and 7 apply to the entire table; Notes appear on page 35; V D = 2.6V ±.V, V DD = 2.6V ±.V Parameter/Condition Symbol Min Max Units Notes Supply voltage V DD V 37, 42 I/O supply voltage V D V 37, 42, 45 I/O reference voltage V REF.49 V D.5 V D V 7, 45 I/O termination voltage system V TT V REF -.4 V REF +.4 V 8, 45 Input high logic voltage V IHDC V REF +.5 V DD +.3 V 29 Input low logic voltage V ILDC.3 V REF -.5 V 29 Input leakage current: I I 2 2 μa Any input V V IN V DD, V REF pin V V IN.35V All other pins not under test = V Output leakage current: are disabled; V V OUT V D I OZ 5 5 μa Full-drive option output High current V OUT = I OH 6.8 ma 38, 4 levels x4, x8, x6: V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OL 6.8 ma Reduced-drive option output levels Design Revision F and K only: Ambient operating temperatures High current V OUT = I OHR 9 ma 39, 4 V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OLR 9 ma Commercial T A 7 C Industrial T A 4 85 C DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 8 23 Micron Technology, Inc. All rights reserved.

20 Electrical Specifications DC and AC Table 9: DC Electrical Characteristics and Operating Conditions -6, -6T, -75E, -75Z, -75 Notes: 5 and 7 apply to the entire table; Notes appear on page 35; V D = 2.5V ±.2V, V DD = 2.5V ±.2V Parameter/Condition Symbol Min Max Units Notes Supply voltage V DD V 37, 42 I/O supply voltage V D V 37, 42, 45 I/O reference voltage V REF.49 V D.5 V D V 7, 45 I/O termination voltage system V TT V REF -.4 V REF +.4 V 8, 45 Input high logic voltage V IHDC V REF +.5 V DD +.3 V 29 Input low logic voltage V ILDC.3 V REF -.5 V 29 Input leakage current: I I 2 2 μa Any input V V IN V DD, V REF pin V V IN.35V All other pins not under test = V Output leakage current: are disabled; V V OUT V D I OZ 5 5 μa Full-drive option output High current V OUT = I OH 6.8 ma 38, 4 levels x4, x8, x6: V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OL 6.8 ma Reduced-drive option output levels Design Revision F and K only: Ambient operating temperatures High current V OUT = I OHR 9 ma 39, 4 V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OLR 9 ma Commercial T A 7 C Industrial T A 4 85 C Table : AC Input Operating Conditions Notes: 5 and 7 apply to the entire table; Notes appear on page 35; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V V D = 2.6V ±.V, V DD = 2.6V ±.V for -5B Parameter/Condition Symbol Min Max Units Notes Input high logic voltage V IHAC V REF +.3 V 5, 29, 4 Input low logic voltage V ILAC V REF -.3 V 5, 29, 4 I/O reference voltage V REFAC.49 V D.5 V D V 7 DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 9 23 Micron Technology, Inc. All rights reserved.

21 Electrical Specifications DC and AC Figure : Input Voltage Waveform V D,min 2.3V V OH,min.67V for SSTL_2 termination System noise margin power/ground, crosstalk, signal integrity attenuation.56v V IHAC.4V V IHDC.3V.275V.25V.225V.2V V REF + AC noise V REF + DC error V REF - DC error V REF - AC noise.v V ILDC.94V V INAC - provides margin between V OL,max and V ILAC V OL,max.83V 2 for SSTL_2 termination Receiver V ILAC Transmitter Notes: V SSQ. V OH,min with test load is.927v. 2. V OL,max with test load is.373v. 3. Numbers in diagram reflect nominal values utilizing circuit below for all devices other than -5B. V TT 25Ω 25Ω Reference point DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 2 23 Micron Technology, Inc. All rights reserved.

22 Electrical Specifications DC and AC Table : Clock Input Operating Conditions Notes: 5, 6, 7, and 3 apply to the entire table; Notes appear on page 35; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V V D = 2.6V ±.V, V DD = 2.6V ±.V for -5B Parameter/Condition Symbol Min Max Units Notes Clock input mid-point voltage: and # V MPDC.5.35 V 7, Clock input voltage level: and # V INDC.3 V D +.3 V 7 Clock input differential voltage: and # V IDDC.36 V D +.6 V 7, 9 Clock input differential voltage: and # V IDAC.7 V D +.6 V 9 Clock input crossing point voltage: and # V IXAC.5 V D V D +.2 V Figure : SSTL_2 Clock Input 2.8V Maximum clock level #.45V.25V.5V X X V MPDC 2 V IXAC 3 V 4 IDDC V 5 IDAC.3V Minimum clock level Notes:. or # may not be more positive than V D +.3V or more negative than V SS -.3V. 2. This provides a minimum of.5v to a maximum of.35v and is always half of V D. 3. and # must cross in this region. 4. and # must meet at least V IDDC,min when static and is centered around V MPDC. 5. and # must have a minimum 7mV peak-to-peak swing. 6. For AC operation, all DC clock requirements must also be satisfied. 7. Numbers in diagram reflect nominal values for all devices other than -5B. DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN 2 23 Micron Technology, Inc. All rights reserved.

23 Electrical Specifications DC and AC Table 2: Capacitance x4, x8 TSOP Note: 4 applies to the entire table; Notes appear on page 35 Parameter Symbol Min Max Units Notes Delta input/output capacitance: [3:] x4, [7:] x8 DC IO.5 pf 25 Delta input capacitance: Command and address DC I.5 pf 3 Delta input capacitance:, # DC I2.25 pf 3 Input/output capacitance:,, DM C IO pf Input capacitance: Command and address C I pf Input capacitance:, # C I pf Input capacitance: E C I pf Table 3: Capacitance x4, x8 FBGA Note: 4 applies to the entire table; Notes appear on page 35 Parameter Symbol Min Max Units Notes Delta input/output capacitance:,, DM DC IO.5 pf 25 Delta input capacitance: Command and address DC I.5 pf 3 Delta input capacitance:, # DC I2.25 pf 3 Input/output capacitance:,, DM C IO pf Input capacitance: Command and address C I pf Input capacitance:, # C I pf Input capacitance: E C I pf Table 4: Capacitance x6 TSOP Note: 4 applies to the entire table; Notes appear on page 35 Parameter Symbol Min Max Units Notes Delta input/output capacitance: [7:], L, LDM DC IOL.5 pf 25 Delta input/output capacitance: [5:8], U, UDM DC IOU.5 pf 25 Delta input capacitance: Command and address DC I.5 pf 3 Delta input capacitance:, # DC I2.25 pf 3 Input/output capacitance:, L, U, LDM, UDM C IO pf Input capacitance: Command and address C I pf Input capacitance:, # C I pf Input capacitance: E C I pf Table 5: Capacitance x6 FBGA Note: 4 applies to the entire table; Notes appear on page 35 Parameter Symbol Min Max Units Notes Delta input/output capacitance: [7:], L, LDM DC IOL.5 pf 25 Delta input/output capacitance: [5:8], U, UDM DC IOU.5 pf 25 Delta input capacitance: Command and address DC I.5 pf 3 Delta input capacitance:, # DC I2.25 pf 3 Input/output capacitance:, L, U, LDM, UDM C IO pf Input capacitance: Command and address C I pf Input capacitance:, # C I pf Input capacitance: E C I pf DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN Micron Technology, Inc. All rights reserved.

24 Electrical Specifications DC and AC Table 6: Electrical Characteristics and Recommended AC Operating Conditions -5B Notes 6, 6 8, and 34 apply to the entire table; Notes appear on page 35; C T A 7 C; V D = 2.6V ±.V, V DD = 2.6V ±.V AC Characteristics -5B Parameter Symbol Min Max Units Notes Access window of from /# t AC.7.7 ns high-level width t CH t 3 Clock cycle time CL = 3 t ns 52 CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 3 and DM input hold time relative to t DH.4 ns 27, 32 and DM input pulse width for each input t DIPW.75 ns 32 Access window of from /# t.6.6 ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.4 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.4 ns 27, 32 falling edge from rising hold time t DSH.2 t falling edge to rising setup time t DSS.2 t Half-clock period t HP t CH, t CL ns 35 Data-out High-Z window from /# t HZ.7 ns 9, 43 Address and control input hold time slew rate.5 V/ns t IH F.6 ns 5 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.6 ns 5 Address and control input setup time slow slew rate t IS S.7 ns Data-out Low-Z window from /# t LZ.7 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD ns hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.5 ns ACTIVE-to-READ with auto precharge command t RAP 5 ns ACTIVE-to-PRECHARGE command t RAS 4 7, ns 36 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 55 ns 55 ACTIVE-to-READ or WRITE delay t RCD 5 ns REFRESH-to-REFRESH command interval t REFC 7.3 μs 24 Average periodic refresh interval t REFI 7.8 μs 24 AUTO REFRESH command period t RFC 7 ns 5 PRECHARGE command period t RP 5 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD ns Terminating voltage delay to V DD t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 write postamble t WPST.4.6 t 2 Write recovery time t WR 5 ns DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN Micron Technology, Inc. All rights reserved.

25 Electrical Specifications DC and AC Table 6: Electrical Characteristics and Recommended AC Operating Conditions -5B continued Notes 6, 6 8, and 34 apply to the entire table; Notes appear on page 35; C T A 7 C; V D = 2.6V ±.V, V DD = 2.6V ±.V AC Characteristics -5B Parameter Symbol Min Max Units Notes Internal WRITE-to-READ command delay t WTR 2 t Exit SELF REFRESH-to-non-READ command t XSNR 7 ns Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN Micron Technology, Inc. All rights reserved.

26 Electrical Specifications DC and AC Table 7: Electrical Characteristics and Recommended AC Operating Conditions -6 Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 35; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -6 FBGA Parameter Symbol Min Max Units Notes Access window of from /# t AC.7.7 ns high-level width t CH t 3 Clock cycle time CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 3 and DM input hold time relative to t DH.45 ns 27, 32 and DM input pulse width for each input t DIPW.75 ns 32 Access window of from /# t.6.6 ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.4 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.45 ns 27, 32 falling edge from rising - hold time t DSH.2 t falling edge to rising - setup time t DSS.2 t Half-clock period t HP t CH, t CL ns 35 Data-out High-Z window from /# t HZ.7 ns 9, 43 Address and control input hold time fast slew rate t IH F.75 ns Address and control input hold time slow slew rate t IH S.8 ns 5 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.75 ns Address and control input setup time slow slew rate t IS S.8 ns 5 Data-out Low-Z window from /# t LZ.7 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD 2 ns - hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.5 ns ACTIVE-to-READ with auto precharge command t RAP 5 ns ACTIVE-to-PRECHARGE command t RAS 42 7, ns 36, 54 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 6 ns 55 ACTIVE-to-READ or WRITE delay t RCD 5 ns REFRESH-to-REFRESH command interval t REFC 7.3 μs 24 Average periodic refresh interval t REFI 7.8 μs 24 AUTO REFRESH command period t RFC 72 ns 5 PRECHARGE command period t RP 5 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 2 ns Terminating voltage delay to V SS t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 write postamble t WPST.4.6 t 2 Write recovery time t WR 5 ns DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN Micron Technology, Inc. All rights reserved.

27 Electrical Specifications DC and AC Table 7: Electrical Characteristics and Recommended AC Operating Conditions -6 continued Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 35; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -6 FBGA Parameter Symbol Min Max Units Notes Internal WRITE-to-READ command delay t WTR t Exit SELF REFRESH-to-non-READ command t XSNR 75 ns Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN Micron Technology, Inc. All rights reserved.

28 Electrical Specifications DC and AC Table 8: Electrical Characteristics and Recommended AC Operating Conditions -6T Notes: 6, 6 8, and 34 apply to the entire table; Notes appear on page 35; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -6T TSOP Parameter Symbol Min Max Units Notes Access window of from /# t AC.7.7 ns high-level width t CH t 3 Clock cycle time CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 3 and DM input hold time relative to t DH.45 ns 27, 32 and DM input pulse width for each input t DIPW.75 ns 32 Access window of from /# t.6.6 ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.45 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.45 ns 27, 32 falling edge from rising - hold time t DSH.2 t falling edge to rising - setup time t DSS.2 t Half-clock period t HP t CH, ns 35 t CL Data-out High-Z window from /# t HZ.7 ns 9, 43 Address and control input hold time fast slew rate t IH F.75 ns Address and control input hold time slow slew rate t IH S.8 ns 5 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.75 ns Address and control input setup time slow slew rate t IS S.8 ns 5 Data-out Low-Z window from /# t LZ.7 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD 2 ns - hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.55 ns ACTIVE-to-READ with auto precharge command t RAP 5 ns ACTIVE-to-PRECHARGE command t RAS 42 7, ns 36, 54 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 6 ns 55 ACTIVE-to-READ or WRITE delay t RCD 5 ns REFRESH-to-REFRESH command interval t REFC 7.3 μs 24 Average periodic refresh interval t REFI 7.8 μs 24 AUTO REFRESH command period t RFC 72 ns 5 PRECHARGE command period t RP 5 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 2 ns Terminating voltage delay to V SS t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 write postamble t WPST.4.6 t 2 DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN Micron Technology, Inc. All rights reserved.

29 Electrical Specifications DC and AC Table 8: Electrical Characteristics and Recommended AC Operating Conditions -6T continued Notes: 6, 6 8, and 34 apply to the entire table; Notes appear on page 35; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -6T TSOP Parameter Symbol Min Max Units Notes Write recovery time t WR 5 ns Internal WRITE-to-READ command delay t WTR t Exit SELF REFRESH-to-non-READ command t XSNR 75 ns Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN Micron Technology, Inc. All rights reserved.

30 Electrical Specifications DC and AC Table 9: Electrical Characteristics and Recommended AC Operating Conditions -75E Notes: 6, 6 8, 34 apply to the entire table; Notes appear on page 35; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -75E Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 3 Clock cycle time CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 3 and DM input hold time relative to t DH.5 ns 27, 32 and DM input pulse width for each input t DIPW.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.5 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.5 ns 27, 32 falling edge from rising - hold time t DSH.2 t falling edge to rising - setup time t DSS.2 t Half-clock period t HP t CH, ns 35 t CL Data-out High-Z window from /# t HZ.75 ns 9, 43 Address and control input hold time fast slew rate t IH F.9 ns Address and control input hold time slow slew rate t IH S ns 5 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.9 ns Address and control input setup time slow slew rate t IS S ns 5 Data-out Low-Z window from /# t LZ.75 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD 5 ns - hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.75 ns ACTIVE-to-READ with auto precharge command t RAP 5 ns ACTIVE-to-PRECHARGE command t RAS 4 2, ns 36, 54 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 6 ns 55 ACTIVE-to-READ or WRITE delay t RCD 5 ns REFRESH-to-REFRESH command interval t REFC 7.3 μs 24 Average periodic refresh interval t REFI 7.8 μs 24 AUTO REFRESH command period t RFC 75 ns 5 PRECHARGE command period t RP 5 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 5 ns Terminating voltage delay to V SS t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 write postamble t WPST.4.6 t 2 DDR_x4x8x6_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/5 EN Micron Technology, Inc. All rights reserved.