CITY UNIVERSITY OF HONG KONG 香港城市大學. New Energy-efficient High-voltage DC-DC Power Conversion Technology 新型高效能高電壓直流功率變換技術

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1 CITY UNIVERSITY OF HONG KONG 香港城市大學 New Energy-efficient High-voltage DC-DC Power Conversion Technology 新型高效能高電壓直流功率變換技術 Submitted to Department of Electronic Engineering 電子工程學系 in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy 哲學博士學位 by Wang Huai 王懷 March 01 二零一二年三月 Copyright 01 by Huai Wang All Rights Reserved

2 Abstract- i ABSTRACT This thesis presents the findings of research on new high-voltage medium-power dc-dc conversion technologies. A current-fed full-bridge step-up high output voltage converter and two multi-level step-down high input voltage converters have been investigated. A switched-capacitor snubber is proposed for zero-current-switching (ZCS) of the four IGBTs in the full-bridge converter. The ZCS can be achieved with minimum circulating current under different loading condition due to the self-adaptable resonant energy in the snubber. Two kinds of energy-efficient solutions are presented to perform the conversion from high input voltage to low output voltage. One is by using a multi-level multi-phase topology with zero-voltage-switching (ZVS) to reduce the voltage stress on the primary-side switches and improve the output current capacity. The other is by employing a three-level converter featured with different voltage stresses on the two series-connected switch pairs, allowing optimal selection of switching devices and wide soft-switching load range. In practice, the low output voltages of the high-voltage converters are usually used to supply various low-voltage converters which are exposure to momentary loads. To improve the dynamic response, a generalized fast transient controller is proposed for different type of low-voltage converters based on the derivation of a uniform second-order switching surface. The considerable power loss and short lifetime of aluminum electrolytic capacitors in power converters impose massive challenges to push up efficiency and lifetime. Therefore, a novel concept to reduce the dc-link capacitance by introducing a voltage compensator connecting in series with the dc bus line is proposed and studied. It explores the possibilities to replace the electrolytic dc-link capacitors in high-voltage power converters by long lifetime low power loss film capacitors without sacrificing power

3 Abstract- ii density and cost effectiveness. The contents of this thesis are as follows: In Chapter 1, the motivation of the research on high-voltage medium-power dc-dc converters will be discussed. Prior-art approaches to improve the efficiency of power converters will be reviewed from component level, circuit level to system level. The principle and associated application limitation of switching surface control for dc-dc converters will be illustrated. Available concepts and solutions to reduce dc-link capacitors in power electronic systems will be presented. In Chapter, the concept of adaptive snubber energy for ZCS will be presented. The operating principles of the proposed current-fed full-bridge converter will be described. The trade-off design and small-signal model will be given. Implementations and evaluations of a 530 V / 15 kv 5 kw experimental prototype will be discussed. In Chapter 3, a solution for high-to-low voltage conversion based on a generalized multi-level multi-phase topology will be discussed. The switching mechanism and operation of a typical switch pair will be analyzed. A dc analysis will be carried out to determine the dc conversion ratio and the ZVS conditions in an analytical form. The selfbalance property of the voltages across the input capacitors will be described. A 1500 V / 48 V, kw prototype with four switch pairs in the primary-side is designed, implemented, and evaluated. In Chapter 4, another solution to convert 1500 V dc to 48 V dc will be presented based on a novel concept, by which the voltage stresses on the series-connected two switch pairs are asymmetric. The advantages of a three-level converter adopted the proposed concept will be illustrated in terms of utilization of switching devices and load range for

4 Abstract- iii soft-switching. A new concept of hybrid ZVS-ZCS scheme will be proposed. The evaluations on a kw prototype will be given to verify the theoretical predictions. In Chapter 5, a uniform second-order switching surface for a fast transient controller of dc-dc converters will be derived. Stability analysis and controller implementation will be discussed. Simulation results on four kinds of dc-dc converters (i.e., boost converter, buck-boost converter, Ćuk converter and SEPIC) will be presented to verify the universal applicability of the proposed control method. Experimental results on a 48 V/48 V buckboost converter prototype will be also analyzed to exhibit the performance of the controller. In Chapter 6, a patent-pending technology for reducing dc-link capacitance in capacitor-supported power electronic systems will be presented. The operation principle and implementation of the proposed voltage compensator will be discussed. Simulation and experimental results will be provided to verify the theoretical analysis. given. In Chapter 7, conclusions and suggestions for future research on this topic will be

5 ACKNOWLEDGEMENT I would like to thank many people who made the work described here possible. First of all, my gratitude is due to my supervisor Prof. Henry S. H. Chung, for his choice to recruit me as a research student in 007, for his sparkling ideas that brought me into the world of power electronics and for his kind guidance and support during my study at the City University of Hong Kong. The philosophy he embraces will continue to benefit me both in research and life. I am also deeply grateful to Prof. Adrian Ioinovici at Holon Institute of Technology, for his critical questions in every single discussion, for his patient instructions from a single word to a full research paper and for his encouragement during my research and life. I would like to thank Prof. Ron S. Y. Hui, Dr. Wei Yan, Dr. Ricky W. H. Lau, Dr. Norman C. F. Tse and Dr. K. F. Tsang, for their kind help during my study. I would like to thank all of other research students and staff at the Centre for Power Electronics for their help and friendship every single day. I am grateful to Dr. Carl Ho and Dr. Francisco Canales for their professional supervision during my internship at ABB Corporate Research Center, Switzerland. I would also like to thank Prof. Jason Lai from Virginia Tech, USA, Prof. Ashoka K. S. Bhat from University of Victoria, Canada and Dr. L. F. Yeung from City University of Hong Kong, Hong Kong, for serving on my Ph.D. oral examination committee. Finally, my heartfelt appreciation goes toward all of my family members, who are always there for me with their support and encouragement throughout my education.

6 TABLE OF CONTENTS ABSTRACT ACKNOWLEDGEMENT TABLE OF CONTENTS CHAPTER 1 OVERVIEW AND BACKGROUND OF RESEARCH INTRODUCTION COMPONENT LEVEL MOSFET and IGBT Aluminum Electrolytic Capacitor and Power Film Capacitor CIRCUIT LEVEL Switch Pairs and Their Combinations Soft-Switching Technology Selection of Topology SYSTEM LEVEL Single-Step Conversion Concept Fast Transient Control Methods for Load Converters E-Cap Reduction Technology ORGANIZATION OF THE THESIS... 4 CHAPTER HIGH OUTPUT VOLTAGE ZCS CURRENT-FED FULL-BRIDGE CONVERTER WITH SELF-ADAPTABLE SOFT-SWITCHING SNUBBER ENERGY INTRODUCTION CURRENT-FED ZCS FB CONVERTER AND ITS OPERATION PRINCIPLE... 7

7 ..1. Circuit Structure Steady-State Operation Modes STEADY-STATE ANALYSIS ZCS Conditions DC Conversion Ratio Maximum Voltage across the Snubber Capacitor C r Duration of the Snubber Capacitor Charging / Discharging Intervals Regulation and Soft-Switching Boundaries SMALL-SIGNAL ANALYSIS AND CONTROLLER DESIGN Small-Signal Model and Open Loop Transfer Functions Controller Design DESIGN PROCEDURE AND EXPERIMENTAL VERIFICATION CHAPTER SUMMARY CHAPTER 3 HIGH INPUT VOLTAGE MULTI-LEVEL MULTI-PHASE DC-DC CONVERTER INTRODUCTION GENERALIZED CIRCUIT STRUCTURE AND ITS OPERATION PRINCIPLE Circuit Structure Operation Principle STEADY-STATE ANALYSIS DC Voltage Conversion Ratio and Duty Cycle Loss ZVS Load Range Self-Balancing Mechanism of Switch-Pair Voltage... 73

8 Steady-State Current Distribution in the Transformer Windings DESIGN CONSIDERATIONS Design Specifications Turns Ratio of the Isolation Transformer (m) Design of the Value of the Leakage Inductance (L lk ) Design of Output Inductors (L f ) Design of Output Capacitor (C o ) Design of Input Capacitors and DC-Blocking Capacitors Selection of MOSFETs and Diodes EXPERIMENTAL VERIFICATIONS CHAPTER SUMMARY... 9 CHAPTER 4 HIGH INPUT VOLTAGE THREE-LEVEL DC-DC CONVERTER WITH ASYMMETRIC VOLTAGE DISTRIBUTION ON SWITCH PAIRS INTRODUCTION CONVERTER WITH ASYMMETRIC VOLTAGE DISTRIBUTION Circuit Structure Conversion Concept with Asymmetric Voltage Distribution OPERATION PRINCIPLE OF THE PROPOSED CONVERTER STEADY-STATE ANALYSIS Steady-State Voltage Stress on C b Voltage Conversion Ratio Voltage Distribution across Switch Pairs... 1

9 4.5. DESIGN GUIDELINES Design Issues Boundaries of the Design Parameters Optimal Design PROTOTYPE AND EXPERIMENTAL VERIFICATIONS CHAPTER SUMMARY CHAPTER 5 A UNIFORM FAST TRANSIENT CONTROLLER FOR DC-DC CONVERTERS INTRODUCTION UNIFORM SECOND-ORDER SWITCHING SURFACE Derivation of Uniform Second-Order Switching Surface Stability Analysis DERIVATION AND IMPLEMENTATION (FOR BUCK-BOOST CONVERTER) STEADY-STATE CHARACTERISTICS (FOR BUCK-BOOST CONVERTER) Switching Frequency Output Voltage EXPERIMENTAL VERIFICATIONS CHAPTER SUMMARY CHAPTER 6 A DC-LINK MODULE FOR REDUCING DC-LINK CAPACITANCE INTRODUCTION BASIC CONCEPT OF THE PROPOSED DC-LINK MODULE STEADY-STATE DC AND AC ANALYSIS

10 6. 4 SERIES-CONNECTED VOLTAGE COMPENSATOR Impementation Analysis of the Voltage Compensator DESIGN OF CAPACITORS FOR DC-LINK AND THE VOLTAGE COMPENSATOR Design of the DC-Link Capacitor Design of the Input Capacitor of the Voltage Compensator SIMULATION AND EXPERIMENTAL VERIFICATIONS Simulations Experimental Verifications CHAPTER SUMMARY CHAPTER 7 CONCLUSIONS AND SUGGESTIONS FOR FURTHER RESEARCH SUMMARY OF THE THESIS MAJOR CONTRIBUTIONS SUGGESTIONS FOR FURTHER RESEARCH APPENDIX A A.1 DERIVATION OF Eq. (4.34) A. DERIVATION OF Eq. (4.37) AND Eq. (4.39)... 0 A.3 DERIVATION OF Eq. (4.38) AND Eq. (4.40) PUBLICATIONS FROM THIS THESIS REFERENCES... 08

11 Chapter 1-1 CHAPTER 1 OVERVIEW AND BACKGROUND OF RESEARCH 1.1. Introduction The objective of this work is to provide essential basis for achieving energy-efficient and environmental-friendly high-voltage dc-dc converters. Specifically, research on circuit topology, soft-switching scheme, fast transient control method and electrolytic capacitor reduction technology has been carried out. The evolution of modern power electronics has witnessed its fast expanding in emerging applications and its indispensable role in processing electric energy [1]-[4]. Extensive technological advancement in power electronic converters has significantly improved the conversion efficiency and quality of electric power. Many efforts have been made to the research on low-voltage power converters (below 1000 V) to push up the efficiency, power density or switching frequency [5]-[15]. However, the research pace on high-voltage power converters, especially on the high-voltage dc-dc converters, is much less notable. High-voltage dc-dc converters are crucial parts in systems such as medical X- ray diagnostic equipment [16], traveling wave tube amplifiers [17], electric railway [18]- [19], etc. One of the key challenges in high-voltage dc-dc converters is that the advancement of high-voltage switching devices is less impressive than that of low voltage ones in terms of power loss, switching speed, reliability, availability and cost. Therefore, the circuit level performance is limited due to the relatively low allowable switching frequency and high power loss of high-voltage switching devices.

12 Chapter 1- Fig. 1.1 shows the block diagram of a typical switched-mode power converter. Various topologies are formed by combining five different types of components in different ways. The performance of the converter depends on the selected components and topology and the applied control scheme. When a power conversion system consisting of more than one converter is considered, the system performance depends on both the converters and the electrical architecture of the system. Therefore, it is necessary to investigate into the suitability of devices, corresponding topologies as well as specific power conversion systems to tackle the challenges in high-voltage dc-dc power conversions. Fig. 1.1 Block diagram of a typical switched-mode power converter. In the following three sections, the challenges and opportunities in the research on high-voltage medium-power dc-dc converters are analyzed at component level, circuit level and system level, respectively.

13 Chapter Component Level The evolution of power electronics lies heavily in the advancement of the components used, especially the power semiconductor devices, capacitors and high frequency magnetic elements. This section gives a brief introduction of some aspects of the components which are critical to the circuit level performance in this research work MOSFET and IGBT Among various types of switching devices, the power metal-oxide-semiconductor field effect transistor (MOSFET) and insulated gate bipolar transistor (IGBT) are widely used in the modern power converters. 1) On-state characteristics During the on-state interval, the on-state resistance (i.e., r DS_on ) of MOSFET and onstate saturation voltage (i.e., V CE, sat ) of IGBT induce forward voltage and thus conduction losses. Fig. 1. represents the on-state characteristics of typical MOSFET and IGBT graphically shown in [1]. The power density limit of 100 W/cm is constrained by the power dissipation and thermal management. According to Fig. 1., it can be noted that a) The on-state current density is compromised by the on-state voltage drop. b) For a given high on-state current density, IGBT has superior performance than MOSFET in terms of on-state voltage drop, therefore, conduction loss is lower. c) For a given current density, the on-state voltage drop V DS_on, thus the on-state resistance r DS_on, increases significantly with the blocking voltage rating. As discussed in [], for high-voltage N channel MOSFET, r DS_on is approximately given by

14 Chapter 1-4 r DS _ on Vb ( ) (1.1) A where V b is the rating of blocking voltage in volts and A is the die area in mm. It should be noted that with the introduction of vertical super-junction MOSFET [] and CoolMOS technology [3], r DS_on can be reduced significantly, however, only for MOSFET with voltage ratings up to 800 V. From this perspective, high-voltage MOSFET is unsuitable for high voltage applications due to the high r DS_on. Fig. 1. Comparison of the on-state characteristics of IGBT and MOSFET structures with different blocking voltage ratings [1].

15 Chapter 1-5 ) Switching characteristics According to the above analysis, IGBT has better performance than MOSFET regarding the on-state characteristics for high voltage applications. However, the switching speed of IGBT is normally slower than that of MOSFET, which is mainly due to their turnoff switching characteristics. Fig. 1.3 shows the simplified model of IGBT. It can be considered as the combination of MOSFET and BJT. A tail current [4] appears during turn off transition as shown in Fig. 1.4 due to this structure. Therefore, MOSFET is superior to IGBT in terms of switching speed and turn-off switching loss. It is more suitable for high frequency operation, which is crucial to achieve high power density converters. Fig. 1.3 Simplified IGBT model.

16 Chapter 1-6 Fig. 1.4 Typical turn-off transitions of MOSFET and IGBT with inductive load. It imposes the specific challenge to select proper switching devices in high-voltage medium-power converters as the compromised performance between the on-state characteristics and switching characteristics of both MOSFET and IGBT Aluminum Electrolytic Capacitor and Power Film Capacitor A typical power conditioning system consists of multiple power converters interconnected by a dc-link capacitor bank. Among different types of capacitor, aluminum electrolytic capacitors are widely chosen for the capacitor bank because of their high volumetric efficiency and low cost. Advances in film capacitor technology in the last two decades are emerging to be applied for dc-link filtering [6]-[7]. Table 1.1 shows a comparison between the aluminum electrolytic capacitor and power film capacitor for the dc-link. Power film

17 Chapter 1-7 capacitors outperform aluminum electrolytic capacitors counterparts in terms of ESR, tolerance, self-healing capability, life expectancy, environmental performance, dc-blocking capability, ripple current capability and reliability. However, the capacitance of the highvoltage film capacitors still cannot compete with electrolytic capacitors, due to their relatively low volumetric efficiency and high cost. Therefore, it imposes obstacles to offer high power density, high reliability and cost-effective solutions. Table 1.1 Comparisons between aluminum electrolytic capacitors and film capacitors. Aluminum electrolytic capacitors Power film capacitors volumetric efficiency 5-10 times (typical) relatively low voltage ratings from low to 700 V [5] from low to 100 kv capacitance tolerance ±0% (typical) ±5%, ±10% (typical) ripple current 0 ma/ μf (typical) 1 A/ μf (typical) ESR** 60 times (typical) [5] Low lifetime,000 hours * (typical) 100, 000 hours* (typical) cost relatively low 5-10 times (typical) *Under rated conditions. ** Equivalent series resistance Circuit Level In this section, switch pairs, topologies and associated soft-switching schemes for high voltage applications are evaluated Switch Pairs and Their Combinations A switch pair is composed of two switches connected in series and driven by complementary gate signals. Fig. 1.5 shows three possible switch pairs using MOSFETs and IGBTs.

18 Chapter 1-8 Fig. 1.5 Three types of switch pair (MOS: MOSFET). For medium to high power applications requiring input-output electrical isolation, converters containing switch pairs are usually adopted. The most popular structure is the full-bridge (FB) converter [8]-[9] with two switch pairs connected in parallel as shown in Fig. 1.6(a). Several FB converters can be connected in input-series-output-parallel (ISOP) to obtain a modular-based converter [30]-[33]. Another one is the three-level (TL) converter [34]-[43] with two switch pairs connected in series so as to withstand high input voltage as shown in Fig. 1.6(b). The two switch pairs in Fig. 1.6(b) can be extended to multiple ones to form multilevel converters [44]-[47]. (a) Full-bridge converter.

19 Chapter 1-9 (b) Three-level converter. Fig. 1.6 Topologies with switch pairs connected in parallel and in series. Table 1. tabulates the possible combinations of the switch pairs in the FB, TL and multilevel converters. For switch pair formed by two different types of switches, for examples, in Cases and 5 listed in Table 1., the maximum operating voltage is determined by the switch with the lower voltage rating in the switch pair. The maximum limit of the input voltage and the optimal soft-switching scheme for each case are provided. Table 1. Analysis of different combinations of switch pairs. Combination of switch pairs (Voltage ratings: MOS-V 1, IGBT-V ) (Assume V 1 < V ) In parallel (FB) In series (TL) Input voltage limitations Optimal softswitching scheme* Case 1 Two MOS-MOS V 1 ZVS Case Two MOS-IGBT V 1 ZVZCS Case 3 Two IGBT-IGBT V ZCS Case 4 Two MOS-MOS V 1 ZVS Case 5 Two MOS-IGBT V 1 ZVZCS Case 6 Two IGBT-IGBT V ZCS Case 7 IGBT-IGBT +MOS-MOS V 1 + V Hybrid ZVS-ZCS Voltage distribution between switch pairs Symmetric Asymmetric * Refer to Section 1.3..

20 Chapter Soft-Switching Technology The concept of soft-switching is dated back to 190s in the application of vibrator converters [48]. The latest round of interest in soft-switching technology starts around 1980s [49]-[5] from the resonant converters to reduce the switching loss and EMI [53]- [54], allowing the increase of switching frequency [55]. There are three types of softswitching: zero-voltage-switching (ZVS), zero-voltage-zero-current-switching (ZVZCS) and zero-current-switching (ZCS). The principle of ZVS is to provide energy to completely discharge and charge the output parasitic capacitors of switches during commutation transitions. The energy for achieving ZVS of the lagging switches in phase-shift FB converters is provided by the leakage inductance of isolation transformer. Therefore, ZVS is only guaranteed above a certain pre-designed load level. To extend the soft-switching range, additional energy sources for achieving ZVS of the lagging switches are fulfilled by either linear inductor [5], saturable inductor [8], coupled inductor [56]-[57], magnetizing inductor [58]-[59] or output inductor [60]. To reduce parasitic ringing, auxiliary circuits are added in secondaryside [50], [61] or primary-side [5], [6]-[65]. These approaches increase the circuit complexity, induce additional duty cycle loss and cause undesirable secondary-side ringing. The magnetizing current of the transformer flows at its maximum value through the primary switches during freewheeling mode, increasing the conduction loss. In an isolated ZVZCS phase-shift FB converter, the ZVS of the leading switches is ensured by energy stored in the output inductor. The ZCS of the lagging switches is fulfilled by resetting the primary winding current during freewheeling mode. Accordingly, various kinds of passive circuits or active circuits are proposed in [66]-[76] to assist ZCS, at

21 Chapter 1-11 the expense of either increasing circuit complexity and/or overvoltage across the secondary-side rectifier. Very little research has been devoted to FB ZCS converters: in [77] and [78], ZCS is obtained in current-driven converters, by using a passive snubber [77], or an active snubber [78]. With these methods, ZCS is achieved by utilizing a resonance process in a snubber formed by a resonant inductance L r (with the inclusion of the leakage inductance of the transformer) and a resonant capacitor C r (with the inclusion of the reflected winding capacitance). However, ZCS is lost at high input current. In order to extend the ZCS range, the characteristic impedance of the resonant tank has to be decreased, either by decreasing L r or increasing C r. The former way leads to an increase in the current stress on the primary switches, and the latter one results in an increase of the time duration for discharging C r, therefore, the loss of duty-cycle. Voltage-driven FB ZCS converters are proposed in [79]-[83] by using snubbers in the primary side [79], [81]-[8] or in the secondary side [80], [83]. In all of the available solutions, the energy used for achieving soft-switching is not optimized. A trade-off among the ZCS range, duty-cycle loss and circulating current has to be accomplished. In the presented research work, a snubbering technology having an adaptive snubber energy control for ZCS of a current-fed dc-dc converter will be discussed in Chapter. It achieves minimum resonant energy provided for ZCS at different load values. Moreover, a new type of soft-switching scheme, called hybrid zero-voltage-switching and zero-currentswitching (hybrid ZVS-ZCS) will be presented in Chapter 4.

22 Chapter Selection of Topology 1) Topologies for high output voltage application The research in resonant converters reveals their suitability for high output voltage applications, especially the series-parallel one [84]-[87]. It shows better output voltage regulation ability under light loading condition compared to series type resonant converter and smaller circulating current than that of parallel one. However, a large variation of the switching frequency is required from full load to no load when operating above the resonant frequency. There is still a trade-off between the upper switching frequency and the circulating current [16] at light loads. Moreover, turn-off loss is not eliminated in series-resonant converters, which is not desirable for converters employing IGBT with turn off tail current. Therefore, ZVS current-fed converters [88]-[91] and ZCS current-fed converters [77] and [9] with capacitive output filter are proposed as an alternative solution for high output voltage application. ZCS is preferable for converters employed IGBTs. However, as discussed in Section 1.3., the ZCS load range is compromised by the light load circulating current, thus, conduction loss in [77] and [9]. In Chapter, a current-fed ZCS FB PWM converter is chosen for converting a 530 V to 15 kv with an adaptive resonant snubber. ) Topologies for high input voltage and low output voltage application The high input voltage to low load voltage application discussed here is specifically referred to the on-board applications in railway systems as presented in Section 1.4. The

23 Chapter 1-13 target input voltage of the prototypes designed is 1500 V. Fig. 1.7 shows the available choices for dc-dc converters in terms of the circuit topology, single switch [93]-[94] or combination of switch pair and soft-switching scheme with respect to various input voltage and power levels. In particular, there are two available solutions to convert the 1500 V line to low load voltages in a single step as presented in the chart of Fig The first one is a FB converter [8]-[83] and [95], in which high-voltage devices are necessary. Switches with voltage rating of 1.7 kv or.5 kv should be used on the primary side. In [8], a secondary-side snubber, with one active switch turned on and off twice in one cycle, is added to assist ZCS of the IGBTs. If the full-wave rectifier is replaced by a current doubler rectifier, two active snubbers are needed for ZCS of all four IGBTs [96]. In [83], two primary-side active snubbers are used to ensure ZCS of the four IGBTs, the auxiliary switches in the snubber are submitted the same voltage stress as the main switches. The second solution is a TL converter [97]-[98]. Four IGBTs with voltage rating of 1. kv can be used for the above specific application. Although ZCS is preferable for IGBTs as stated above, these TL converters are implemented with ZVS. In Chapter 3 and Chapter 4, two novel solutions are proposed with multi-level and three-level (with asymmetric voltage stresses on the two switch pairs) circuit structures, respectively. Current multiplier and current doubler [99] rectification circuits are applied respectively to enhance the output current capacity.

24 Chapter 1-14 Fig. 1.7 Available options on topology, combination of switch pair and soft-switching scheme for dc-dc power converters with different input voltages and output power levels System Level Single-Step Conversion Concept Typical railway systems are powered by dc transmission lines with voltage levels of 600 V, 750 V, 1500 V or 3000 V [100]. This voltage is then inverted into a 3-phase ac voltage of 400 V, 60 Hz, and further rectified into a dc voltage of 110 V for charging of backup batteries. The 110 V voltage is further converted to lower voltages for supplying the low-voltage equipment (which requires input of 4 V, 3 V, 48 V or 64 V [101]). Fig. 1.8 shows the conventional architecture of the electrical system on metro trains. As illustrated, the energy supplied to the low voltage equipment goes through multiple power conversion stages for converting the high voltage of several kilovolts into low voltages, implying low overall power conversion efficiency. An alternative energy-efficient approach would be to perform the high-voltage to low-voltage dc-dc conversion in a single-

25 Chapter 1-15 step and at high switching frequency as shown in Fig Based on the innovation in system level, it is possible to significantly improve the power conversion efficiency and power density for converters used for on-board low voltage applications. Fig. 1.8 Typical block diagram of the electrical network on metro trains. Fig. 1.9 Proposed block diagram of the electrical network on metro trains.

26 Chapter Fast Transient Control Methods for Load Converters The low output voltages of the high-voltage converters are usually used to supply various low-voltage converters which are exposure to momentary loads. Therefore, it is crucial to improve the dynamic response of those low-voltage converters. Much effort has been made in developing various control schemes for switchedmode dc-dc converters to achieve good output regulation and dynamic response. The controller is designed dominantly with small-signal linearization techniques in frequency domain [10]. However, switching converters are highly nonlinear dynamic systems and their large-signal characteristics will behave differently from that predicted by the smallsignal design approaches. Furthermore, some converter circuits like boost- and buckboost-derived converters are non-minimum phase systems, having a right-half-plane zero in the linearized control-to-output transfer function. They are slow in responding because of larger phase lag between input and output signals, resulting in faulty behavior at the start of a response. This property makes the controller impossible to be designed with classical control theories to achieve fast dynamic response over wide bandwidth of supply and load disturbances. To overcome the limitations of conventional small-signal-based controllers, an alternative concept is to design controllers directly in time domain to achieve fast dynamic responses. One major class of them is switching surface control. The concept is to determine the time sequences to turn on/off switches according to certain constrains, namely, switching surfaces [103]-[106]. Typical switching surface control methods are hysteretic control with zero-order switching surface as shown in Fig. 1.10(a)-(b) or slidingmode control (SMC) with first-order switching surface [107]-[116] shown in Fig. 1.10(c).

27 Chapter 1-17 (a) Voltage hysteresis control (i.e., bang-bang control). (b) Current hysteresis control.

28 Chapter 1-18 (c) Sliding mode control. (d) Boundary control with second/high -order switching surface Fig Switching surface control methods with different switching surfaces.

29 Chapter 1-19 The hysteretic controller tightly regulates the inductor current at the current reference. With further extension on regulating the output voltage, the SMC is the popular choice in boundary control. However, the optimal sliding surface and the stability for fast dynamic response depend on the supply and load characteristics. It is thus difficult to design a set of well-defined control parameters for the sliding surface at all operating points. The control parameters such as the slope of the switching function are sometimes designed by trial-and-error, start-up profile, switching frequency, etc. In general, the converter requires taking several switching actions before settling to the steady-state. The SMC is sometimes applied to the fast control loop and the output is regulated by a proportional-integral (PI) controller. The PI controller is designed by classical control theory or sophisticated design method, like the fuzzy controller. Instead of a linear switching surface, second-order and high-order switching surfaces are proposed for buck converter [117]-[10] as shown in Fig. 1.10(d). These nonlinear switching surfaces are approximately or ideally follow the on/off state trajectories of buck converter. Therefore, the parameters used in the control law are well-defined and the converter can revert to steady-state after two switching actions. A single control law is applicable for buck converter operating in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The control methods are named as boundary control with second/high -order switching surface. Apart from the aforementioned merits, there are several practical issues to apply boundary control with second/high -order switching surface, as well as other switching surface control methods, for dc-dc converters. For example, the switching frequency is varying, the controller performance is sensitive to parameters of the output filter and the inductor is suffered from high peak current. To

30 Chapter 1-0 handle these issues, several techniques have been proposed for buck-converter [11]-[13] to achieve fixed frequency, parameter independent solution or programmed inductor current. However, one remaining fundamental issue which poses great challenges is that the same concept cannot be easily applied to converters with non-minimum-phase characteristics [0]. It is difficult to formulate a simple switching surface on the state-plane for a converter with state trajectories in spiral shape, such as the boost converter discussed in [14]. Part of the objective of this research work is to tackle the above mentioned fundamental issue in switching surface control, therefore, to apply the concept of boundary control with second-order switching surface to all of basic dc-dc converters and make it possible to apply the associated developed control techniques for buck converter to other kind of converters. Accordingly, a uniform second-order switching surface σ on a Cartesian x-y plane rather than the state plane is proposed and discussed in Chapter E-Cap Reduction Technology The considerable power loss of aluminum electrolytic capacitors (E-Caps) observed in the research of high-voltage converters inspires the investigations into capacitors used in capacitor-supported power electronic systems. Meanwhile, from system level perspective, the high input voltage of the converters discussed in Chapter 3 and Chapter 4 is obtained from ac-dc front-end stage. Therefore, low frequency ripples appear in the input capacitors and therefore large electrolytic capacitors are normally required to limit the input voltage variations. As discussed in Section 1.., the widely used E-Caps suffer from short lifetime, which will in turn affect the overall reliability of the system. The replacement of

31 Chapter 1-1 E-Caps by power film capacitors can reduce the power loss and extend the lifetime, however, at expense of considerable increase of cost and volume. Therefore, a practical and feasible approach to deal with the above described issues is to reduce the required capacitance. There are many prior-art methods, which are classified as follows: 1) Performance tradeoff - This simple method allows the dc-link voltage to have large variation with smaller capacitance. However, such approach is practically less impressive as the system performance is degraded. It is only suitable for certain applications, like the ones discussed in [15] and [16]. In [17], a set of procedure for designing an optimal value of the capacitor bank is discussed. ) Reduction of the dc-link capacitor current with sophisticated control. Different control methods are proposed in [18]-[133]. As shown in Fig. 1.11(a), their methodology is based on rendering the current i DC1 to i DC so as to minimize the ripple current i C flowing through the capacitor. The first converter is an active rectifier in [18]-[131], and a step-up dc-dc converter in [13]-[133], while the second converter is an inverter. The advantage of this approach lies in that no auxiliary active switch is needed. However, those control methods cannot be applied to systems with front-end diode-bridge rectifier. Moreover, apart from requiring a sophisticated controller, some of them also rely on specific relationship in the operating frequency between the first and second converters [18], [131], and [13]. The method described in [19] is limited to three-phase systems. The controller described in [18] is based on assuming ideal, lossless energy conversion. Thus, the input current could be distorted unless multiple cell load inverters are

32 Chapter 1- applied. The performance of these controllers is highly dependent on the accuracy of the calculations [130], [133] and affected by the overall time delays within the control loops. 3) Increase in the frequency of dc-link voltage ripple. A double frequency front-end converter that utilizes the multi-phase concept is proposed in [134], resulting in reduced voltage ripple. However, the approach cannot significantly reduce the dclink capacitance. 4) Ripple cancellation circuit with coupled magnetic device. In [135], a coupled inductor is applied to cancel the voltage ripple of the dc input, dc output or dc-link of a power converter. The concept is based on the assumptions that the capacitance is infinite and the turns ratio of the coupled inductor is ideally 1:1. With finite capacitance, the coupled inductor filter and the capacitor becomes a low pass filter. To avoid large size of the coupled windings, the technique is unsuitable for filtering low-frequency voltage ripples, such as those in dc-link capacitors. Moreover, the dynamic response of the capacitor may be degraded due to the series-connected coupled winding. Besides the aforementioned methods, active power filters can also be used for reduction of the dc-link capacitance. They have been traditionally proposed on the ac side for current harmonic reduction in distribution systems or power electronic converters [136]- [147]. There are shunt active filters [140]-[144], series active filters [145]-[147] and hybrid ones [145]. In [148]-[155], active power filters are applied in high-voltage direct-current (HVDC) transmission line and other dc distribution systems for harmonic reduction and dc voltage stabilization. They require an external power source connecting to the input of the

33 Chapter 1-3 active filters to assist the active power control between the source and load. For the application of reducing dc-link capacitance in power electronic conversion systems, the concept of active filters is adopted in [156]-[170]. It is based on connecting an auxiliary circuit in parallel with the dc-link capacitor as shown in Fig. 1.11(b). The added circuit serves as an active impedance or energy source. Different methods of implementing the auxiliary circuit are given. In [157], the auxiliary circuit has a single switch with dissipative resistor. In [161], a relay is placed at the input line and is activated, depending on the dc-link voltage level, resulting in a stable dc-link voltage, but at the expense of reducing the input power factor of the entire system. In [156], [160] and [163], an H-bridge circuit with a current source (inductor) is used to minimize the ripple current of the dc-link capacitor. However, the high inductor current stress and high switching frequency requirement in [163] are the major practical challenges of the method. A current injection method was applied in [159]-[160], [16] and [164] by a half-bridge structure. In [165]- [166], a two-switch converter that can operate bi-directionally in both buck and boost modes is used for the H-bridge front-end and dc current electrical load application. In [167], series-connected dual boost converter is as the shunt active filter for a three-phase diode rectifier front-end conversion system. In [168], the ripple reduction circuit allows an additional power port for enhancing the dynamic response of the whole system. The common challenge of all these methods is that the components used in the auxiliary circuit are under a high voltage stress, which could be as high as the dc-link voltage.

34 Chapter 1-4 Fig Prior-art concepts for reducing dc-link capacitors Organization of the Thesis This thesis contains seven chapters. In Chapter, the concept of adaptive snubber energy for ZCS will be presented. The operating principles of the proposed current-fed FB converter will be described. The trade-off design and small-signal model will be given. Implementations and evaluations of a 530 V / 15 kv 5 kw experimental prototype will be discussed. In Chapter 3, a solution for high-to-low voltage conversion based on a generalized multi-level multi-phase topology will be discussed. The switching mechanism and operation of a typical switch pair will be analyzed. A dc analysis will be carried out to determine the dc conversion ratio and the ZVS conditions in an analytical form. The selfbalance property of the voltages across the input capacitors will be described. A 1500 V / 48 V, kw prototype with four switch pairs in the primary-side is designed, implemented, and evaluated. In Chapter 4, another solution to convert 1500 V dc to 48 V dc will be presented

35 Chapter 1-5 based on a novel concept, by which the voltage stresses on the series-connected two switch pairs are asymmetric. The advantages of a TL converter adopted the proposed concept will be illustrated in terms of utilization of switching devices and load range for soft-switching. A new concept of hybrid ZVS-ZCS scheme will be proposed. The evaluations on a kw prototype will be given to verify the theoretical predictions. In Chapter 5, a uniform second-order switching surface for a fast transient controller of dc-dc converters will be derived. Stability analysis and controller implementation will be discussed. Simulation results on four kinds of dc-dc converters (i.e., boost converter, buck-boost converter, Ćuk converter and SEPIC) will be presented to verify the universal applicability of the proposed control method. Experimental results on a 48 V/48 V buck-boost converter prototype will be also analyzed to exhibit the performance of the controller. In Chapter 6, a patent-pending technology for reducing dc-link capacitance in capacitor-supported power electronic systems will be presented. The operation principle and implementation of the proposed voltage compensator will be discussed. Simulation and experimental results will be provided to verify the theoretical analysis. given. In Chapter 7, conclusions and suggestions for future research on this topic will be

36 Chapter -6 CHAPTER HIGH OUTPUT VOLTAGE ZCS CURRENT-FED FULL-BRIDGE CONVERTER WITH SELF-ADAPTABLE SOFT-SWITCHING SNUBBER ENERGY.1. Introduction This chapter proposes a snubbering technology having an adaptive snubber energy control for ZCS of current-fed dc-dc converters. The snubber is implemented with a switched-capacitor circuit in which the charging and discharging processes of the capacitor are controlled, depending on the loading condition. Therefore, the resonant energy provided for ZCS is self-adaptable and is minimized at different load values. The conduction losses of switching devices are kept minimal while achieving soft-switching. Based on the concept, a novel soft-switched, current-driven FB converter is presented. An adaptive ZCS snubber is connected in series with the primary windings of the isolation transformer. All primary switches are operated with ZCS and the snubber switches are operated with ZVS. For a given input current, the snubber capacitor is charged up to the minimum required energy for ZCS of the switches. Thus, less resonant energy is needed and the currents following through the primary switches never exceed the input current. High efficiencies are expected to be obtained at wide load range. A 5 kw prototype converting 530 V dc to 15 kv dc has been built and the controller is implemented with a digital signal processor (DSP). The testing results confirm the theoretical predictions.

37 Chapter -7.. Current-Fed ZCS FB Converter and Its Operation Principle..1. Circuit Structure Fig..1 Proposed current-fed full-bridge converter with adaptive ZCS snubber. The proposed current-fed FB converter is shown in Fig..1. L is the input inductor to provide an input current source. Four IGBTs S 1 -S 4 are used in the primary-side FB circuit and driven by phase-shift PWM signals. N p and N s are the number of turns of the primary windings and secondary windings of the transformer T r, respectively. L lk is the leakage inductance of T r. A ZCS snubber realized by a switched-capacitor circuit is connected in series with the primary windings of the isolation transformer. The snubber is composed of two unidirectional transistors S a1, S a, and one capacitor C r. A diode bridge formed by D 1 -D 4 is used for the ac-dc rectification. A capacitive filter is applied in the output side, which is preferable in high output voltage application. As defined in Fig..1, V o is the output voltage, i p is the primary current of T r, i o is the rectified secondary current before the output capacitor and v Cr is the voltage across the snubber capacitor C r.

38 Chapter Steady-State Operation Modes Fig.. Timing diagram for analysis of the current-fed FB converter.

39 Chapter -9 Fig.. shows the timing diagram of the proposed converter in one switching cycle. The upper two switches (S 1 and S ) and the lower two switches (S 3 and S 4 ) are driven complementarily, respectively. The driving signals for S 1 and S 4 have a phase difference of 180. The steady-state operations are cyclically divided into 1 modes and are symmetric in the first and the second half cycles. Therefore, the following analysis is given for the first half cycle. For the sake of simplicity, the effect of the magnetizing inductance (3.9 mh in the experimental prototype) of the transformer is neglected. It has been verified by simulation that the soft-switching function and converter operations are not affected by the magnetizing inductance. Fig..3 shows the corresponding equivalent circuits. (a) Mode 0 [before t 0 ] (b) Mode 1 [t 0, t 1 ]

40 Chapter -30 (c) Mode [t 1, t ] (d) Mode 3 (e) Mode 4

41 Chapter -31 (f) Mode 5 (g) Mode 6 Fig..3 Operation modes of the current-fed FB converter (first half cycle). Mode 1 [t 0, t 1 ] [Fig..3(b)]: Before t 0, the circuit topology is shown in Fig..3(a). The input energy is transferred to the load via diodes D and D 3. At t 0, a new cycle begins with S a1 turning off with ZVS. The energy transfer continues. C r is being charged i t I (.1a) p() in I v t t t in Cr () 0 (.1b) Cr The duration of this stage is

42 Chapter -3 t CV I (.1c) 01 r Cr in where V Cr is defined as Iin V v ( t ) t t (.1d) Cr Cr Cr As will be explained in Section.3.1, the duration of this interval is determined to give the minimum capacitor voltage vcr ( t 1) necessary to achieve ZCS of the switches for each value of the line and load currents. ZCS can be achieved at high input current without increasing unnecessarily the capacitor s accumulated energy at a lower input current. That is, the snubber energy is self-adjustable depending on the value of the input (and implicitly the load) current. Mode [t 1, t ] [Fig..3(c)]: At t 1, S 3 turns on with ZCS, the primary current starts reducing. Thus, the current i p flowing through the primary side of T r is V Cr nvo ip () t = Iin cost t sintt (.a) 1 1 Z p where Z p Llk Cr, 1 LC lk r and n is the primary-to-secondary turns ratio of the transformer. The snubber capacitor voltage v Cr is given by v () t I Z sin tt V nv cos tt nv (.b) Cr in p 1 Cr o 1 o The topology ends when the primary current drops to zero, giving the duration of this stage t 1 1 I tan 1 inz p V nv Cr o (.c)

43 Chapter -33 v ( t ) V nv I Z nv (.d) Cr Cr o in p o According to (.a), with a higher I in, one needs a larger V Cr to bring the primary current to zero. When I in is low, the required value of V Cr is also low. Consequently, the durations of the first and second switching intervals are only slightly dependent on the value of I in, no loss of duty-cycle arises from getting such a large ZCS range. Mode 3 [t, t 3 ] [Fig..3(d)]: At t, i p reaches zero, S 4 is switched off with ZCS. As a result, the secondary current reaches zero, and the rectifier diodes turn-off naturally (ZCS). The load voltage is assured by the output capacitor (freewheeling stage) i () 0 p t (.3a) v () t = v ( t ) (.3b) Cr Cr v ( t ) = v ( t ) (.3c) Cr 3 Cr Mode 4 [t 3, t 4 ] [Fig..3(e)]: The PWM dictates the instant t 3 when S is turned on with ZCS. The energy stored in C r is transferred to the load. i p goes negative and increases in absolute value, the presence of L lk in the i p path assures that the rectifier diodes D 1 and D 4 are turned on with ZCS. The current through S 1, is1 () t Iin ip() t, decreases v ( t ) nv Cr 3 o ip () t sin t t3 (.4a) Z p v () t nv V nv cos t t (.4b) Cr o Cr o The stage ends when the primary current in absolute value reaches the input current, giving the duration of this topology 3

44 Chapter -34 t 34 I Z 1 sin 1 in p VCr nvo IinZp nvo (.4c) Cr 4 o Cr o 34 v ( t ) nv V nv cos t (.4d) Mode 5 [t 4, t 5 ] [Fig..3(f)]: At t 4, i p reaches -I in, the current through S 1 drops to zero, so S 1 can be turned-off with ZCS. The energy is transferred from the line to the load. C r is discharged to the load, thus recuperating its energy. i () t I p in (.5a) This mode ends when C r I v t nv t t (.5b) in Cr () o Cr is completely discharged. 4 CnV r o t45 (.5c) Iin Mode 6 [t 5, t 6 ] [Fig..3(g)]: At t 5, S a turns on with ZVS, and the circuit operates in this transfer-energy mode until a new half-cycle is commenced by turning off S a. i () t I p in (.6a) vcr () t 0 (.6a) It can be noted that, in neither stage, the primary current overpasses the input current, keeping thus the conduction losses in the primary switches at their minimum value. S 1 is turned on with ZCS at t 9 and is turned off with both ZCS and ZVS at t 4. S 3 is turned on and off with ZCS at t 1 and t 8, respectively. The operations of S and S 4 are the same as those of S 1 and S 3, respectively. Thus, all of the four switches S 1 - S 4 are switched with ZCS.

45 Chapter Steady-State Analysis.3.1. ZCS Conditions In order to ensure soft-switching of the primary switches, two conditions have to be satisfied: 1) i p has to drop to 0 in Mode, and ) i p given by (.4a) has to reach -I in in Mode 4. By taking (.d) and (.3c) into account, Eq. (.4a) gives V I Z nv I Z nv (.7) Cr in p o in p o It can be noted that i p in (.4a) has to reach -I in. It is equivalent to satisfying the following condition 1 C ( 1 r vcr t3) nvo Llk I in (.8) That is, it requires sufficient energy in C r for reducing the primary current from 0 to -I in. It can be seen from (.7) that for a given converter (with certain values of Z p, n, V o ), V Cr depends solely on the value of I in, i.e. the resonant energy used to achieve ZCS is selfadaptable. As explained in Section.5, I in is sensed, and the minimum necessary capacitor voltage for ensuring ZCS at the measured value of the input current, V Cr, is calculated by (.7). In the first stage, C r is charged. When the sensed value of v Cr reaches the calculated valuev Cr, the switch S 3 (respectively S 4 in the second half-cycle) is turned on, marking the end of this switching stage (i.e., determining the instant t 1 in the timing diagram)..3.. DC Conversion Ratio A phase-shift control is used. The energy transfer is controlled by the delay between S 1 and S 3 in the first half-cycle, and S and S 4 in the second half-cycle. By

46 Chapter -36 assimilating the shift angle with a duty-cycle D, and operating as the boost converter where the on-topology is characterized by the charging of the input inductor, one can define DTs t1 t3 t34 (.9) In order to get the formula of the dc conversion ratio, an input-to-output energy balance written for a half-cycle is obtained 6 1 TV I nv IS (.10) s in in o k k1 where t k ISk ip () t dt. tk 1 By taking into account thatt 3 = DTs t 1 t 34, t 56 Ts/DTst 01 t 45 and using (.1a.5a), (.1c.5c), (.7) and (.9), one gets IS C V 1 r Cr IS C I Z nv V r in p o Cr IS3 0 IS CI Z 4 r in p IS CnV 5 r o IS 6 1 DTs I C V Cr C nv in r r o By inserting the above formulas of IS k (k = 1,,6) in (.10), the dc conversion ratio, M, results

47 Chapter -37 V 1 M V C nv I Z I Z nv I Z n 1 D IT in s o in r o in p in p o in p (.11) Comparing it with the conversion ratio formula for a boost hard-switching FB: M 1/[ n(1 D)] it results that the intervals for forming ZCS lead to a loss of regulation range (i.e. DT s cannot be reduced to zero, if so required for regulation purpose, but its lower limit is t 1 +t 34 ). D loss This loss of regulation is expressed by D loss as follows C nv I Z I Z nv I Z I Ts r o in p in p o in p in (.1) Fig..4 Duty- cycle loss versus normalized input current under different snubber capacitor values (V o = 15 kv, n = 1/0, L lk = 3.6 µh and f s = 0 khz).

48 Chapter -38 D loss is represented versus the normalized input current in Fig..4 (the input current is normalized with respect to its nominal value I in,rated ). It can be noted that D loss increases with the value of C r, but it always has a very small value. And even when increasing the input current, there is only a little change in the duty-cycle loss Maximum Voltage across the Snubber Capacitor C r In the proposed converter, the maximum voltage of the snubber capacitor is crucial in determining the voltage stress across both the primary transistors and auxiliary switches. Fig..5 presents the maximum voltage (v Cr,max = v Cr (t )) of the snubber capacitor for various C r and L lk calculated using (.d) and (.7) for the maximum input current. Larger snubber capacitance and lower leakage inductance are beneficial to reducing v Cr,max. Fig..5 Maximum v Cr versus C r under different L lk values (V o = 15 kv, V in = 0.8 V in,rated, I o = 1. I o,rated, n = 1/0, and f s = 0 khz).

49 Chapter Duration of the Snubber Capacitor Charging / Discharging Intervals In order to increase the soft-switching range, one is interested in keeping the soft switching intervals short. The modes 1,, 4, and 5 create the ZCS and ZVS conditions for the main and auxiliary switches, respectively. Their total duration (= t 0 + t 35 ) calculated for the maximum input current according to (.1c,.c,.4c,.5c) versus C r for different values of L lk is plotted in Fig..6. It can be noted that smaller values of L lk and C r are beneficial for reducing the duration of those intervals. Fig..6 Duration of charging and discharging intervals of the snubber capacitor versus C r under different L lk values (V o = 15 kv, V in = 0.8 V in,rated,and n = 1/0) Regulation and Soft-Switching Boundaries According to (.9),

50 Chapter DT t01 t s 45 t56 (.13) For ensuring the existence of the soft-switching assisting intervals (Modes 1,, 4, 5), the boundary on the duty-cycle are given by the inequality t1 t34 1 t01 t45 D (.14) T T s s By substituting (.1c), (.c), (.4c), (.5c) and (.7), the above inequality becomes 1 ( tan 1 in p ) s T IinZp nvo IinZp I Z 1 C I Z nv I Z D I Ts r in p o in p in (.15) Fig..7(a) gives the operating limits of the duty cycle versus the normalized output current. The intersection between D min and D max represents the minimum load current for which soft-switching is achieved. For the considered design specifications (i.e., V o = 15 kv, n = 1/0, L lk = 3.6 µh, C r = 0.0 µf and f s = 0 khz), the transistors can be soft-switched for a load range starting from 0%. Clearly, ZCS can still be maintained at a heavy current. In Fig..7(b), the voltage on the resonant capacitor at instant t, v Cr (t ), is also given versus the normalized load current within the designed input voltage range. It can be noticed that, except at the maximum load current, this voltage is always smaller than v Cr,max, confirming the self-adaptable characteristics of the proposed soft-switching solution, i.e. at each actual value of the load current, the snubber will use the minimum necessary resonant energy to get ZCS for the primary switches.

51 Chapter -41 (a) (b) Fig..7 (a) Lower and upper boundaries of the duty-cycle for soft-switching versus normalized load current; (b) Adaptive snubber capacitor voltage v Cr (t ) versus normalized load current (V o = 15 kv, n = 1/0, L lk = 3.6 µh, C r = 0.0 µf and f s = 0 khz).

52 Chapter Small-Signal Analysis and Controller Design.4.1. Small-Signal Model and Open Loop Transfer Functions The effective duty cycle Deff D Dloss can be written as D eff 1 1 IinZ p D 1 T s IinZp nv o (.16) by applying a Taylor expansion of (.1) and retaining the first three terms. By superposing ac small-signal perturbations v ˆin, i ˆin, v ˆo, i and ˆd ô on the values of the input voltage V in, input current I in, output voltage V o, output current I o, and duty-cycle D, respectively, after a few manipulations in (.16), one can find the ac small-signal perturbation in the effective duty-cycle as follows ˆ ˆ nl V ˆ nl I d d i vˆ d ˆ d ˆ d ˆ T nv I Z T nv I Z lk o lk in eff in o i v s o in p s o in p (.17) where d ˆ i Qi ˆ and d ˆ Q vˆ, i in v v o Q i nllkvo T nv I Z s o in p, Q v nllk Iin T nv I Z s o in p. Consequently, an averaged linear circuit model is derived as shown in Fig..8. To simplify the analysis, the parasitic resistances of the input inductor, r L, and of the output capacitor, r C, are neglected in the small-signal models in Fig..9 used for derivation of the associated power stage transfer functions. Fig..8 Small-signal model of the proposed converter.

53 Chapter -43 (a) Small-signal ac model with d ˆ 0andi ˆ o 0 (b) Small-signal ac model with vˆ 0andiˆ 0 in o (c) Small-signal ac model with d ˆ 0andvˆ in 0 Fig..9 Small-signal models for derivation of the power stage transfer functions. According to Fig..9, the ac small-signal transfer functions of the power stage are derived as follows G vg v () s () s vˆ () s LCs L R L C s R o ˆ d( s) iˆ o ( s) 0 in L L (.18) G ig iˆ () s Cs 1 R () s (.19) vˆ () s LCs L R L C s R in L dˆ () s iˆ () 0 o s in L L

54 Chapter -44 G id i () s () s ds ˆ( ) vˆ iˆ o() s 0 in ncv si V V R in o in o o L L L LCs L R L C s R (.0) G vd v () s () s ds ˆ( ) vˆ iˆ o() s 0 in ni V LI s o in o in L L LCs L R L C s R in vˆ ( ) ˆ in s d( s) 0 io() s LCs L RL L C s RL (.1) iˆ () s Ai () s = (.) vˆ () s Ls Zo() s =- (.3) i s o vˆ ˆ in ( s) d( s) 0 o() LCs L RL L C s RL where nv Q, ni Q, n(1 D ) and ni Q nv Q. o i in v eff in i o v The ac open-loop transfer functions: input voltage-to-output voltage, G vg, dutycycle-to- output-voltage, G vd, and output-current-to-output-voltage (output impedance), Z o are used in the voltage control closed-loop. The ac open-loop transfer functions: inputvoltage-to-input-current (input admittance), G ig, duty cycle-to-input current, G id, and output current-to-input current, A i, are used in the current control closed loop..4.. Controller Design A current-mode control method is used to control the proposed converter. The equivalent small-signal ac model of the closed-loop regulator is given in Fig..10, where the following notations are used: vˆ e() s - small-signal error voltage. Kv - output voltage scaling factor. Ki - inductor current scaling factor.

55 Chapter -45 G () vc s -transfer function of voltage loop compensator. G () cc s -transfer function of current loop compensator. Fig..10 Closed-loop small-signal ac equivalent model of the regulator. Fig..11 Bode diagram of G id (s) (V o = 15 kv, n = 1/0, L lk = 3.6 µh, C r = 0.0 µf, R L = 45 kω and f s = 0 khz).

56 Chapter -46 Fig..1 Bode diagram of voltage-loop gain Tv ( s ) (V o = 15 kv, n = 1/0, L lk = 3.6 μh, C r = 0.0 μf, R L = 45 k and f s = 0 khz). According to Fig..10, the current loop gain, T i (s), results in T() s K K G () s G () s (.4) i i PWM cc id A PI controller is used for the current loop compensator. Thus, G cc (s) can be expressed as Kii Gcc () s Kip (.5) s G id (s) rather than T i (s) itself is measured in the experimental prototype to determine the parameters K ip and K ii. Fig..11 presents the Bode diagram of G id (s) which provides the information for the PI controller design. The values chosen for K ip and K ii are 6.9 and , respectively. The voltage loop gain, T v, results in

57 Chapter -47 KPWM KvGvc () s Gvd () s Gcc () s Tv () s 1 T( s) i (.6) A PI controller is used for the voltage loop compensator. Thus, G vc (s) can be expressed as Kvi Gvc() s Kvp (.7) s with K vp = 39.45, K vi = Fig..1 shows the Bode diagram of the voltage-loop with and without compensator G vc. The designed controller increases the gain at low frequencies to about 50 db. The designed cross frequency of the voltage-loop is 84.4 Hz. The phase margin is 65 o and the gain margin is 14.5 db. G vc (s) and G cc (s) are transferred into the difference equation forms of v v 6.915( e e ) 1.5e (.8) n n1 n n1 n v v 41.31( e e ) 3.7e (.9) n n1 n n1 n.5. Design Procedure and Experimental Verification The proposed converter is designed and implemented with V in = 530 V±0%, P o,rated = 5 kw, V o = 15 kv. A switching frequency of 0 khz is used, giving T s / = 5 μs. 1) The minimum boundary on L lk is chosen for achieving a soft increase in the primary current (i.e. of the current through S ) at t 3 when S is turned-on. By using Fig..5 and Fig..6, one can choose the values of C r and L lk, for keeping the total duration of the resonant-purposed soft-switching intervals at 4 s (i.e. less than 0% of a half switching period) and for limiting v Cr,max at 931 V (which is the maximum capacitor voltage value attained when the input voltage drops at its lowest value of the given range): L lk = 3.6 μh, C r = 0.0 μf.

58 Chapter -48 ) The ratings of the switches are chosen by considering the voltage and current stresses. The voltage stress of the main switches is I in,max Z p + nv o and that of the auxiliary switches is I in,max Z p + nv o. The current stress of all switches is I in,max. 3) The value of the input inductor is chosen to limit the input current ripple i L.5 % from its nominal value of V o. LnD 1D TV s o il (.30) 4) The value of the output capacitor C o is chosen to limit the voltage ripple V at 0.6% o at C D IT / V (.31) o max o S o 5) The output diodes are chosen by considering the voltage and current stresses. The voltage stress and current stress of the diode are V o and P o,max / V o, respectively. The four main switches are driven by phase-shift PWM signals with adaptable durations of charging and discharging intervals of the snubber capacitor. The driven signals of the two auxiliary switches are generated by detecting the zero-cross point of the voltage of the snubber capacitor. The component values are listed in Table.1. The switches used in the prototype are IGBT modules (having anti-parallel diodes) connected in series with diodes. The function is to perform unidirectional current flow operation. Fig..13 shows the photo of the 5 kw experimental prototype.

59 Chapter -49 Table.1 Component values used in the analysis and experimental prototype. Component Value S 1 ~ S 4 FF150R17ME3G ) (1700 V/150 A) (with RHRP3010 S a1 ~ S a F4-50R1KS4 (100 V/50 A) (with RHRP3010) IGBT driver D 1 ~ D 4 (diode bridge module) C r L lk C o Transformer core SD106AI kv / 3 A 0.0 F 3.6 H 0. F / 30 kv Ferrite EE160 Transformer turn ratios 15: 300 Output voltage resistive divider 1:5000 Fig..13 Photo of the 5 kw experimental prototype.

60 Chapter -50 Fig..14 Simplified software flowchart of the proposed control strategy (ε is a small numerical value). The control system is implemented by a Digital Signal Processor (DSP) TMS30F8335 with a soft-start scheme. The inductor current i L (i.e. the input current I in ) and output voltage V o are sampled to provide the necessary information for the currentmode control and to calculate the minimum snubber voltage V Cr for realizing ZCS using (.7). The instantaneous value of the snubber capacitor voltage v Cr is sensed and compared with the calculated value V Cr. When the measured voltage of the resonant capacitor reaches the calculated value, S 3 (S 4 ) is turned on, thus practically determining the instant t 1 (t 7 ) as a function of the input current/load. Consequently, the energy accumulated in the snubber is the minimum one necessary to get ZCS for the actual input/load current. The maximum v Cr (t 1 ) for getting ZCS is reached at the upper limit of the range of the input

61 Chapter -51 current. Fig..14 presents the simplified software flowchart of the proposed control strategy. The experimental steady-state voltage and current waveforms of the primary switches S 1 and S 3, and auxiliary switch S a1 under full load, and at 5% loading condition, are given in Fig..15 and Fig..16, respectively. One can see from the X-Y plots that the primary switches turn-on/off with ZCS, and the auxiliary switch turns-on/off with ZVS. At a reduced load, soft switching is still maintained. It should be noted that due to the parasitic capacitance in parallel with the isolation transformer, the voltage acorss the primary-side windings can not instantly increase and decrease. Therefore, the captured waveforms of V S1 in Fig..15(a) and Fig..16(a) are not exactly the same as the theorectical one during t 8 -t 9 shown in Fig... (a) Waveforms of v S1 and i S1 (v S1: 500 V/div, i S1 : 5 A/div and timebase: 5 µs/div).

62 Chapter -5 (b) X-Y plot of v S1 and i S1 (v S1: 500 V/div, i S1 : 5 A/div and timebase: 5 µs/div). (c) Waveforms of v S3 and i S3 (v S3: 500 V/div, i S3 : 5 A/div and timebase: 5 µs/div).

63 Chapter -53 (d) X-Y plot of v S3 and i S3 (v S3: 500 V/div, i S3 : 5 A/div and timebase: 5 µs/div). (e) Waveforms of v Sa1 and i Sa1 (v Sa1: 500 V/div, i Sa1 : 5 A/div and timebase: 5 µs/div).

64 Chapter -54 (f) X-Y plot of v Sa1 and i Sa1 (v Sa1: 500 V/div, i Sa1 : 5 A/div and timebase: 5 µs/div). Fig..15 Switching waveforms of S 1, S 3, and S a1 at full load. (a) Waveforms of v S1 and i S1 (v S1: 500 V/div, i S1 :.5 A/div and timebase: 5 µs/div).

65 Chapter -55 (b) X-Y plot of v S1 and i S1 (v S1: 500 V/div, i S1 :.5 A/div and timebase: 5 µs/div). (c) Waveforms of v S3 and i S3 (v S3: 500 V/div, i S3 :.5 A/div and timebase: 5 µs/div).

66 Chapter -56 (d) X-Y plot of v S3 and i S3 (v S3: 500 V/div, i S3 :.5 A/div and timebase: 5 µs/div). (e) Waveforms of v Sa1 and i Sa1 (v Sa1: 500 V/div, i Sa1 :.5 A/div and timebase: 5 µs/div).

67 Chapter -57 (f) X-Y plot of v Sa1 and i Sa1 (v Sa1: 500 V/div, i Sa1 :.5 A/div and timebase: 5 µs/div). Fig..16 Switching waveforms of S 1, S 3, and S a1 at 5% load. The experimental Bode diagrams of G id (s) and T v (s) are given in Fig..11 and Fig..1, respectively, in order to compare the experimental values with the calculated ones. The experimental results are in full agreement with the theoretical expectations. The Bode plot of the voltage loop gain proves a good stability, and good phase and gain margins, of 6º and 17 db, respectively. Fig..17 presents the snubber capacitor voltage v Cr (t ) (in percentage of v Cr,max ) under different line / loading condition (a reduced input voltage attracts an increased input current with a constant output power). One can see that v Cr (t ) is lower for all the conditions, compared with its upper value reached at maximum input/load current. This proves the adaptive characteristic of the soft-switching solution proposed.

68 Chapter -58 Fig..17 Measured v Cr (t ) (in percentage of v Cr,max ) under different line / loading condition. The experimental efficiency versus the load is given in Table.. The efficiencies are 93% at full load and 90.% at 5% load. A comparative study into the efficiencies of the converter at the nominal power with hard-switching and with an un-optimized ZCS scheme (i.e., the designed values of C r and L r are not optimized and the energy provided to achieve the ZCS is not minimum) has been performed. With the optimized RCD snubber in the hard-switched converter, the conversion efficiency is 83%. With the un-optimized ZCS scheme, the conversion efficiency is 89%, which is higher than the hard-switched converter. Nevertheless, the efficiency is less than the one with the proposed self-adaptable soft-switching snubber energy scheme. This confirms the advantages of the proposed method.

69 Chapter -59 Table. Experimental efficiency versus load (V in = 530 V, I o,rated = 1/3A). Load (percentage) Efficiency 5% 90.% 50% 91.3% 100% 93%.6. Chapter Summary In this chapter, a new soft-switched FB converter utilizing an adaptive snubber has been proposed. It is particularly useful for high-voltage applications. The primary switches are operated with ZCS, allowing the use of IGBT. The auxiliary switches are operated with ZVS. The rectifier diodes are operated with ZCS naturally. The maximum current stress on all the switches is the input current. Soft switching is achieved over a very wide line and load range. The main characteristic of the solution is its self-adaptability: the snubber energy necessary to get ZCS for the main switches is adaptable and is dependent on the value of the primary current. Only at the maximum input current (reached at the maximum load current and lower limit of input voltage range), the snubber capacitor will be charged to the maximum level. For the other value of the input current, less snubber energy is used. It can avoid unnecessary energy circulation, and thus reduce conduction loss. In each cycle, all the energy accumulated in the snubber capacitor for soft switching is recuperated to the load. A current-controlled feedback has been implemented with a DSP. Experimental results measured on a 5 kw, 530 V/15 kv prototype confirm the advantages of the proposed converter.

70 Chapter 3-60 CHAPTER 3 HIGH INPUT VOLTAGE MULTI-LEVEL MULTI-PHASE DC-DC CONVERTER 3.1. Introduction This chapter presents a generalized multi-level multi-phase circuit structure for high input voltage to low load voltage applications. The proposed structure is formed by n switch pairs on the primary side, an n-phase isolation transformer with the primary windings connected to dc-blocking capacitors, and an n-phase current multiplier on the output side. The switching patterns applied to the switch pairs have a phase difference of 360 n, and the output inductor currents are interleaved correspondingly, making necessary a smaller output filter. With input voltage V in and load current I o, the converter features V in /n voltage stress on the primary-side switches, and I o /n current stress on the secondary-side inductors and diodes. The primary-side switches are commutated with ZVS. The proposed circuit structure is especially suitable for generating low voltages for the on-board applications of metro trains from the widely used 1.5 kv or 3 kv dc line in a single step. Moreover, as the switching devices on the primary side withstand a fraction of the input voltage only, the most popularly chosen 500/600 V MOSFETs can be used in the proposed circuit with several kilovolts supply voltage, allowing for a higher operation frequency and lower conduction losses. A 1500/48 V, kw prototype with four switch pairs has been designed, implemented and evaluated. The experimental results prove the soft-switching behavior and low voltage stress of the primary-side switches, and low current flowing through the rectifier s diodes and inductors.

71 Chapter Generalized Circuit Structure and Its Operation Principle Circuit Structure Fig. 3.1 General structure of the proposed multi-level multi-phase dc-dc converter. Fig. 3. Circuit structure of the (k-1)-th and k-th switch pairs and rectifier branches. The generalized structure of the proposed converter is shown in Fig It is formed by n switch pairs on the primary side and an n-phase isolation transformer with

72 Chapter 3-6 turns-ratio m. The primary windings are connected to the switch pairs with each winding having a series-connected dc-blocking capacitor, while the secondary windings are connected to an n-phase rectifier. The dc-blocking capacitors have the same value. There are n dc-link capacitors C 1, C,, C n of the same capacitance to split equally the input voltage V in. Each switch pair SP k is connected across a dc-link capacitor C k (k = 1,,, n). The structure of the (k-1)-th and k-th switch pairs and associated rectifier branches is shown in Fig. 3.. The dc-blocking capacitors connected to the primary windings are C W1, C W,, C Wn. Each switch pair contains two switching devices, S ku and S kd (with the built-in diodecapacitor pairs D ku -C ku and D kd -C kd ) operated in anti-phase. The switching patterns applied to the two adjacent switch pairs have a phase difference of 360 n. The output current is shared by n identical parallel diode-inductor branches D 1 -L f1, D -L f, and D n -L fn to reduce the current stress of the inductors to one-nth of the load current Operation Principle (a) Timing diagram in one steady-state cycle.

73 Chapter 3-63 (b) Detailed timing diagram of the k-th switch pair in the k-th interval of T s. Fig. 3.3 Operation timing diagram of the proposed converter.

74 Chapter 3-64 The output voltage is regulated by varying the duty cycle, the same in each switch pair. Fig. 3.3(a) gives the timing diagram of the proposed converter in one switching cycle and Fig. 3.3(b) presents the detailed operation timing diagram of the k-th switch pair in the k-th interval T s /n. The duty cycle D is defined by the on-time of upper switch S ku over the total duration of the k-th interval, T s /n. A dead time is added for soft-switching transitions. The operation modes for the switch pair SP k are theoretically analyzed based on the following assumptions: a) the equivalent parasitic capacitors paralleled with each MOSFET are of the same value C s, b) the input voltage is shared evenly by the n input capacitors (this will be proved in Section 3.3), and c) the leakage inductances of each transformer winding have an identical value of L lk. The status of the other switch pairs keeps unchanged during the discussed time interval. v Wx denotes the voltage on the primary winding W x, v wx denotes the voltage across the secondary winding w x, i Wx denotes the primary current flowing through W x, i px denotes the primary-side current circulating through the switches, or their parasitic capacitances, of switch pair SP x, and i Dx is the current flowing through diode D x. During the considered k-th interval: [t k0, t k0 +T s /n], with the exception for the switches in the pair SP k, all the other switches do not change their status: all the upper switches are in the off-state and all the lower switches are in the on-state. Similarly, all the rectifier diodes, except D k, are conducting in a freewheeling mode. Generally, the converter transfers energy when the upper switch of the k-th switch pair SP k is on and then enters into the freewheeling stage until another energy transfer stage begins after the upper switch of the (k+1)-th switch pair SP k+1 is on. Therefore, the energy transferred from primary-side to secondary-side is in a sequential manner in one steadystate cycle, allowing for an interleaved operation of the output inductors. During the

75 Chapter 3-65 transition intervals, the freewheeling currents in the primary-side or output inductor currents are used for providing the ZVS conditions for turning on MOSFETs. The detailed analysis allowing for steady-stage analysis and design of the prototype in Section 3.3 and Section 3.4 are given based on the following equivalent operation modes shown in Fig (a) Mode k_0 [Before t k0 ]. (b) Mode k_1 [t k0, t k1 ].

76 Chapter 3-66 (c) Mode k_ [t k1, t k ]. (d) Mode k_3 [t k, t k3 ]. (e) Mode k_4 [t k3, t k4 ].

77 Chapter 3-67 (f) Mode k_5 [t k4, t k5 ]. Fig. 3.4 Operation modes of the k-th switch pair in the k-th interval of a switching cycle. Mode k_1 [t k0, t k1 ]: Before t k0, as shown in Fig. 3.4 (a), the upper switches S (k-1)u and S ku are off and the lower switches S (k-1)d and S kd are on. Capacitor C ku is charged at V in /n. The converter is in a freewheeling mode. The values of the currents before t k0 will be proven in Section They are i W(k-1) (t k0 ) = (n-1) i o /(mn ), i Wk (t k0 ) = -i o /(mn ), i Wx (x =1,,,n, x k-1, k) = -i o /(mn ), i D(k-1) (t k0 ) = 0, i Dk (t k0 ) = i o /n, i D(k+1) (t k0 ) = i o /n, i Dx (x = 1,,,n, x k-1,k, k+1) = i o /n. The voltages across the primary windings at t k0 are zero. At t k0, S kd is switched off with ZVS due to the presence of C kd. C ku is discharged and C kd is charged in a resonant manner, providing the ZVS condition for S ku turn on at t k1. In this mode, the voltage across C kd,v CkD, increases from 0 to V in /n, and the voltage on C ku, v CkU, decreases from V in /n to 0. It can be assumed that the voltage across the dc-blocking capacitor C W(k-1) keeps constant within one steady-state cycle with value of V in /n (this will be proved in Section 3.3.3). According to Fig. 3.4(b), from a KVL equation written in the loop formed by S (k-1)d in on-state, C W(k-1), C ku and primary winding W k-1, it results that v W(k-1) goes from a zero value to a negative one (-V in /n). Similarly, by writing a KVL equation in

78 Chapter 3-68 the following loop, formed by C kd, C k+1, C Wk and primary winding W k, it results that v Wk increases from zero to a positive value V in /n. Therefore i0 ipk () t ipk ( tk 0)cos( t) cos( t) (3.1) mn Vin io Llk vcku () t sint (3.) n mn C s io Llk vckd () t sint (3.3) mn C s io Llk vwk () t VC ( k 1) vckd () t VCWk sint (3.4) mn C io Llk vw( k1) () t vcku() t VCW( k1) sint (3.5) mn C 1 i io i () t i ( t ) v () t dt 1 cos t L mn mn (3.6) o Wk Wk k 0 Wk lk W( k1) W( k1) k0 W( k1) lk 1 n1 io io i () t i ( t ) v () t dt 1 cost L mn mn (3.7) where L C. 1 lk s Taking into account that i Dx = i Lfx - i secx (x = 1,,, n) and that the inductor currents keep their values at the transition instant, it results s s io idk () t ilfk () t m iwk () t iw ( k 1) () t 1cost n (3.8) io io id( k1) () t ilf ( k1) () t m iw( k1) () t iw( k ) () t 1cos( t) n n (3.9) io io id( k1) () t ilf ( k1) () t m iw( k1) () t iwk() t 1cos( t) n n (3.10)

79 Chapter 3-69 Diode D k-1, which is off in the previous T s /n period, starts conducting because the primary-side current i p(k-1) becomes smaller than the corresponding reflected output inductor current i Lf(k-1), indicating the transition from an energy transfer mode to a freewheeling mode of this rectifier branch. During the first mode, all the diodes are on. Therefore, the converter is still in the freewheeling mode. This mode ends when v CkD reaches V in /n and v CkU decreases to zero. From (3.), the duration of this mode is given by sin mvin tk tk tk io Llk C s (3.11) Mode k_ [t k1, t k ]: As v CkU (t k1 ) = 0, D ku conducts naturally. After a while, S ku turns on with ZVS. The primary-side current i pk increases linearly, remaining less than the reflected output inductor current i Lfk. Therefore, the converter is still in the freewheeling stage. According to Fig. 3.4(c) v () t v () t V V V / n (3.1) Wk CkD C( k 1) CWk in v () t V V / n (3.13) W( k1) CW( k1) in 1 io Vin i () t i ( t ) v () t dt t L (3.14) mn nl Wk Wk k1 Wk lk 1 n1 io Vin i () t i ( t ) v () t dt t L (3.15) mn nl W( k1) W( k1) 1 W( k1) lk io Vin ipk () t iwk () t iw ( k 1) () t t (3.16) mn nl io Vin ip( k1) () t iw( k1) () t iw( k) () t t (3.17) mn nl lk lk lk lk

80 Chapter 3-70 Vin ip () t i ( 1) ( 1) () () k W k t iwk t t (3.18) nl io io mvin idk () t ilfk () t mipk () t 1 cost t n (3.19) n nl mvin id( k1) () t ilf ( k1) () t mip( k1) () t t (3.0) nl io mvin id( k1) () t ilf ( k1) () t mip( k1) () t t (3.1) n nl lk lk lk lk During this mode, the leakage inductance of the winding W k is charged. The mode ends when i pk reaches the reflected secondary-side current i o /(mn), indicating the end of the freewheeling stage. During this mode, the primary winding W k is supplied with voltage V in /n, while the voltage across the corresponding secondary winding w k is zero (the secondary side is still in freewheeling mode, even if the primary-side switch is turned on with the purpose of starting the transfer of energy. This phenomenon is typical for ZVS in FB converters), resulting in a duty cycle loss. According to (3.16), the duration of this interval is given by il o lk tk1 tk tk1 (3.) mvin At the end of the second mode, D k turns off with ZCS according to (3.19) and (3.). At the instant t k, according to (3.14)-(3.1), the values of the currents are: i Wk (t k ) = (n-1)i o /(mn ), i W(k-1) (t k ) = -i o /(mn ), i pk (t k ) = i o /(mn), i p(k-1) (t k ) = 0, i p(k+1) (t k ) = -i o /(mn), i Dk (t k ) = 0, i D(k-1) (t k ) = i o /n, and i D(k+1) (t k ) = i o /n. Mode k_3 [t k, t k3 ]: The converter enters the energy-transfer stage. The voltages across primary windings v Wk and v W(k-1) are V in /n and -V in /n, respectively. In the secondary side, the winding voltages v wk and v w(k-1) become the reflected voltage values of associated

81 Chapter 3-71 primary windings: V in /(mn) and -V in /(mn), respectively. The currents on both primary and secondary sides are constant, by assuming that the current variations in the output inductors are negligible. Mode k_4 [t k3, t k4 ]: According to the controlled PWM signal, S ku is turned-off at t k3 with ZVS due to the parallel capacitance across the switch. The converter is commutated from the energy-transfer stage to the freewheeling stage. C ku and C kd are charged and discharged respectively by i pk / 1 io vcku () t ipk () t dt t C (3.3) mnc s Vin 1 Vin io vckd () t ipk () t dt t n C (3.4) n mnc s Vin io vwk () t VC ( k 1) vckd () t VCWk vckd () t t (3.5) n mnc Vin io vw( k1) () t vcku() t VCW( k1) t (3.6) n mnc s s s s This mode ends when C kd is fully discharged. According to (3.4), the duration is mvincs tk34 tk4 tk3 (3.7) i o Mode k_5 [t k4, t k5 ]: At t k4, the body diode of S kd conducts naturally. Therefore, S kd can be turned on with ZVS subsequently. From KVL written in the same loops as in the first Mode, it results that the voltages across primary-side and secondary-side windings are zero and no energy is transferred from the primary-side to secondary-side. The converter operates in a new freewheeling stage. All of the currents keep constant and remain the values as the ones calculated at the instant t k during the third, fourth and fifth modes. Therefore,

82 Chapter 3-7 n1 io io iwk () t, i (),( 1,,,, ) Wx t x n xk (3.8) mn mn n1 io io iwk () t, i (),( 1,,, ) wx t x n xk (3.9) n n io io ipk () t, ip( k 1) () t, ipx() t 0,( x1,, n, x k, k1) (3.30) mn mn io io iseck () t, isec( k 1) () t, isecx () t 0,( x1,, n, x k, k 1) (3.31) n n io io idk () t 0, id( k 1) () t, idx () t,( x1,, n, x k, k1) (3.3) n n For the other n-1 T s /n intervals in Fig. 3.3(a), the converter operates in a similar manner Steady-State Analysis DC Voltage Conversion Ratio and Duty Cycle Loss During the analyzed k-th interval, the transfer of power from input to load occurs during Mode k_3 by neglecting the energy transferred during the switching transition t k34 for ZVS. An input-output energy balance written for a T s /n interval gives V V i DT T n n mn n n tk 3 in in o s s ipk () t dt t tk 01 tk1 Voi (3.33) o k t k01 is very short and thus negligible compared to t k1. Therefore, according to (3.) and (3.33), the conversion ratio M and duty cycle loss D loss are given by M Vo 1 niol lk D Vin mn mvints (3.34)

83 Chapter 3-73 D loss ni L mv T o lk (3.35) in s ZVS Load Range For the lower switch S kd, the energy stored in both output inductor and leakage inductor provides the ZVS turn-on condition. However, for turning on the upper switch S ku, as illustrated in Mode k_1, only the energy stored in the leakage inductor is used to discharge the parallel capacitor C ku. Therefore, the ZVS load range is determined from (3.) by the condition that v CkU reaches zero 1 io Llk 1Vin C mn n s (3.36) Moreover, the durations of the left and right dead time between the two PWM signals of each switch pair should be long enough to fully discharge the parasitic capacitor voltage t dl mv sin in tk (3.37) io Llk Cs t dr mvincs tk 34 (3.38) i o where t dl and t dr are the dead time of left and right sides respectively Self-Balancing Mechanism of Switch-Pair Voltage Fig. 3.5 represents a voltage loop during the freewheeling stage shown in Fig. 3.4(f). Let V in(k-1) and V ink denote the voltages across the input capacitors C k-1 and C k, respectively. During the freewheeling stage, the voltage across the transformer winding W k-1 is zero,

84 Chapter 3-74 implying an equality between the voltages on capacitors C k and C W(k-1). In case that a perturbation occurs, the current through the loop will equalize the two capacitor voltages. V V (3.39) CW k 1 ink Fig. 3.5 Voltage loop during the freewheeling stage of k-th switch pair. In practice, the voltage across the dc-blocking capacitor C W(k-1) is relatively constant over one switching cycle. From KVL written in a loop formed by C (k-1)d, C ku, C W(k-1) and W k-1 in Fig. 3., as the winding average voltage is zero in a steady-state cycle, it results that VCW ( k1) vcw ( k 1) vcku vck 1, where v D CkU and vck 1 represent the average value over D a cycle. Referring to Fig. 3.3(b), the average voltage v CkU in one cycle is given by

85 Chapter 3-75 v CkU Tstk0 tk1 tk tk3 tk4 Tstk0 v () t dt v () t dt v () t dt v () t dt v () t dt v () t dt T T t CkU k0 t CkU k0 t CkU k1 t CkU CkU CkU k tk3 tk4 s s tk1 tk4 Ts vcku () t dt00 vcku () t dt T t s Dk tk 34 Vink k0 t k3 (3.40) T s n where D k is the duty cycle of switch pair SP k. In Mode k_1, as the duration t k01 is very short, sin t t, (3.), (3.11), (3.3), (3.7), (3.40) give v CkU D n 1 k V ink (3.41) Similarly, the average voltage v C(k-1)D in one cycle is given by Dk 1 v 1 V 1 ( k 1) Ck D ink (3.4) n where D k-1 (k 1) is the duty cycle of switch pair SP k-1. According to (3.41)-(3.4), 1 VCW ( k 1) vcku v 1 Vink Dk 1Vin 1 DV k ink ( k 1) Ck D k (3.43) n Substituting (3.43) into (3.39), one gets V V ink in( k 1) D ( k 1) ( k 1) (3.44) D k A simple control scheme with only one voltage loop is configured for the proposed converter. A pair of PWM signals is generated and then shifted by times of 360 n to drive other switch pairs. Therefore, by neglecting tiny differences that could appear in the shifting process, the duty cycles of the generated PWM driving signals are the same. Duty cycle imbalances caused by the mismatched driver dead time and MOSFET switching characteristics can be removed by system calibration [170], implying a negligible difference

86 Chapter 3-76 between D k and D k-1. As a result, regardless of the capacitors values, the voltage distribution on each input capacitor will reach parity after a few switching cycles from start-up or other dynamic perturbations, except for no load condition. According to (3.39), it implies that the voltage across the dc-blocking capacitor C W(k-1) is equal to V in / n Steady-State Current Distribution in the Transformer Windings It is essential to study the steady-state current distributions in the transformer windings, therefore, to verify the initial values used for analysis of the first mode in Section 3.. As shown in Fig. 3.3(a), there are n energy-transfer stages in one cycle. The current in each output inductor is considered to have a constant value i o /n. As diode D x is blocked in the x-th energy-transfer stage (x = 1,,, n), stage1: iw 1,1 iwn,1 ilf1 io / n stage : iw, iw 1, ilf io / n stage n: iwn, n iw( n1), n ilfn io / n (3.45) where i wj,k denotes the current through the secondary-side winding w j in the k-th energy transfer stage. It can be observed from Fig. 3.3(b) that a winding current changes its value only two times in a steady-cycle T s. Such a change can take place only in the first two operation modes after the transition from a T s /n interval to the next T s /n interval. For example, i wk, which is -i o /n before the beginning of the k-th interval, will change to (n-1)i o /n during the first two modes of the k-th interval and will change again to -i o /n after the transition to the (k+1)-th interval. Therefore, during the transition from the k-th energy-transfer stage to (k+1)-th energy-transfer stage, the currents in the corresponding two adjacent windings w k

87 Chapter 3-77 and w k+1 decrease and increase respectively by the same amount of current defined as i, and those in other secondary windings keep constant. It can be shown that iw 1,1 iw 1, ni, iw,1 iw, n,, iwn ( 1),1 iwn ( 1), n, iwn,1 iwnn, i iw 1, iw 1,1 i, iw, iw,1 i, iw3, iw3,1,, iwn, iwn,1 iw1, niw1,( n1),, iwn ( ), niwn ( ), n1, iwn ( 1), niwn ( 1), n1 i, iwnn, iwnn, 1i (3.46) Considering that the initial current of the transformer is i i i (3.47) w1, k w, k wn, k0 By solving (3.45)-(3.47), one gets n1 io io i io / n, iwk, k, i wx, x ( x1,,, n, and xk) (3.48) n n Therefore, the current distribution in the primary windings during steady-state is given by n1 io io iwk, k, i Wx, x ( x1,,, n, and xk) (3.49) mn mn According to (3.48), the currents in the secondary windings of the isolation transformer at the beginning of the k-th stage are given by i wk ( 1) 0 n1 io ( t ) (3.50) n io iwx ( t0) ( x1,,, n, and x k 1) (3.51) n Based on (3.50)-(3.51), the initial currents flowing through the primary windings and rectification diodes of the analyzed k-th interval in Section 3. are given by the following equations (3.5) and (3.53), respectively.

88 Chapter 3-78 n1 io iw( k1) ( t0) mn io iwx( t0) ( x 1,,, n, and x k 1) mn (3.5) idk ( 1) () t ilf( k1) iwk ( 1) i wk ( ) 0 io idk () t ilfk iwk i w( k 1) n io idx() t ilfx iwx i w( x1) ( x1,, n, x k1, k) n (3.53) 3.4. Design Considerations Design Specifications Design considerations are presented for the specified prototype shown in Table 3.1. The variation of the input voltage is within ±10% of the nominal value 1500 V. A converter with four switch pairs are selected here as a demonstration example, i.e. n = 4. Table 3.1 Design specifications of the proposed dc-dc converter with four switch pairs. Items Values Units Remarks V in,min 1350 V minimum input voltage V in,rated 1500 V rated input voltage V in,max 1650 V maximum input voltage V o 48 V output voltage P 000 W rated output power f 50 khz switching frequency n 4 number of modules I o 10 % current ripple V o 1 % voltage ripple T h 0 ms hold-up time from 1500V to 100V D eff,designed 0.5 designed effective duty cycle

89 Chapter Turns Ratio of the Isolation Transformer (m) According to (3.34), where D D ni L mv T eff o lk in s in eff o m V D n V (3.54). By substituting n = 4, V in = 1500 V, V o = 48 V, D eff,min = 0.5 into (3.54), it results in m = Thus, the value of m is practically chosen to be close to such theoretical value Design of the Value of the Leakage Inductance (L lk ) The leakage inductance is a very crucial parameter to determine the duty cycle loss and soft-switching range as shown in (3.35) and (3.36), which are represented in Fig. 3.6 and Fig It can be observed that a lower inductance value is beneficial to reducing the duty cycle loss while narrowing the soft-switching range. Therefore, a trade-off design between duty cycle loss and ZVS load range is considered. Consequently, L lk is selected with the value of 0 μh to achieve soft-switching from a 60% load and above. The duty cycle loss at nominal load will be 0.11 accordingly. It should be noted that the leakage inductance of isolation transformer depends on the design and fabrication process conducted by the manufacturer. On the one hand, it is unnecessary to design transformers with the required leakage inductance because an external inductor can be placed in series with the primary windings of the transformer. On the other hand, the leakage inductance is usually pre-determined, provided by the manufacturer. The components used in the converter are thus designed with the leakage inductance.

90 Chapter 3-80 Duty cycle loss 0,30 0,5 0,0 0,15 0,10 10% load 30% load 50% load 80% load 100% load 0,05 0, Leakage inductance (µh) Fig. 3.6 Duty cycle loss versus leakage inductance under different loading condition (V in = 1500 V, I o,rated = 41.7 A, m = 1, n = 4, f s = 50 khz). 100% Starting point of soft-switching I o /I o,rated 90% 80% 70% 60% 50% 40% 30% 0% Leakage inductance (μh) Fig. 3.7 Minimal load for soft-switching versus leakage inductance (V in = 1500 V, I o,rated = 41.7 A, m = 1, n = 4, f s = 50 khz).

91 Chapter Design of Output Inductors (L f ) Fig. 3.8 Rectifier inductor currents and output current (n = 4). Fig. 3.8 shows the relationships between the theoretical inductor current of each rectifier branch (phase) and the output current with n = 4. Assuming that the inductors are identical (i.e. L f1 = L f = = L fn ) one can obtain the phase current ripple D ilfk 1 n VT Lf eff o s (3.55) The output current ripple is given by VT o s io 1 Deff (3.56) Lf Therefore, the output current ripple is reduced to n1 Deff n Deff times of the phase current ripple. For n = 4, D eff = 0.5, the output current ripple will be 57% of the phase current ripple. The output inductor is designed according to the required i in Table 3.1 as o

92 Chapter 3-8 L f min D VT o s 1 eff,min io (3.57) For each phase, an inductor with a value of 14 µh is chosen Design of Output Capacitor (C o ) The output voltage ripple and RMS current of the capacitor I, vo Co rms are given by / ir _ io Ts n o ESR C v o o (3.58) 8C o I Co, rms 3 i (3.59) o 6 The capacitance C o, equivalent series resistance (ESR) R ESR_Co, and ripple current rating I AC of the capacitor are selected to ensure that the output voltage ripple is less than 1% of the nominal value, and I Co,rms is lower than I AC. Accordingly, two capacitors with C o = 0 µf, R ESR = 1 mω and I AC = 1.49 A are used in parallel for the testing prototype. The power dissipation of the output capacitor is approximately equal to ir 1. o ESR Design of Input Capacitors and DC-Blocking Capacitors The input capacitor voltage ripple and hold-up time are used to choose the values of the input capacitors. By neglecting the transition period t k01 and t k34, the current flow Deff io i eff o through capacitor C k, i i i n D i o C k in pk when the upper switch S ku is mn mn mn Deff io on, and ic i k in when S ku is off. Therefore, the voltage ripple on the capacitor C k mn is given by

93 Chapter 3-83 nd i D T nd i R _ eff o eff s eff o ESR Ck k mn VC (3.60) k mn C where R ESR _ C k is the ESR of the selected capacitors to ensure V Ck is within 1% of V in /n. The input capacitors are designed by considering the 0 ms hold-up time from 1500 V to 100 V. It results in C in V PT o h in, rated Vin, drop (3.61) where T h is the designed hold-up time, V in,rated is the nominal input voltage, V in,drop is the designed voltage drop within the hold-up time period, and η is the designed efficiency (η = 90% for calculation). The minimum calculated value C in is μf. Accordingly, four 400 V (450 V surge) 680 μf electrolytic capacitors with ESR of 150 mω at 100 Hz are selected for C 1 -C 4. Film capacitors are selected for the dc-blocking due to their high current capability and low ESR properties. In dc-dc converter applications, the selection of film capacitors applied for dc-blocking mainly depends on the required capacitance limited by voltage ripple. By neglecting the transition intervals, according to Fig. 3.3, the voltage ripples of the dc-blocking capacitors are given by ( n1) i T VCWk (3.6) C mn n 1 o s Wk The value of the capacitance is designed to ensure the voltage ripple of each capacitor is less than.5%. In the prototype, the voltages across C W1, C W, C W3 are V in /4 and the voltage stress of C W4 is (3 /4) V in. Accordingly, 400 V/4.7 µf metallized polyester film capacitors with measured ESR of 14.3 mω at 50 khz are selected for C W1, C W, C W3 and

94 Chapter V/1.5 µf metallized polypropylene film capacitor with measured ESR of 9.9 mω at 50 khz is chosen for C W Selection of MOSFETs and Diodes The voltage stresses of the MOSFETs are V in /n and the current stresses are i o /mn. The voltage stresses of the secondary-side diodes are V in /(mn) while their average currents are i o /n. According to the specifications, 600 V/35 A MOSFETs (SPW35N60CFD) and 600 V/ 15 A diodes (FFH15S60S) are used. Table 3. shows the design cases for different level of input voltage. The designed number of switch pairs, associated turns-ratio of the transformer and voltage rating of MOSFET are given to convert the input voltages to 48 V. It can be noted that in all these cases, the widely used 500 or 600 V MOSFET can serve for implementing the proposed converters. Table 3. Number of switch pairs, turns ratio of transformer and voltage rating of MOSFET for specific input voltage. V in (V) n m Rating of MOSFET V DS (V) 600 3: : : : : :1 600

95 Chapter Experimental Verifications Based on the specifications given in Table 3.1, a kw 1500 V / 48 V prototype with four switch pairs has been built and tested as shown in Fig It should be noted that the four phase transformer is carried out with four separate cores (i.e., four single phase transformers) in the prototype. The experimental results are shown in Fig Fig Fig. 3.9 Photo of the experimental prototype. The PWM driving signals for switch pairs SP 1 and SP are measured as shown in Fig All of the values are measured at the point when the PWM signals increase to 50% of their high level. The duty cycles for SP 1 and SP are and 0.606, respectively, implying a negligible difference. The left and right dead times between driving signals for upper and lower switch in one switch pair are 360 ns. The phase shift angle between the observed two switch pairs is 90.4, which is very close to the theoretical value of 90.

96 Chapter 3-86 Fig Measured PWM driving signals for switch pairs SP 1 and SP (v GS1U, v GS1D, v GSU and v GSD : 10 V/div, Timebase: µs / div). Fig gives the switching waveforms of switch pair SP 1 under various loading condition (i.e. 100%, 80% and 60% of the nominal load). It can be observed that both switching transistors are turned on/off with zero-voltage, implying a negligible switching loss. With load variations, the reflected load current in the primary-side changed; therefore, the slopes of the MOSFET voltages have a small difference during the ZVS commutation intervals. The voltage stresses on the two switches are only one-fourth of the total input voltage. The switching waveforms of other switche pairs are similar with those of S P1.

97 Chapter 3-87 Fig ZVS turns on/off of one switch pair under different loading condition (v GS1U and v GS1D : 10 V/div, v S1U and v S1D : 00 V/div, Timebase: 00 ns/div).

98 Chapter 3-88 Fig Waveforms of transformer primary-side winding current i W1, voltage of S 1D and driving signals for the switch pair SP 1. Fig Waveforms of output inductor currents.

99 Chapter 3-89 Fig Waveforms of driving signals and currents in one rectification branch. Fig. 3.1 shows the waveform of the current i W1 flowing through the primary-side winding of the isolation transformer. The current stresses, thus, the conduction losses of the primary-side switches depend on the primary-side currents in the isolation transformer windings. Fig presents the waveforms of the four output inductor currents. Due to the self-balancing mechanism of the input capacitor voltages and well-balanced power stage design, the prototype shows a good performance of output phase current sharing among different rectification branches, with T s /4 phase shift between two adjacent inductor currents. It can be observed from the waveforms that the discrepancy between the largest inductor current and smallest inductor current is 0.96 A, which is acceptable when considering the design margin of the output inductors.

100 Chapter 3-90 Fig gives the inductor and diode currents in one rectifier branch. It can be noted that both the current stress of the inductor and average current of the diode are 1/n of the output current. Therefore, the magnetic size of the inductors and the conduction loss of the diodes are reduced, giving an improved efficiency and well thermal distribution. The waveforms are in a good agreement with the theoretical analysis. The efficiency is measured at different loading condition, starting at light load where ZVS is lost, and up to nominal load. The results are plotted in Fig The efficiency measured at around nominal power rating (P o = 03 W) is 90.75%. The power losses in different components are measured under full load as shown in Fig The input power is 9. W and the ratios between the power loss in specific component and input power are also indicated in the figure. It can be noted that the major losses are in the passive components, i.e. isolation transformers, output inductors and rectifiers, while the total loss in the MOSFETs is only.51% of the input power. It implies that the power loss of the MOSFETs is dominantly induced by the conduction loss and their switching loss is negligible with the aid of ZVS switching.

101 Chapter Hard-switching Soft-switching Efficiency (%) Output power (W) Fig Measured efficiency under various loading condition. Fig Measured losses in the components under full load (P in = 66.8 W and the ratios between the power loss in specific component and input power are indicated in percentage).

102 Chapter Chapter Summary A generalized circuit structure for high input voltage dc-dc power conversions is presented. It performs the conversion from several kilovolts to a low voltage of 48 V in a single step. The voltage stress on the primary-side switches and the current stress in the secondary-side inductors/diodes are reduced to 1/n of the input voltage and output current, respectively. Therefore, it allows the use of MOSFETs with low voltage rating and diodes with low current rating. ZVS of the switching devices achieves a negligible switching loss. The voltages across the input capacitors and the currents through the output inductors are well-balanced due to the intrinsic self-balancing mechanism. The current multiplier with interleaved rectification in the secondary-side reveals high current capacity and reduced size of magnetic components. The experimental evaluations on a 1500 /48 V kw prototype with four switch pairs verify the theoretical analysis. An efficiency of 90.75% is obtained at nominal load. Compared with other available topologies, as shown in Table 3.3, the proposed structure represents the optimum one with respect to the voltage stress on the switches and number of switches. Especially, compared with FB- based ISOP converters, the proposed converter withstands the same voltage stress, however, halves the number of switches. Table 3.3 Comparison of number of switches and voltage stresses in different topologies. Topology No. of switch Voltage stress FB converter 4 V in TL converter 4 V in / FB based ISOP converter 4n V in / n Proposed converter n V in / n

103 Chapter 4-93 CHAPTER 4 HIGH INPUT VOLTAGE THREE-LEVEL DC-DC CONVERTER WITH ASYMMETRIC VOLTAGE DISTRIBUTION ON SWITCH PAIRS 4.1. Introduction This chapter presents a power conversion concept with asymmetric distribution of the high input voltage among switch pairs in multi-level dc-dc converters. Instead of same voltage stress on the primary-side switches as those discussed in Chapter 3, it is intentionally control the voltage distribution among the switch pairs by applying different duty cycles for them. The advantages of the proposed asymmetric conversion concept are twofold. Firstly, it provides an additional degree of freedom to choose switching devices, allowing optimal selection of their voltage ratings and thus overall performance. The low-voltage switch pairs can be implemented with MOSFETs, and the high-voltage switch pairs with IGBTs. Secondly, it exhibits new properties which ensure ZVS of the MOSFET switch pairs started from very light load without additional circuitry for ensuring soft-switching. Based on the proposed concept, a TL converter with one IGBT switch pair and one MOSFET switch pair is proposed. Besides the ZVS of the two MOSFETs, an active snubber is introduced in the secondary-side to assist the ZCS of the two IGBTs. The ZCS snubber energy is completely released to the load, leading also to a duty-cycle gain. Therefore, the proposed soft-switching scheme is fundamentally different from ZVZCS and is named as hybrid ZVS-ZCS. A kw prototype, which performs the same function as the one discussed in Chapter 3 (i.e., conversion from 1500 V dc to 48 V dc), is built and evaluated to verify the theoretical analysis.

104 Chapter Converter with Asymmetric Voltage Distribution The circuit structure and the concept of the power conversion with asymmetric voltage distribution on the switch pairs are given as follows Circuit Structure (a) Circuit schematic. (b) Simplified control block diagram. Fig. 4.1 Proposed hybrid ZVS-ZCS dc-dc converter with secondary-side ZCS snubber and asymmetric voltage distribution on primary-side switch pairs.

105 Chapter 4-95 Fig. 4.1(a) presents the proposed converter with two switch pairs SP 1 and SP, which are composed of two IGBTs S 1, S, and two MOSFETs S 3, S 4 connected in series, respectively. The intermediate stage is a dc-blocking capacitor C b and high frequency isolation transformer. The turns-ratio of the transformer from primary-to-secondary is m and its leakage inductance is L lk. V C1, V C and V Cb are the voltages across the dc-link capacitors C 1, C and the capacitor C b, respectively. To improve the output current capacity, a current doubler rectifier [99] is applied in the secondary side, formed by two inductor-diode branches L f1 -D R1 and L f -D R. A snubber composed of switches S a1, S a, diode D a, capacitors C r1, C r and inductor L r is shown in Fig. 4.1 to fulfill ZCS of S 1 and S. S a1 is used to provide ZCS condition for S 1 while S a is used to provide ZCS condition for S. The function of S a1 and C r1 is to reduce i sec, and thus i p, from positive value to zero before S 1 turns off. And the function of S a, D a, L r and C r is to increase i sec from negative to zero before S turns off Conversion Concept with Asymmetric Voltage Distribution It will be shown in Section 4.4 that the voltages on input capacitors C 1 and C are inversely proportional to the duty cycles D 1 and D, implying that k V C 1 (4.1) V C D D 1 where k is defined as the voltage distribution factor, D 1 and D are the steady-state duty cycles of upper switches in each switch pair, S 1 and S 3. As shown in Table 1., the available solutions distribute the input voltage equally among the switch pairs (i.e., k = 1). Referring to (4.1), the concept proposed here allows asymmetric voltage stresses on each

106 Chapter 4-96 switch pair by adjusting the value of k. One of the implications is that it can provide an additional degree of freedom to select switching devices and allow for optimal combinations in terms of the operating frequency, switching loss, conduction loss and costeffectiveness Operation Principle of the Proposed Converter A simplified control block diagram illustrating the generation of the driving signals for S 1 -S 4 and S a1 -S a is presented in Fig. 4.1(b). The asymmetric duty cycles for S 1 and S 3 are obtained by using different control signals having a ratio of k for the PWM1 and PWM modules in the DSP controller. With designed parameters for the ZCS snubber, the conduction interval of S a1 and S a are constant. Therefore, the turn on and turn off instants of S a1 depends on the turn off time of S 1 (i.e., the control signal v con ). S a is turned off at the end of a switching cycle, implying a fixed turn on time instant. The voltages across C 1 and C are also sampled for overvoltage protection and fine tuning k if necessary for limiting the discrepancy between the actual voltage stress distribution and the desirable one. The operation consists of nine modes in one switching cycle. The timing diagram for a steady-state cycle is shown in Fig. 4.(a). Fig. 4.(b) and Fig. 4.(c) show the detailed operation of the two auxiliary snubber switches S a1 and S a, respectively. For sake of simplicity, the analysis is referred to the secondary of the transformer. The equivalent circuits in each operation mode are given in Fig The voltages across the input capacitors C 1, C, and dc-blocking capacitor C b are assumed constant in steady-state and the output inductors L f1 and L f are large enough to be considered as constant current sources. The parameters used in the following discussions are listed in Table 4.1.

107 Chapter 4-97 Table 4.1 Definitions and parameters used in the following analysis. D 1 D D 1 D duty cycle of switch S 1 as defined Fig. 4.(a) duty cycle of switch S 3 as defined in Fig. 4.(a) net effect on duty cycle D 1 due to ZVS duty cycle loss and ZCS duty cycle gain net effect on duty cycle D due to ZVS duty cycle loss and ZCS duty cycle gain t dl1 dead-time of gate signal from S to S 1 t dr1 dead-time of gate signal from S 1 to S t dl dead-time of gate signal from S 4 to S 3 t dr dead-time of gate signal from S 3 to S 4 T s switching period of the converter t i-j time duration from t i to t j (i.e., t i-j = t j - t i ) V L eq V C -V Cb ( Llk / m ) Lr Llk Lr /( Llk m Lr ) m L ( C C ) ω r1 lk r1 r L ( C C ) m Z r1 lk r1 r m L C ω r lk r1 L C m Z r lk r1 ω r3 1 LC lk S (C s3 = C s4 = C s ) Z r3 L lk C S ω r4 1 LrC r L C Z r4 r r ω r5 1 LeqC r L C Z r5 eq r

108 (a) General timing diagram during one cycle Chapter 4-98

109 Chapter 4-99 (b) Detailed timing diagram during t 3 to t 5 (c) Detailed timing diagram during t 10 to t 1 Fig. 4. Timing diagram of the proposed converter.

110 Chapter Mode 1 [t 0 -t 1 ] - Transition from freewheeling stage to energy transfer stage I [Fig. 4.3(a)] Before S 1 is turned on, the currents through diodes D R1 and D R keep constant and the body diode of S is conducting as shown in Fig. 4.3(a)-(i) and Fig. 4.3(a)-(ii). When S 1 is on, the current in D S is diverted to S 1 linearly due to the presence of parasitic inductance L S1 as shown in Fig. 4.3(a)-(iii). After D S stops conducting, the current i sec increases linearly due to voltage (V C1 +V C -V Cb ) /m applied on the leakage inductance L lk /m. Thus, the current in D R1 decreases and reaches zero at t 1, while that in D R increases to the load current. At t 1, current i sec increases to i Lf1 and D R1 is finally blocked. The duration of this mode is given by t 1 t 0 t 01 t dl1 L i S1 S V ( t C1 1 ) ( L S1 L lk )[ i m V Lf 1 C1 mi V S ( t 1 )] (4.) where i S (t 1 ) is the current flowing through D S at the instant t 1, i.e. at the end of steadystate cycle, as given by (4.33). The absolute value of i S (t 1 ) depends on the loading condition and increases with the reduction of the load. With practical design, at full load, i S (t 1 ) is approximately equal to zero while at no load i S (t 1 ) is -i Lf,nom / m, where i Lf,nom is the current flowing through L f under the nominal load. Moreover, the duration in which i S1 increases from zero to i Lf1 /m is very short, as compared to the switching period. To simplify the analysis, i S1 is assumed to increase linearly from zero to i Lf1 /m as shown in Fig. 4.(a) and the value of L S1 is negligible compared to L lk. Therefore, the duration of t 0-1 in (4.) is approximated by LlkiLf 1 LlkiLf 1 t1 t0 t0 1 tdl1 t (4.3) m V dl1 V V mv V C1 C Meanwhile, L r and C r are in a resonant mode until i Sa (current flowing through the body diode of S a ) reaches zero within t 0-1 as shown in Fig. 4.3(a)-(i) and Fig. 4.(c). Cb C1

111 Chapter (i) (ii)

112 Chapter 4-10 (iii) (iv) Fig. 4.3(a) Mode 1 (t 0 -t 1 ).

113 Chapter Mode [t 1 -t 4 ]-Energy transfer stage I [Fig. 4.3(b)-(d)] During this mode, the energy is transferred from the input to the load through the switches S 1 and S 4. This mode can be divided into three sub-stages: Sub-stage I [t 1 -t ] [Fig. 4.3(b)] - Charging of capacitors C r1 and C r. At t 1, the voltage across the secondary-side winding of the transformer becomes positive, thus, the diodes D Sa1 and D a conduct. Capacitors C r1 and C r are charged in a resonant manner with the leakage inductance L lk. The initial value of i sec is i Lf1. Therefore, i VC1 V t) ilf 1 sin r1( t t ) (4.4) mz sec ( 1 r1 v VC1 V t) vcr ( t) 1 cos r1( t ) (4.5) m C ( t r1 1 By referring i sec to the primary side, i ilf 1 VC1 V t) i p ( t) sin 1( t ) r (4.6) m m Z S1( t1 r1 After one-half resonant cycle, at t, the capacitor voltages v Cr1 and v Cr reach their maximum value (V C1 +V) / m and the current i sec returns to i Lf1. The diode D Sa1 and D a are blocked and the voltages of C r1 and C r are clamped at the maximum level. The time interval of this sub-stage is equal to half of the resonant cycle, that is t t 1 t 1 Llk ( Cr1 Cr ) m (4.7) Sub-stage II [t -t 3 ] [Fig. 4.3 (c)] - Energy transfer with constant i sec. During this sub-stage, all of the voltages and currents in the circuits are assumed constant. Sub-stage III [t 3 -t 4 ] [Fig. 4.3 (d)] - Commutation of S 1 with ZCS. At t 3, S a1 turns on

114 Chapter with ZCS due to the presence of leakage inductance L lk, which starts resonating with C r1 to make the current through S 1 drop to zero or become negative. The initial voltage of C r1 is v Cr1 (t 3 ) = (V C1 + V) / m as discussed above. Therefore, it can be obtained that i VC1 V t) ilf 1 sin r ( t t ) (4.8) mz sec ( 3 r v VC1 V t) 1 cos r ( t ) (4.9) m C ( t r1 3 i VC1 V t) sin r ( t ) (4.10) mz Sa1( t3 r It implies that i ilf 1 VC1 V t) i p ( t) sin ( t ) r (4.11) m m Z S1( t3 r When the current through S 1 drops to zero, and goes negative, D S1 conducts. S 1 is turned off at t 4 with ZCS when i S1 reaches its negative peak value as shown in Fig. 4.(b) (i S1 = i sec /m). Therefore, v VC1 V ( t4 (4.1) m C ) r1 LlkCr1 t4 t3 t3 4 (4.13) m

115 Chapter Fig. 4.3(b) Mode sub-stage I (t 1 -t ). Fig. 4.3(c) Mode sub-stage II (t -t 3 ).

116 Chapter (i) (ii) Fig. 4.3(d) Mode sub-stage III (t 3 -t 4 )

117 Chapter Mode 3 [t 4 -t 5 ]-Transition from energy transfer stage to freewheeling stage I [Fig. 4.3(e)] After S 1 is turned off at t 4, i sec increases to zero from negative values, and then the body diode of S 1, D S1, is blocked. Therefore, the primary transformer voltage drops as shown in Fig. 4.(a). As the diode D R1 is still in the blocking state, i Lf1 is fully supplied by the capacitor C r1 before S is turned on. After S is on, C r1 is further discharged until its voltage drops to zero as shown in Fig. 4.(b). The duration of this mode is approximately equal to t C ( V V ) r1 C1 5 t4 t4 5 (4.14) mil f 1 It should be noted that although S 1 is off during this period, the diode D R1 is still off and the resonant energy of C r1 is released to the load, contributing to a duty cycle gain. (i)

118 Chapter (ii) Fig. 4.3(e) Mode 3 (t 4 -t 5 ). Mode 4 [t 5 -t 6 ]-Freewheeling stage I [Fig. 4.3(f)] As v Cr1 reduces to zero at t 5, D R1 turns on naturally. i DR1 increases from zero to i Lf1 while i Sa1 reduces to zero quickly as shown in Fig. 4.(a) and Fig. 4.3(f)-(i). Therefore, S a1 can be turned off with ZCS after a short while since i Sa1 becomes zero. The diodes D R1 and D R are in freewheeling state. However, unlike that stage with symmetric operation between two switch pairs in TL converter [43], the current flowing through the transformer winding i sec increases linearly due to a difference of the voltages on C and C b. This phenomenon is owing to asymmetric operation of the two switch pairs, which will be investigated in Section 4.5 in detail. As shown in Fig. 4.3(f), i sec mv ( t t5 ) ( t) (4.15) L lk

119 Chapter This mode ends when t = T s / and S 4 is turned off with ZVS due to the presence of its parasitic capacitance C S4. The duration of this mode is t T (1 D ) s 1 6 t5 t5 6 tdr1 (4.16) Accordingly, the current i sec at t 6 is given by mv mv Ts i sec ( t6 ) ( t6 t5 ) (1 D1 ) tdr 1 L L (4.17) lk lk (i)

120 Chapter (ii) (iii) Fig. 4.3(f) Mode 4 (t 5 -t 6 ).

121 Chapter Mode 5[t 6 -t 7 ] - Transition from freewheeling stage to energy transfer stage II [Fig. 4.3(g)] After S 4 is turned off at t 6, the equivalent circuit is shown in Fig. 4.3(g). With initial conditions v CS3 (t 6 ) = V C and i p (t 6 ) = i sec (t 6 ) / m, v 1 ( t) VCb V cos r3 ( t t6 ) i p ( t6 ) Z r3 sin r3 ( t 6 ) (4.18) CS 3 t i V t) sin r3 ( t t6 ) i p ( t6 ) cosr3 ( t t ) (4.19) Z p ( 6 r3 The process described by (4.18)-(4.19) is the resonance occurred among L lk, C S3 and C S4. C S3 is fully discharged and C S4 is fully charged by the energy stored in the leakage inductance. D S3 will conduct when the voltage of C S3 reaches zero as shown in Fig. 4.3(g)- (ii). This transition takes place in a similar way as the corresponding process in symmetric FB or TL converters. However, the significant difference lies in that the energy that is provided by L lk is independent of loading condition, which can be observed from (4.17). It implies that S 3 can be turned on with ZVS from very light load to full load without any additional assisted strategies. S 3 is turned on with ZVS in a short while after D S3 conducts. The current in D R reaches zero at t 7 while the current of D R1 increases to the load current. At t 7, the primary-side current i p negatively increases to -i Lf /m. Therefore, the duration of this mode is given by LlkiLf t7 t6 t67 tdl (4.0) m V V C

122 Chapter 4-11 (i) (ii)

123 Chapter (iii) Fig. 4.3(g) Mode 5 (t 6 -t 7 ). Fig. 4.3(h) Mode 6 (t 7 -t 8 ).

124 Chapter Mode 6 [t 7 -t 8 ]-Energy transfer stage II [Fig. 4.3(h)] During this mode, D R1 is conducting and D R is blocked. Energy is transferred from C b to load through the switches of S and S 3. All of the voltages and currents in the circuits can be assumed constant. Mode 7 [t 8 -t 9 ]-Transition from energy transfer stage to freewheeling stage II [Fig. 4.3(i)] At t 8, S 3 is turned off with ZVS at the presence of C S3. i sec starts to charge C S3 and discharge C S4 with an approximately constant current i sec (t 8 )/ (i.e. -i Lf /). This mode ends when the voltage across C S4 reduces to zero. It implies that t mc V mc V s C s C 9 t8 t8 9 (4.1) isec ( t8 ) ilf Fig. 4.3(i) Mode 7 (t 8 -t 9 ).

125 Chapter Mode 8 [t 9 -t 11 ]-Freewheeling stage II [Fig. 4.3(j)-(k)] After v CS4 reaches zero, D S4 is conducting to clamp this voltage at zero. S 4 can be turned on with ZVS after t 9. Therefore, the duration of t dr should be long enough to ensure v CS4 reaches zero before S 4 turns on, that is t dr t 8-9. This mode can be divided into two sub-stages and their equivalent circuits are presented in Fig. 4.3(j)-(k). Sub-stage I [t 9 -t 10 ] [Fig. 4.3(j)]- Linear increase of i sec. During t 9 -t 11, diode D R1 and D R are conducting and the voltage between the nodes a and b as indicated in Fig. 4.3(j) is zero. The secondary-side winding current i sec increases slightly from negative values due to the voltage difference V. It gives that i sec mv ( t t9 ) ( t) ilf (4.) L lk Fig. 4.3(j) Mode 8 sub-stage I (t 9 -t 10 ).

126 Chapter Sub-stage II [t 10 -t 11 ] [Fig. 4.3(k)]- Resonance between L r and C r. C r starts to resonate with L r after S a turns on with ZCS at t 10 as shown in Fig. 4.(c). The equivalent circuit is presented in Fig. 4.3(k) with the initial value of v Cr (t 10 ) = (V C1 + V) / m, implying that v ( VC1 V ) t) cosr 4 ( t - ) (4.3) m Cr ( t10 i ( VC1 V ) t) sinr 4 ( t - ) (4.4) mz Sa ( t10 r 4 This mode ends when v Cr drops to zero at t 11, therefore, the duration of this sub-stage is t 11 L C r r t10 t10 11 (4.5) i Sa ( t 11 ) ( V V ) C1 (4.6) mz r 4 According to (4.), by neglecting the short period of t dr and t 11-1, one gets i sec ( t m(1 D ) VT s 11) ilf (4.7) Llk

127 Chapter Fig. 4.3(k) Mode 8 sub-stage II (t 10 -t 11 ). Mode 9 [t 11 -t 1 ]-Energy transfer stage induced by C r [Fig. 4.3(l)] During this mode, resonance occurs among the components L r, L lk and C r. At t 11, the snubber diode D a starts conducting, and C r begins to resonant with both L r and L lk. v Cr becomes negative and the diode D R is blocked. The output inductor current i Lf is supplied by both i sec and i Sa as shown in Fig. 4.3(l). By neglecting the effect of V during this resonant period, i v Cr ( Sa 11 sec 11 Lf r5 r5 t11 t) [ i ( t ) i ( t ) i ] Z sin ( t ) (4.8) Llk t) isa( t11) [ i ( t11) isec( t11) i ][1 cos 5( t )] Sa Lf r (4.9) m L L Sa( t11 r lk m Lr t) isec( t11) [ i ( t11) isec( t11) i ][1 cos 5( t t )] Sa Lf r (4.30) m L L sec( 11 r lk i It implies that the primary-side current flowing through S is given by

128 Chapter i isec( t) isec( t11) mlr t) [ i ( t11) isec( t11) i ][1 cos 5( t )] Sa Lf r (4.31) m m m L L S ( t11 r lk Within one-half of the resonant cycle, i sec increases from negative values to zero, and then to positive values. i Sa drops to zero and then goes to below zero as indicated in Fig. 4.(c). Therefore, S and S a can be turned off with ZCS after their currents become negative, respectively. It can be noted that during this period, the diode D R is blocked and the energy in C r is transferred to the load, contributing a duty cycle gain. The duration of this sub-stage is given by t t t L eq C (4.3) r According to (4.6)-(4.7) and (4.31)-(4.3), 1 D VT ml V V m1 D ilf s r C1 VTs is ( t1) (4.33) m Llk m Lr Llk mz r 4 Llk (i)

129 Chapter (ii) (iii) Fig. 4.3(l) Mode 9 (t 11 -t 1 ).

130 Chapter Steady-State Analysis Steady-State Voltage Stress on C b The voltage across the dc-blocking capacitor C b can be derived by calculating the voltage-second values in one steady-state cycle between the mid-points of the two switch pairs, that are, nodes A and B as indicated in Fig It can be obtained that s dl C s p C s s p C s C C C Cb T t V T t i C V T t i C V D V D V V V ) ( ) ( 1 (4.34) Detailed proof of (4.34) is given in the Appendix A.1. In practical design, the third term is negligible compared to other ones because of a very small value of C s and small difference between i p (t 6 ) and -i p (t 8 ). Therefore, V Cb is approximately equal to s dl C C C C Cb T t V D V D V V V (4.35) According to (4.35), C C s dl C Cb C V D D V T t V V V V (4.36) Voltage Conversion Ratio The voltage-second balances written on the inductors L f1 and L f give D D m V V V C o (4.37) 1 D D m V V V C o (4.38)

131 Chapter 4-11 where C V V LC V Li mi T mt V mt V V r1 C1 lk r1 lk Lf 1 D1 Lf 1 s s C1 s C1 t mc sv Leq VC V Llk ilf m L C dl eq D V D ilf Ts L T r Cr VC V Ts s m VC V Ts Llk VC V (4.39) (4.40) Detailed proof of (4.37)-(4.40) is given in Appendix A. and A.3. It should be noted that the above equations for ΔD 1 are for heavy loading condition when the secondary winding current i sec can be assumed to be zero during t 01 and t 45. Under light load, with the consideration of i sec, the first term (i.e., t 45 /(T s )) of ΔD 1 is approximately presented by C V V r1 C1 Lf1 sec mi i T s, where i sec is the average current of i sec during t 45. The fourth term of ΔD 1 is zero due to that i sec itself is sufficient to supply the load current, implying that there is no duty cycle loss during the turn on transition of S 1. According to (4.37)-(4.38), the conversion ratio is given by M V 1 m D D D D D o 1 1 (4.41) V in 1 D D 1 D Practically, the net effect values of D 1 and D are negligible compared to D 1 and D. Therefore, Eq. (4.41) can be simplified into M V V 1 m D D D D o 1 (4.4) in 1 By substituting (4.1) into (4.4), the conversion ratio can be represented by 1 k M D1 m 1 k (4.43)

132 Chapter Voltage Distribution across Switch Pairs According to (4.37) and (4.38), k V C V D D V D1 D1 D D D D V D D D D C1 in (4.44) V V in by By neglecting V, D 1 and D, the steady-state voltage distribution factor is given k V C1 (4.45) V C D D 1 Therefore, the voltage across the switches in each switch pair can be adjusted by varying D 1, D, and thus k, allowing for the choice of the optimal combination of switching devices. It should be noted that the input to output voltage ratio is not necessary to be constant. The duty cycles of D 1 and D will be updated accordingly with the required voltage conversion ratio. During the startup, the voltage distribution can be assured by selecting the ratio between the capacitance values of C 1 and C. The capacitors C 1 and C are charged up instantaneously at the beginning to the initial values defined as V C1 (0) and V C (0), which are assumed to be inversely proportional to their capacitance values. It gives that V V C1 (4.46) C (0) (0) C C 1 The DSP controller provides a soft-start function that makes the effective duty cycle increase slowly, and controls the two capacitor voltages (i.e., V C1 and V C ) in the designed ratio.

133 Chapter Design Guidelines The design guidelines for the proposed converter are illustrated by an experimental prototype. The specifications are tabulated in Table 4.. The discussions here focus on the determination of the turns-ratio of the transformer, leakage inductance (or external inductance if necessary) L lk, the voltages difference V, and the snubber passive components C r1, C r and L r. For selection of other components selection, the design guidelines are similar with conventional cases (e.g., the converter discussed in Chapter 3) and will not be presented here. Table 4. Design specifications of the experimental prototype. Specifications Value Nominal input voltage (V in ) 1500 V Minimum input voltage (V in,min ) 1350 V Maximum input voltage (V in,max ) 1650 V Nominal output power (P o ) kw Nominal voltage distribution factor ( k nom ) Output voltage ripple <1 % Nominal output voltage (V o ) 48 V Output current ripple <10 % Switching frequency ( f s ) 50 khz Design Issues 1) Issues on the turns-ratio of the isolation transformer and duty cycle ranges According to (4.43), (4.45) and the specifications listed in Table 4., the duty cycle ranges with respect to different turns-ratio of the isolation transformer are shown in Table 4.3. To allow the proper operation, the values of D 1 and D should be within [0, 0.5] and

134 Chapter 4-14 [0, 1], respectively. m = 4 is selected to retain reasonable margins of the D 1 and D. Moreover, compared to the cases when m is less than 4 (e.g., m =, m = 3), it will reduce the primary-side currents to achieve lower conduction losses of the switching devices. Table 4.3 Ranges of duty cycles with respect to m. m D 1,min D 1,nom D 1,max D,min D,nom D,max * *An invalid state. ) Issues on the soft-switching conditions (a) ZCS condition of S 1 According to (4.11), to ensure that i S1 drops to zero before t 4, C r1 LlkiLf 1 (4.47) V V C1,min where V C1,min is the minimum voltage stress on C 1. (b) ZCS condition of S a1 After S 1 turns off at t 4, the energy stored in C r1 is released to load until the current in C r1 decays to zero, therefore, i Sa1 becomes zero and then S a1 can be turned off with ZCS without special constraints on the snubber parameters.

135 Chapter 4-15 (c) ZCS condition of S and S a According to (4.6)-(4.7), (4.9) and (4.31), to ensure that i S and i Sa drop to zero before t 1, the capacitance value of C r should fulfill the inequalities C L r 1 D,min VT s Llk m Lr VC 1,min V 4 r (4.48) L L m r lk (4.49) (d) ZVS condition of S 3 As discussed in Section 4.3, the voltage difference V is used to charge the leakage inductance L lk of the transformer during the freewheeling stage t 5-6 and then the energy stored in L lk provides the ZVS condition for turning on S 3 within the interval [t 6, t 7 ]. According to (4.18), the following condition should be adopted to ensure that the voltage across C S3 drops to zero before S 3 turns on. V V C,max lk s L C 1D T t 1max, s dr1 (4.50) where V C,max is the maximum voltage stress on C. According to (4.50), provided that there is a slight difference in the voltages between V C and V Cb, S 3 will be in ZVS. Practically, the variations of the midpoint voltage between C 1 and C only affect the duration of the switching transition of S 3. (e) ZVS condition of S 4 It is practically easy for S 4 to achieve ZVS as the converter is still operating in energy transfer stage before S 4 is turned on.

136 Chapter 4-16 The secondary-side active snubber provides ZCS condition for the IGBTs. Without it, all IGBTs could be switched with ZVS, but not a favorable operation. Moreover, S 3 might also be hard-switched at turn on. 3) Issues on the current limits of switching devices (a) Current limit of S 1 The maximum current stress of S 1, i S1,max, occurs within t 1-. It should not exceed the pre-selected maximum current rating of the switching device S 1, defined as I S1,max. According to (4.6), it is given by i S1,max i V V Lf 1 C1,max m m L ( C C ) lk r1 r I S1,max (4.51) (b) Current limit of the primary-side winding during the freewheeling stage t 5-6 During the freewheeling stage t 5-6, the current in the primary-side winding flows through S and S 4 and its magnitude should be less than the pre-selected maximum current ratings of these devices. According to (4.17), the condition is given by V T 1D VT i t D t I I s 1,min s p( 6) max 1 1,min dr1 min S,max, S4,max L lk Llk (4.5) where I S,max and I S4,max are the pre-selected maximum current ratings of S and S 4, respectively. (c) Current limit of S a The maximum current flowing in S a occurs at t 11 and from (4.6), one gets

137 Chapter 4-17 i Sa,max r r V C 1,max V I (4.53) Sa,max m L C where I Sa,max is the pre-selected maximum current rating of S a and V C1,max is the maximum voltage stress on C 1. 4) Issues on the conduction time of S a1 and S a and resonant time of t 1- The conduction time of S a1 is t 3-5 and that of S a is t To ensure proper operation of the switching devices, the minimum conduction durations should be larger than reasonable values (e.g., larger than five times of the total turn on/off time of S a1 and S a, respectively). Therefore, according to (4.13)-(4.14), (4.5) and (4.3), the conditions are given by L lk m C r1 C r1 ( V C1,min mi L f 1 V ) 5 t r1 t f 1 (4.54) L C r r L eq C r 5 t r t f (4.55) where t r1 and t f1 are the turn on and turn off time of S a1, respectively. t r and t f are the turn on and turn off time of S a, respectively. The time duration of t 1- is given by (4.7), which will affect the conduction loss of S 1. The longer t 1- is, the larger conduction losses are induced. Therefore, t 1- is designed to be less than 5% of the conduction time of S 1. It gives that L lk ( C ) 5% D T r1 r s 1,min m C (4.56)

138 Chapter Boundaries of the Design Parameters 1) Boundaries of L lk and L r According to (4.53), C Sa,max r r 4 mi V C1,max L V (4.57) According to the definition of L eq in Table 4.1 and (4.49), L L L (4.58) r eq r By substituting the maximum values of C r and L eq represented by (4.57) and (4.58), respectively, into (4.55), one gets L r 0 V V t t 0 t t V C1,max r f r f C1,max (4.59) 3mI 3mI Sa,max Sa,max According to (4.47), lk Lf 1 r1 r min r1,min C C C V Li C1,min V (4.60) By substituting the minimum value of C r1 + C r represented by (4.60) into (4.56), L lk mvc1,min V D1,min Ts mvc1,min D1,min Ts (4.61) 8i 8i Lf 1 Lf 1 Therefore, according to (4.49), (4.59) and (4.61), the boundaries of L r and L lk are given by 0mt t V mv D T (4.6) 3 8 r f C1,max C1,min 1,min s Llk ISa,max ilf 1 0 t t V L (4.63) 3 r f C1,max lk Lr misa,max m

139 Chapter 4-19 ) Boundary of V According to (4.5), V L min I, I 1 D T lk S,max S 4,max 1,min s (4.64) By considering (4.50) and (4.64) together, V min, C,max LlkC L I I s V 1D T t 1D T lk S,max S 4,max 1,max s dr1 1,min s (4.65) 3) Boundary of C r According to (4.48) and (4.57), L r 1 D,min VT s misa,maxlr Cr L 1,min 4 lk m Lr VC V VC 1,max V 4 (4.66) 4) Boundary of C r1 According to (4.51), C V L mi i lk S1,max Lf 1 r1 C r C1,max V (4.67) Taking into account (4.47), lk Lf 1 lk S1,max Lf 1 lk S1,max Lf 1 C r1 C r Li L mi i L mi i V V V V V V C1,min C1,max C1,max (4.68)

140 Chapter Optimal Design 1) Minimization of the circulating current during freewheeling stage t 5-6 According to (4.5), the circulating current in the freewheeling stage t 5-6 will jump up with the increase of ΔV under specific L lk. Moreover, by referring to (4.53) and (4.66), it can be observed that small value of ΔV is beneficial to reduce the lower boundary of C r, therefore, allowing reduction of the current stress of S a. ΔV is designed with its minimum value represented by (4.65). Therefore, V V min V C,max lk s L C 1D T t 1,max s dr1 (4.69) According to (4.36) and (4.45), V C1 dl1 V (4.70) T t s It reveals that the desired value of V presented by (4.69) can be achieved by selecting a proper dead-time t dl1 and is irrelevant with loading condition. ) Trade-off between ΔD 1 and the current stress of S 1 Based on (4.39) and (4.51), Fig. 4.4 graphically presents the values of ΔD 1 and current stress of S 1 with different L lk and C r1. Each pair of values of L lk and C r1 within the boundaries presented by (4.6) and (4.68) are reiterated by (4.54) and (4.56) and only the ones meet the conditions are shown in Fig It should be noted that the value of C r is neglected for the sake of simplification during the checking process. Moreover, the values of the current stress shown in Fig. 4.4(b) are approximated ones with C r = 0. This approximation will not affect the design of L lk and C r1 as C r is much smaller than C r1 and

141 Chapter the selection of C r is independent of C r1 as shown later. It can be observed that large values of L lk and C r1 are beneficial to achieve the duty cycle gain and increase its value. However, high value of C r1 will induce large current stress of S 1, leading to increasing conduction losses. (a) ΔD 1 versus L lk and C r1

142 Chapter 4-13 (b) Approximated current stress of S 1 versus L lk and C r1 Fig. 4.4 Graphically trade-off conditions for designing of L lk and C r1 (m = 4, V C1,min = 900 V, V C1 = 1000 V, V C1,max = 1100 V, i Lf1 = 7.8 A, I S1,max = 0 A, T s = 0 µs). 3) Trade-off between ΔD and the current stress of S According to (4.40) and (4.53), Fig. 4.5 plots the surfaces of ΔD and the current stress of S a with varying values of L r and C r. Each pair of values of L r and C r within the boundaries presented by (4.63) and (4.66) should meet the condition in (4.55). It can be noted that higher value of L r is beneficial to increase the value of ΔD and reduce the current stress of S a. Large value of C r is also preferable to obtain more duty cycle gain, however, will induce high current stress on S a.

143 Chapter (a) ΔD versus L r and C r (b) Current stress of S a versus L r and C r Fig. 4.5 Graphically trade-off conditions for designing of L r and C r (m = 4, V C1,min = 900 V, V C1 = 1000 V, V C1,max = 1100 V, L lk = 36 µh, i Lf = 13.9 A, I Sa,max = 48 A, T s =0 µs, t dl = 0.78 µs).

144 Chapter Prototype and Experimental Verifications A 1500 V to 48 V kw prototype is built to verify the proposed dc-dc conversion concept. The specifications are as shown in Table 4.. The design flow chart of ΔV, L lk, L r, C r1 and C r based on the design guideline in Section 4.5 is presented in Fig According to Table 4.3, the turns ratio of the isolation transformer is selected as m = 4 and the duty cycle D 1, D are within [0.349, 0.47] and [0.698, 0.854], respectively. Fig. 4.4 and Fig. 4.5 are plotted with the pre-selected switching devices which have the following parameters: I S1,max = 0 A, I Sa,max = 48 A, t r1 = t r = ns and t f1 = t f = 9 ns. To compromise ΔD 1 and current stress of S 1, maximum allowable L lk is chosen and minimum value of C r1 is selected. With the design specifications, L lk = 36 µh and C r1 = 34 nf. L r is selected with the allowable maximum value and trade-off considerations should be made for the selection of C r. According to (4.66) and Fig. 4.5, L r is limited within 1.93 µh. Therefore, L r is selected with 1.6 µh to maintain a reasonable difference from that of L lk /m and to retain margin for tolerance considerations of practical inductors. C r is chosen to be 10 nf. Accordingly, the selected component parameters of the converter are presented in Table 4.4. L lk is designed to be 36 H. It is realized by connecting an external inductor with inductance of 5 H in series with the 11 H leakage inductance of the transformer. Film capacitors instead of electrolytic capacitors are used for the dc-link due to their high voltage blocking capability. The dc-blocking capacitor C b is also implemented by film capacitor with low equivalent series resistance (ESR) to sustain high current and reduce its power losses. Fig. 4.7 shows the photo of the prototype (without showing the DSP control board).

145 Fig. 4.6 Design flow chart for ΔV, L lk, L r, C r1 and C r. Chapter 4-135

146 Chapter Table 4.4 Component selections of the prototype. Items Component Selections Turns ratio m 4:1 Transformer Magnetizing inductance 9.5 mh Transformer leakage inductance 11 H Inductance L lk 36 H Transformer leakage inductance 11 H Externally added inductor 5 H dc-link capacitors C V/30 µf (pc film cap.) dc-link capacitors C 800V/60 µf (pc film cap.) dc-blocking capacitor C b 600 V/10 µf /ESR 5.3 mω (film cap.) Output capacitor C o 100 V/00 µf / ESR 90 mω (electrolytic cap.) Output inductors, L f1 and L f 10 H Primary-side IGBT S 1 and S IHW0N10R3 (100 V/0 A) Snubber IGBT S a1 and S a IRGS406DPBF (600 V/4 A) MOSFETs S 3 and S 4 SPW0N60C3 (650 V/0.7 A) Rectifier diode D 1 and D FFH30S60S (600 V/30 A) Snubber diode D a STTH10LCD06SB (600 V/10 A) Snubber capacitor C r1 34 nf (film cap.) Snubber capacitor C r 10 nf (film cap.) Snubber inductor L r 1.6 H

147 Chapter Fig. 4.7 Photo of the kw 1500 V-to-48 V prototype. Fig. 4.8 describes the driving signals for the primary-side switches. It can be observed that different duty cycles are applied to the two switch pairs to achieve the asymmetric voltage distribution on them. The gate signals for S 1 and S 3 have a phase difference of around 180. Fig. 4.9 presents the switching waveforms of the proposed converter under full load and 10% loads. It can be observed that the IGBT switches S 1 and S are turned on/off with ZCS and the MOSFET switches S 3 and S 4 are switched by ZVS. Soft-switching can be achieved from very light load to nominal load. Moreover, the voltage stresses on S 3 and S 4 are around 500 V as shown in Fig. 4.9(b), implying that it achieves an asymmetric voltage distribution with k =, which is in well agreement with the theoretical predictions. The ZCS waveforms for the auxiliary switches S a1 and S a are presented in Fig. 4.9(e).

148 Chapter Fig. 4.8 Asymmetric driving signals for the two switch pairs. (a) ZCS turn on/off of S 1 and S under full load.

149 Chapter (b) ZVS turn on/off of S 3 and S 4 under full load. (c) ZCS turn on/off of S 1 and S under 10% load.

150 Chapter (d) ZVS turn on/off of S 3 and S 4 under 10% load. (e) ZCS turn on/off of Sa 1 and Sa under full load. Fig. 4.9 Switching waveforms of S 1 -S 4 and S a1 -S a.

151 Chapter Fig shows the voltage waveforms across the input capacitors C 1 and C at start up. The voltage distribution ratio is found to be 1.998, which is in consistent with (4.45) and (4.46). Fig shows the relationship of open loop voltage and output current with fixed duty cycle and input voltage. The output voltage increases with the reduction of load current due to increased effective duty cycles. As the practical voltage drops on diodes, active switches and parasitic resistors have not been considered in the theoretical calculations, the calculated output voltages are observed to have some discrepancies with the simulation and experimental ones. Fig. 4.1 presents the measured efficiencies of the prototype. It reveals that the proposed converter exhibits high efficiency within wide load ranges. The efficiency under nominal load is 9.4%. The power losses in main components are analyzed in Fig The key loss is on the rectifier diodes. With the aid of soft-switching, the power dissipated on the two switch pairs is only 0.7% of the input power. The efficiency without the ZCS snubber is also presented in Fig. 4.1, indicating an efficiency reduction of 1.7% under nominal load mainly due to the turn off losses of IGBTs S 1 and S. The efficiencies with open loop voltage varying from 48 V to 5.1 V (corresponding to Fig. 4.11) under different loading condition are shown in Fig The power losses are mainly composed of two parts. The first part is almost constant, such as the core losses of isolation transformer and output inductors, power supplies for gate drivers and control circuits, and part of the power losses in the ZCS snubber. The second part is increased with the output power. The efficiency drops at light load due to that the first part power losses will become dominant.

152 Chapter 4-14 Fig Voltage across C 1 and C during start-up. Output Voltage V o (V) Output Current (A) simulated calculated measured Fig Open loop voltage and current characteristics with fixed duty cycles and input voltage.

153 Chapter Efficiency (%) With ZCS Snubber 77 Without ZCS Snubber Open loop with constant duty cycle Output power (W) Fig. 4.1 Measured efficiencies under different loading condition. Fig Power losses in main components under nominal load.

154 Chapter Compared to the prototype in Chapter 3 with same specifications, the proposed one achieves 16.% volume reduction and 1.6% and 8.% efficiency improvement under full load and 50% load, respectively Chapter Summary A novel concept of dc-dc conversion with asymmetric voltage distribution across switch pairs is proposed and applied for a particular kind of high input voltage application. It allows using optimal choices of switching devices to achieve high frequency and high efficiency operations. A hybrid ZVS-ZCS soft-switching technique is developed to make the switching losses of MOSFETs and IGBTs negligible. The asymmetric operations of the MOSFET switch pair and IGBT switch pair induce a voltage difference between dc-link capacitor C and dc-blocking capacitor C b. This voltage difference is independent of loading condition and is the energy source for achieving ZVS of the lagging switch in the MOSFET switch pair. The proposed snubber for ZCS of the IGBT switch pair completely releases the snubber energy to the load, resulting in a duty cycle gain. The two switch pairs can be soft-switched from very light load to full load with minimum circulating energy. The control stage is implemented with a single digital controller without additional hardware circuitry as compared to its counterpart in FB or TL converters. The switches of the snubber commutate with ZCS. The concept is verified by a 1500/48 V kw prototype. Experimental results are in good agreement with the theoretical analysis. A voltage distribution factor of is achieved and the measured efficiency at nominal load is 9.4%.

155 Chapter CHAPTER 5 AUNIFORM FAST TRANSIENT CONTROLLER FOR DC-DC CONVERTERS 5. 1 Introduction The output of the high input voltage converters discussed in Chapter 3 and Chapter 4 are usually used to supply energy for various kinds of low-voltage converters. The performance of the dynamic response of those low-voltage converters is critical as they are momentary loads in the metro train applications. This chapter presents a uniform fast transient controller for those low-voltage converters based on the second-order switching surface control method developed in [117]. Much effort has been made to the switching surface control of buck converter. However, it remains a fundamental challenge to apply the same concept and associated control technique to converters with non-minimum-phase characteristics. A nonlinear control method for all basic dc-dc converters (i.e. buck converter, boost converter, buckboost converter, uk converter and SEPIC) is proposed by deriving a uniform switching surface. It retains the advantages of boundary control for buck converter with secondorder switching surface. For example, the converters can reach steady-state in two switching actions after being subjected to large-signal disturbances. The derivations are general-oriented and can determine the circuit variables needed in the switching function. The same controller is universally applicable to different converters operating in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). A 190 W 48/48 V (i.e., unregulated input voltage with nominal value of 48 V to a regulated output voltage of 48 V with different polarity) buck-boost converter prototype has been built and evaluated to confirm the theoretical predictions.

156 Chapter Uniform Second-Order Switching Surface Derivation of Uniform Second-Order Switching Surface Fig. 5.1 shows the basic dc-dc converters. The first three ones, as presented in Fig. 5.1(a)-(c), are composed of one capacitor and one inductor. The last two, Ćuk converter and single-ended primary-inductor converter (SEPIC), include two inductors and two capacitors. Fig. 5. plots the theoretical waveforms of their inductor currents and capacitor voltages. Generally, there are two types of distinctive curves to present the relationship between inductor currents and capacitor voltages as shown in Fig. 5.(a) and Fig. 5.(b). It can be noted from Fig. 5.(b) that the capacitor voltages are monotonically decrease with the corresponding inductor currents for converters with non-minimum phase characteristics, imposing the challenge to apply switching surface control to those converters. (a) Buck converter. (b) Boost converter.

157 Chapter (c) Buck-boost converter. (d) Ćuk converter. (e) Single-ended primary-inductor converter (SEPIC). Fig. 5.1 Basic dc-dc converters.

158 Chapter Fig. 5. Theoretical relationships between inductor current and capacitor voltage: (a) i L -v C in buck converter and i L -v C in uk converter; (b) i L -v C in boost and buckboost converter, i L1 -v C1 in uk converter and i L1 -v C1, i L -v C in SEPIC. To handle the above fundamental issue in switching surface control and incorporate the advantages of the boundary control with second-order switching surface which has been applied on buck converter [117], a uniform second-order switching surface is proposed. It extends the control state variables (i.e. inductor currents and capacitor voltages) in previously proposed switching surface controllers to arbitrary direct or indirect control variables, namely x and y. Consequently, the relationships between x and y in all basic dcdc converters are exactly the same as that of i L -v C in buck converter shown in Fig. 5.(a). Therefore, the switching surfaces of different kind of converters can be easily defined on a Cartesian x-y plane. x and y have the same properties as those of inductor current and capacitor voltage respectively in buck converter, implying that dy dx k ( x x ) (5.1) s ref where k s is state trajectory parameter related with the slope of x and x ref is the reference value.

159 Chapter Fig. 5.3 Principle of boundary control with uniform second order switching surface: (a) control variables, (b) control law. With the aid of Fig. 5.3, according to (5.1), the approximated on-state trajectory Traj on and off-state CCM trajectory Traj can be expressed respectively as follows off Traj on yt ( ) yt ( 0) k s1 xt ( ) x ref xt ( 0) x ref 0 (5.) Traj off yt () yt ( ) k s xt () x ref xt ( ) x ref 0 (5.3) where t 0 and t are the turn on/off instants, respectively, k s1 is the trajectory parameter during on-state period and k s is that during off-state CCM period. k s1 > 0 and k s < 0. In DCM, after the x reaches zero, the trajectory moves along the y-axis, x = 0 and the corresponding trajectory parameter k s3 = 0 during this interval. Fig. 5.4 presents typical switching surface, load line and ideal on/off statetrajectories of basic dc-dc converters on x-y plane. The trajectories are plotted by firstly

160 Chapter solving on- and off-state space equations of specific converter with different initial conditions and then mapping the state variables i L and v C to x and y, respectively. It is the ideal state trajectories which can be approximated by (5.) and (5.3). Fig. 5.4 Typical trajectories, load line and switching surface of basic dc-dc converters on the x-y plane. As discussed in [117], the ideal second-order switching surface should pass through the target operating point (y ref, x ref ), and exactly along the approximated on-state trajectory when x is below the load line, and the off-state trajectory when x is above the load line. By transforming the i L -v C state plane to the Cartesian x-y plane, a well-defined uniform second-order switching surface can be obtained as shown in Fig It approximately follows the ideal on-state trajectory and off-state trajectory when the state is below and above the load line, respectively, implying a high velocity to revert to the target

161 Chapter operating point from arbitrary operating points. The switching instants are determined by predicting the operating point at t 1 and t 3 as shown in Fig By putting y(t) = y ref, x(t) = x ref, y(t 0 ) = y, and y(t ) = y into (5.) and (5.3), respectively, a general form of the switching surface is given by ( y y ) k( x x ) (5.4) ref ref where σ is the uniform second-order switching surface, k is the control parameter and can be expressed as follows for an ideal second-order switching surface 1 sgn ( x xref ) 1 sgn ( x xref ) k k s1 ks (5.5) k can be of other values, which affect the stability and trajectory velocity along the switching surface as discussed in Section 5.3. In the following analysis, k 1 and k are defined as general control parameters for turn-on and turn-off switching actions, respectively. Practically, in order to avoid chattering phenomenon, a modified switching surface is derived by adding a hysteresis band y as shown in Fig. 5.4 into (5.4), resulting in y yref k1 ( x xref ) y ( x xref ) = (5.6) y yref k ( x xref ) y ( x xref ) where and are the uniform second-order switching surface below and above load line. Therefore, the uniform control law for the basic dc-dc converters is formulated as follows. The switch S is turned on if

162 Chapter 5-15 y( t) k1 ( x x ) ( y y) 0 and x( t) x (5.7a) ref ref ref S is turned off if y( t) k ( x x ) ( y y) 0 and x( t) x (5.7b) ref ref ref Table 5.1 Load line and control variables of the proposed uniform control law. Converter type Load line x y Buck Boost Buck-boost i i v R o L i L v o vi oo L i v L in vi oo L io i v L in i 1 1 Li Cv L o 1 1 Li Cv Cv v vo Ćuk il i L v o R L o in o vi oo 1 SEPIC il 1iL io i v L1 +i L L ( i 1i ) Cv Cv v in L L o in o Table 5. Control parameters of the proposed uniform control law. Converter type Buck Boost Buck-boost Ćuk SEPIC k S1 (on-state) k S (off-state CCM) k S (off-state DCM) L L 0 Cv ( in vo ) Cvo L L L C ( v v ) C1 L o Lvin ( v v ) in o Lvin 0 v L o 0 Cv o Lvin 0 v o 0

163 Chapter Table 5.1 and Table 5. tabulate the transformed variables x, y and their associated load line and control parameters k s1 and k s for ideal second-order switching surfaces. An example demonstrating the derivation procedures of x, y, and k for a buck-boost converter will be given in Section 5.3. It should be noted that the derivations for uk converter and SEPIC are based on reduced-order models discussed in [108]-[110]. In uk converter, the output inductor current i L and output capacitor voltage v C are selected as the state variables. In SEPIC, the inductor currents i L1, i L and output capacitor voltage v C are chosen as the state variables. The results for SEPIC presented in Table 5.1 and Table 5. are based on assumptions that the voltage across the dc-blocking capacitor C 1 is equal to v in, and the converter is designed with L 1 = L = L. Simulations have been done on boost converter, buck-boost converter, uk converter and SEPIC to verify the analysis shown Table 5.1 and Table 5.. Load changes from CCM to CCM, from CCM to DCM and from DCM to CCM are simulated. The results presented in Fig. 5.5 reveal that the single controller (with different control parameters) can control the four converters operating in both CCM and DCM. The converters can revert to steady-state by two switch actions after being exposed to large disturbances. It can also be noted from Fig. 5.5(e)-(f) that x and y exhibit similar properties during steady-state and transient periods as those of i L and v C in buck converter discussed in [117].

164 Chapter (a) Boost converter with load change from 1 Ω to 50 Ω (CCM to CCM) (v in = 4 V, v o,ref = 48 V, L = 0. mh, C = 110 uf). (b) Buck-boost converter with load change from 1 Ω to 00 Ω (CCM to DCM) (v in = 48 V, v o,ref = 48 V, L = 0.1 mh, C = 150 uf).

165 Chapter (c) Ćuk converter with load change from 50 Ω to 1 Ω (CCM to CCM) (v in = 48 V, v o,ref = 48 V, L 1 =1 mh, L = 0.45 mh, C 1 = 0 uf, C = 110 uf). (d) SEPIC converter with load change from 00 Ω to 1 Ω (DCM to CCM) (v in = 48 V, v o,ref = 48 V, L 1 = L = 0.3 mh, C 1 = 4.7 uf, C = 0 uf).

166 Chapter (e) SEPIC converter with load change from 50 Ω to 1 Ω (x-y waveforms) (v in = 48 V, v o,ref = 48 V, L 1 = L = 0.3 mh, C 1 = 4.7 uf, C = 0 uf). (f) SEPIC converter with load change from 1 Ω to 50 Ω (x-y waveforms) (v in = 48 V, v o,ref = 48 V, L 1 = L = 0.3 mh, C 1 = 4.7 uf, C = 0 uf). Fig. 5.5 Simulation results of basic dc-dc converters with the proposed uniform controller.

167 Chapter Stability Analysis By varying the control parameters of k 1 and k, the points along 0 can be divided based on the directions of on/off trajectories at the switching surface [106]. There are three possible modes of the points: rejective mode, reflective mode and refractive mode. In rejective mode, the trajectories on both sides of the switching surface depart away from the switching surface, which will lead to unstable operation of the converter. In reflective mode, the sate trajectories direct toward the switching surface on both side and will move along the surface to the target operating point. In refractive mode, trajectories reach to the switching surface on one side and away from the other side. The state will move around the target operating point. Thus, based on the analysis in [106], the conditions leading to rejective mode are given by onstate off state 0 0 or or onstate off state 0, 0, onstate off state 0 0 (5.8) and the ones for ensuring reflective operation are given by onstate off state 0 0 or or onstate off state 0, 0, onstate off state 0 0 (5.9) where on-state and off-state indicate the corresponding value when the initial state is on- state and off-state, respectively. For example, onstate is the rate change of (i.e. ) when the initial state is on and off state is the rate change of (i.e. ) if the initial state is off. According to (5.), (5.3) and (5.6), if the initial state is on, ) (5.10a) onstate k s1 k )( x xref

168 Chapter ) (5.10b) - onstate ( ks 1 k1)( x xref d dx onstate ( k s1 k )( x xref ) ( x xref ) (5.10c) dt dt onstate on If the initial state is off, ) (5.11a) off state ( k s k )( x xref ) (5.11b) off state ( k s k1)( x xref d dx off state ( k s k1)( x xref ) ( x xref ) (5.11c) dt dt off state off where dx dt 0, dx dt 0 are the slopes of x during on- and off-state, respectively. on off By substituting (5.10) and (5.11) into (5.8) and (5.9), the regions of the control parameters for rejective mode and reflective mode are given by (5.1) and (5.13), respectively. k k k k (5.1) 1 s and s1 k k k k (5.13) 1 s1 and s The conditions for refractive mode are within the ones outside the conditions of (5.1) and (5.13). However, global stability can only be assured if each successive intersection with the switching surface brings the operation closer to the target operating point as illustrated in Fig A (x n, y n ), B (x n+1, y n+1 ) and C (x n+, y n+ ) are three subsequent intersections between the state trajectories and the switching surface, called successor points. The condition for stable operation is given by

169 Chapter S (5.14) n S n where S n is the distance between A and the target point O (x ref, y ref ), S n ( xn xref ) ( yn yref ) and S n+ is the distance between C and O, S n xn xref ) ( yn yref ) (. Fig. 5.6 Illustration of the movement of successor in refractive mode. By neglecting the hysteresis band y, for a generic successor point on 0, y n yref k( xn xref ) (5.15) Therefore the condition given in (5.14) can be rewritten as ( xn xref ) ( xn xref ) (5.16)

170 Chapter As shown in Fig. 5.6, the successor points A and C are on and B is on. Both of A and B are on the off-state trajectory while B and C are on the on-state trajectory. According to (5.)-(5.3), (5.6) and (5.15), it can be derived that - ks k ks k ( x x ) ( x x ) 1 1 n ref n ref ks 1 k ks k1 (5.17) In order to satisfy (5.16), it results in k1 k (5.18) Fig. 5.7 Stability analysis of the proposed uniform second-order switching surface with different control parameters k 1 and k. Fig. 5.7 summarizes the aforementioned analysis and presents k 1 and k regions for different operation modes. It can be observed that when k 1 = k s1 and k = k s, the switching

171 Chapter surface is along the boundary of the reflective and refractive regions. Fig. 5.8 shows five typical switching surfaces with specific values of k 1 and k. A and B are points on the right and left sides of switching surfaces of, and 3, and A and C locate on the two sides of switching surfaces 4 and 5. 1 n (n = 1,, 3, 4, 5) and n indicate turn off/on part of one specific switching surface above and below the load line, respectively. It can be noted that the curved switching surfaces, 3, and 5 will make arbitrary point operate in reflective, stable refractive, unstable refractive and rejective mode, respectively. When is selected, which approximately follows the on/off state trajectory, the arbitrary point A or B will reach the target operating point by two switching actions. 1 4 Fig. 5.8 Illustration of rejective, refractive and reflective operation modes.

172 Chapter Derivation and Implementation (for Buck-Boost Converter) Fig. 5.9 Operation modes of buck-boost converter. With the aid of Fig. 5.9, the derivation procedures for getting the results tabulated in Table 5.1 and Table 5. are explained by a buck-boost converter as follows: Step 1 - Derivation of the load line. The load line is derived by considering the average steady-state inductor current i L,ref. For buck-boost converter, i v i o o L, ref io (5.19) vin where v in is the input voltage, and v o and i o are the output voltage and current, respectively. Step - Determination of x, y and k s1. For buck-boost converter, the control variable x is firstly selected as the inductor currenti L. As shown in Fig. 5.9(a), during on-

173 Chapter state interval, dv di o L Lv RCv o (5.0) in where L and C are the inductor and output capacitor, respectively, and R is the equivalent load resistance. By using (5.1), it can be shown that k s1 1 1 y k s1 ( il il, ref ) dil ( LiL Cvo Cvin vo ) (5.1) L Hence, y can be chosen as 1 y Li L 1 Cv o Cv in v o (5.) L k s 1 (5.3) Step 3 - Determination of k s. As shown in Fig. 5.9(b), during off-state interval, d y di L d y dt Lvin ( il il,ref ) (5.4) dt di v L o k Lv in s (5.5) vo Step 4 - Calculation of y ref. Based on (5.19) and (5.), 1 v i 1 ( ) (5.6) o o y ref L io C vo, ref C vin vo, ref vin Step 5 - Formation of the control law. According to (5.7), the switching criterion is described as follows. The switch S is turned on if

174 Chapter y ( t) k1 ( il il, ref ) ( yref y) 0 and il( t) il, ref (5.7a) S is turned off if y ( t) k ( il il, ref ) ( yref y) 0 and il( t) il, ref (5.7b) An ideal second-order switching surface is that k 1 = k s1 and k = k s. Step 6 - Implementation of control law. Based on the above derivations, the block diagram of the controller for buck-boost converter is shown in Fig Fig Block diagram of the proposed uniform controller for buck-boost converter.

175 Chapter Steady-State Characteristics (for Buck-Boost Converter) Switching Frequency (a) CCM. (b) DCM. Fig Switching surface and the steady-state trajectories of buck-boost converter.

176 Chapter The effect of the equivalent series resistance (ESR) of the output capacitor is taken into account for the analysis as it is critical to the switching frequency variation. Define ESR v o as the measured output and act vo as the actual capacitor voltage. It can be shown that v v i R (5.8) ESR act o o C C where i C is the capacitor current, i C = -i o during the on-state period and i C = i L -i o during the off-state period. R C is the ESR of output capacitor. Therefore, the measured y ESR and ESR yref including ESR effect are given by ESR 1 1 act act y LiL C( vo icrc) Cvin( vo icrc) (5.9) ESR 1 1 act act yref LiL, ref C( vo, ref ic RC ) Cvin ( vo, ref ic RC ) (5.30) Fig presents the and the steady-state trajectory of buck-boost converter operated in CCM and DCM. Points A (y 1, x max ) and B (y, x min ) are on the switching surface of and as shown in Fig. 5.11(a) to illustrate the CCM case: y yref k ( xmax xref ) y 0 (5.31a) 1 y yref k ( x xref ) y 0 (5.31b) 1 min At steady-state, the ripple currents x max x ref and x ref x min are of the same value. As points A and B are both on the on and off state trajectories, y 1 = y. Substitute ESR y y1, ESR 1 y y, (5.6), (5.9) and (5.30) into (5.31), resulting in y k k ESR ESR 1 ESR 1 y y yref (5.3) k1 k

177 Chapter x x min max RCCv ( in vo) 4( k1 k) RCv C ( in vo) io vin y RCv C ( in vo) ( k k ) 1 (5.33) where xmin xref xmin and xmax xmax xref. When R C = 0, x x min_ RC0 max_ RC0 y k k 1 (5.34) For buck-boost converter, when S is on, i L v in t on L, where t on is the on time. When S is off, i L v o t off L, where t off is the off time. Therefore, the switching frequency f s_ccm of the buck-boost converter operated in CCM is f s_ CCM ( k1 k) vovin L( vin vo ) RCC( vin vo ) 4( k1k) RCC( vin vo ) io vin y RCC( vin vo ) (5.35) By substituting R C = 0 into (5.35) to obtain the switching frequency excluding the effect of ESR as follows: f s_ CCM _ RC 0 o in Lv ( v) in vv o y k k 1 (5.36) When operated in DCM, x reaches to zero during the off-state period as indicated by the points B (y, 0) and C (y 3, 0) shown in Fig. 5.11(b). In a similar way, it yields x max x ref RCCv ( in vo) 4( k1k) RCv C ( in vo) io vin y RCv C ( in vo) ( k k ) 1 (5.37)

178 Chapter For buck-boost converter, the average inductor current is equal to x ref, given by I L L( v v ) i 1 il,max Li 0 L LiL 1 in o L,max il dil dil T 0 i s v L,max in v (5.38) o Ts vinvo According to (5.6), (5.37) and (5.38), f oo s_ DCM RCv C ( in vo) 4( k1 k) RCv C ( in vo) io vin y RCv C ( in vo) vin v o L io vin ( k1 k) vi (5.39) When R C = 0 f vi oo s_ DCM _ RC 0 vin vo y L io vin k1 k (5.40) Fig. 5.1 presents the switching frequency of buck-boost converter with the proposed control scheme. In DCM, the switching frequency increases with load current and reaches a constant value when the converter enters into the CCM if ideally R C = 0. The switching frequency in DCM increases slightly with the ESR of the output capacitor, while in CCM it drops with the increasing value of ESR. Therefore, an output capacitor with low ESR is beneficial to reduce the variation of the switching frequency in CCM.

179 Chapter k DCM CCM Switching frequency (Hz) 34k 30k 6k k 18k 14k 10k Switching frequency (Hz) 35k 34k 33k 3k 31k R C increase 30k 0,17 0, 0,7 0,3 0,37 Output current (A) R C increase 0.00E+00 R C = E-03 R C = mω 6.00E-03 R C = 6 mω 1.00E-0 R C = 10mΩ.00E-0 R C = 0 mω 0 0,5 1 1,5,5 3 3,5 4 4,5 5 Output current (A) Fig. 5.1 Steady-state switching frequency of buck-boost converter with the controller Output Voltage For buck-boost converter, the minimum and maximum voltages occur when the inductor current i L reach highest and lowest levels, respectively. According to Fig. 5.11, i L, ref il,max C vin vo, min 1 1 y1 Cvo,min L (5.41a) y i L, ref il,min C vin vo, max 1 1 Cvo,max L (5.41b) Based on (5.3), (5.34) and (5.41),

180 Chapter v o, max A BiL, ref vin (5.4) v o, min A BiL, ref vin (5.43) where k1 k L A ( vin vo, ref ) y and C k k 1 B L C y k k 1. Thus, the average output voltage v o,av is given by v A Bi A Bi L, ref L, ref o, av vin (5.44) d v d i o, av L, ref B 1 4 A BiL, ref A BiL, ref 1 0 (5.45) It reveals from (5.45) that the steady-state output voltage will be slightly decreased with the increase of load. Fig plots the average output voltage under different loading condition when v in = 48 V, v o,ref = 48 V, y =.4 mv, k 1 = and k = It can be noted that the maximum variation of the average output voltage from no load to rated load is 64 mv.

181 Chapter ,010 48,000 Average output voltage (V) 47,990 47,980 47,970 47,960 47,950 47,940 47, ,5 1 1,5,5 3 3,5 4 4,5 Output current (A) Fig Average output voltage versus output current of buck-boost converter with proposed uniform control law (v in = 48 V, v o,ref = 48 V, y =.4 mv, k 1 = and k = ) Experimental Verifications A 190 W, 48/48 V prototype of buck-boost converter is built with an inductor of 0.36 mh and output capacitor of 150 µf. For the sake of investigation, the proposed control method is implemented according to Fig by a digital method. The prototype is tested under six kinds of load change conditions: a) output resistance is from 47 Ω to1.3 Ω, and vice versa; b) the value of output resistor reduces from 100 Ω to 1.3 Ω, and vice versa, and (c) a large load variation with output resistance from 500 Ω to 13.6 Ω, and vice versa. Fig. 5.14(a) and Fig. 5.15(a) present waveforms of the output voltage v o, output current i o, inductor current i L and switching signal V GS under a load change from 1.0 A to

182 Chapter A and vice versus. The converter operates in CCM under both loading condition. It can be observed from the gate signal V GS that the output voltage approaches to the steadystate after two switching actions. The setting time is 30 μs and 4 μs for the transients of load increase and load decrease, respectively. Fig. 5.14(b) and Fig. 5.15(b) show the dynamic response of the converter when the load is switched between the value for critical current conduction mode operation and nominal value. The load currents are 0.48 A and 3.9 A, respectively. The inductor current reaches zero at the end of each cycle. A fast dynamic response and well output voltage regulation can be maintained. Fig. 5.14(c) and Fig. 5.15(c) give the dynamic response when the operation mode of the converter change from DCM to CCM or versus after large signal disturbance. The load currents are switched between A and 3.53 A. It can be observed that the converter reaches steady-state by two switching actions for energy absorbing and releasing, confirming that the same controller is suitable for both CCM and DCM operation. The variations of the average output voltages are 45 mv, 60 mv and 70 mv respectively for the three cases of load increase, as presented in Fig (a), (b) and (c).

183 Chapter (a) (b)

184 Chapter (c) Fig Waveforms of dynamic response under increased loading condition. (a) R L from 47 Ω to 1.3 Ω, (b) R L from 100 Ω to 1.3 Ω, (c) R L from 500 Ω to 13.6 Ω. (v o : (ac) 500 mv/div, i o : A/div, i L : 5 A/div, v GS : 0 V/div and Timebase: 100 µs/div).

185 Chapter (a) (b)

186 Chapter (c) Fig Waveforms of dynamic response under reduced loading condition. (a) R L from 1.3 Ω to 47 Ω, (b) R L from 1.3 Ω to 100 Ω, (c) R L from 13.6 Ω to 500 Ω.(v o : (ac) 500 mv/div, i o : A/div, i L : 5 A/div, v GS : 0 V/div and Timebase: 00 µs/div). Fig shows the output voltage, output current and driving signal when start-up. The switch is always off to release the energy stored in the inductor to the load to increase the output voltage level before reaching steady-state. The start-up time is measured with.15 ms. Fig presents the measured switching frequency at R c = 1.4 mω. With output capacitor of low ESR, the switching frequency is found to vary 4. khz when the converter is operated from critical conduction mode to the rated load.

187 Chapter Fig Waveforms of start-up period of buck-boost converter (v o : 50 V/div, i o : 1 A/div, v GS : 0 V/div and Timebase: ms/div). 38k 36k Switching frequency (Hz) 34k 3k 30k 8k 6k 4k k 0k Experimental results Calculation (Rc=0) C = 0) Calculation (Rc=1.4mΩ) C = mω) 0 0,5 1 1,5,5 3 3,5 4 Output current (A) Fig Measured switching frequency of buck-boost converter.

188 Chapter Chapter Summary A uniform fast transient controller with second-order switching surface for basic dcdc converters is proposed. State variables such as capacitor voltage and inductor current are transformed to Cartesian x-y plane to formulate a general form of switching criterion for different types of dc-dc converters. The control parameters are obtained readily by considering the component values of the power stage without any sophisticated calculations. Stability analysis has been carried out by varying the control parameters in different regions. Derivation steps, design approaches and steady-state analysis are demonstrated with a buck-boost converter. A 48/48 V 190 W prototype has been built and tested under both CCM and DCM conditions. It has been verified that the control method addresses a complete operation and does not differentiate startup, transient, and steady-state intervals. The results of the large-signal response are in good agreement with the theoretical predictions.

189 Chapter CHAPTER 6 A DC-LINK MODULE FOR REDUCING DC-LINK CAPACITANCE 6.1 Introduction The aluminum electrolytic capacitors (E-Caps) consume considerable power and induce reliability concern in one of the prototypes of the high input voltage converter presented in Chapter 3. The observations motive that partial of the work is devoted to the component level research of capacitors. It explores the possibilities to reduce the dc-link capacitance in general capacitor-supported power electronic systems, which in turn has the potential to be applied in the front-end ac-dc stage of high-voltage dc-dc converters. Accordingly, a dc-link module consists of a dc-link capacitor and a voltage compensator connected in series with the dc bus line is proposed. The compensator processes the ripple voltage and reactive power only and thus can be implemented with switches and capacitors of low voltage rating. The capacitance value used in the dc-link module is significantly reduced from the original one. Therefore, it allows the use of alternatives (e.g., power film capacitor) with long lifetime and low power loss to replace E- Caps with comparable size and cost. Simulation on several types of power electronic converters and prototype testing on a power factor corrector (PFC) verify the feasibility of the proposed concept.

190 Chapter Basic Concept of the Proposed DC-Link Module A typical power conditioning system consists of multiple power converters interconnected by a high-voltage dc-link. Fig. 6.1 shows an example with two converters. The first converter is used to convert the input, either in the form of ac or dc, into dc. The second converter is used to provide the required form of power to the load from the dc-link. The dc-link voltage is supported by a capacitor bank, which is used to absorb the instantaneous power difference between the input source and output load, minimize the voltage variation on the dc-link, and in some applications provide sufficient energy during the hold-up time of the whole system. Fig. 6.1 Block diagram of a typical capacitor-supported power electronic conversion system. Fig. 6. Basic concept of the proposed dc-link module.

191 Chapter Fig. 6. illustrates the basic concept of the proposed dc-link module with reduced dc-link capacitance. The dc-link capacitor is connected to the output of the front-end power conversion stage. Typically, the previous stage is a bridge rectifier or PFC, which generates a dc voltage and an ac ripple component. As shown in Fig. 6., the capacitor voltage v C is composed of a dc component V C superimposed a voltage ripple of Δv C with a peak-to-peak value of vc. To decouple these two parts, a voltage compensator is connected in series with the dc-bus to generate an ac voltage v ab that closely follows the ripple voltage Δv C. Therefore, an ideal dc voltage V DC will appear at the two terminals of the bus line. A much higher voltage ripple is allowed on the dc-link capacitor. The value of dc-link capacitance depends on the designed maximum magnitude of v ab permitting the reduction of the value of the capacitor. The dc-link capacitor together with the proposed voltage compensator forms a dc-link module that can be applied in various capacitor-supported power electronic systems. 6.3 Steady-State DC and AC Analysis A dc analysis of the circuit shown in Fig. 6. gives V d V (6.1) C I d I (6.) A where V d and V C are the dc components of v d and v C, respectively, and I d and I A are the dc component of i d and i A, respectively. An ac analysis of the circuit in steady-state operation is taken by assuming that

192 Chapter i () t I sin t (6.3) A A i () t I sin t (6.4) d d where i and i are the ac components of i A d d and i A, respectively, I A and Id are the amplitudes of respectively. i and i A d, respectively, and 1 and are the frequencies of i and i A d, Thus, the ac component of v C, (i.e., vc ) and v ab (i.e., vab ) can be expressed as 1 vab() t vc () t ia() t id () t dt C I I sin 90 sin 90 d t t A 1 1 1C C (6.5) Based on (6.4)-(6.5), the average power P ab provided by the voltage compensator in a period T is given by 1 T Pab v () () 0 ab t id t dt T I T d IA sin CT 0 1 t 1 1 dt (6.6) where T is the least common multiple of. It can be noted that P ab = 0 except and 1 for a special case when 1 and 1. Therefore, the voltage compensator handles reactive power only in all of other cases. For the special case mentioned, the dc-link capacitance can be reduced by synchronization control of the phase 1 and without the proposed voltage compensator. The apparent power of the voltage compensator is given by

193 Chapter S I I I I 1 1 ab A d d d 1C (6.7) Therefore, when 1 or1 and 1, the reactive power processed by the voltage compensator is equal to S ab, that is 1 1 Qab IA Id Id Id 1C (,or and = ) (6.8) The output terminal voltage (i.e.,v ab ) of the voltage compensator is only the voltage ripple of the dc-link. Therefore, S ab presented by (6.7) is considerable small compared to that of the specific main dc-link power conversion system. Especially, the apparent power rating is reduced significantly compared to that of the solutions with parallel active circuits discussed in Section Series-Connected Voltage Compensator Implementation Fig. 6.3 shows the implementation of v ab and its control method. v ab is an dc-ac converter consisting of a full-bridge (FB) and an output filter formed by the inductor L f and capacitor C f. Its dc side is connected to an energy storage device such as a capacitor or voltage source. The gate signals for the switches S 1 -S 4 in the FB are generated by a PWM modulator. It should be noted that the power stage could be implemented by a half-bridge for loads with unidirectional current flow. The voltage ripple on C is sampled by a scaling factor of α. In order to avoid v ab from generating dc voltage, the dc output of v ab is

194 Chapter extracted by a low-pass filter. The output of the low pass filter passes to a PI control block. The output of the PI block, v os, is combined with the ripple voltage on C to compose the modulating signal v m for the PWM modulator. Power Stage S 1 D S1 S D S C a + v a L f C f S 3 D S3 S 4 D S4 i a a b i d i C v ab Front-end stage C + v C voltage sense voltage sense and low pass filter v d Load PI V C - v fd + vcon = - v + C DC offset v os v m M a PWM controller Control Stage driving signals for S 1 -S 4 Fig Implementation of the voltage compensator Analysis of the Voltage Compensator Figs. 6.4(a) and (b) present the operating modes of the voltage compensator. When S and S 3 are on, the capacitor C a is charged by the load current i d and when S 1 and S 4 are on, the capacitor C a is discharged. Fig. 6.4(c) shows the waveforms of the dc-link

195 Chapter capacitor voltage v C, modulating signal v m, carrier signal v tri, and the voltage across C a, v a. It should be noted that the control signal v con may contain multiple frequency components as it is obtained by scaling down Δv C. According to (6.5), the amplitude modulation ratios for different frequency components can be defined as m a1 I A (6.9) CV 1 tri m a I d (6.10) CV tri where is the scaling factor v / v used for PWM. con C and V tri is the amplitude of the tri-angular waveform

196 Chapter i Lf L f i d a i Lf L f i d a i Cf i Cf v a C a C f v ab v a C a C f v ab (a) b (b) b v C,max vc t v C,min V tri V m t v a,max va v a,min t 0 t 1 t (c) Fig Operation of the voltage compensator: (a) operating mode when S and S 3 are on, (b) operating mode when S 1 and S 4 are on and (c) SPWM and the voltage across C a. t To study the charging and discharging processes of C a, t 0 and t 1 in Fig. 6.4 (c) are defined as the two time instants when Δv C is across zero within one period. During t 0 -t 1, the capacitor C a is being charged by the load current and its voltage increases from minimum to maximum. Based on Fig. 6.4 and unipolar SPWM principle discussed in [169], the voltage across C a during t 0 -t 1 is given by

197 Chapter t v () t v I I sin t i () t Ca Ca,min d d Cf C t0 a v Ca,min ma 1sin 1t 190 masin t 90 dt t Id ma 1sin 1t190masin t 90dt t 0 t ma 1 Id sin 1t 1 90 sin t 1 dt t0 t Ca ma Id sin tcostdt t 0 t - icf ( t) ma 1sin1t190ma sint 90dt t 0 (6.11) where v Ca,min is the minimum voltage on C a. During t 0 -t 1, the net charge of the filter capacitor C f by i Cf is zero, therefore, when 1, the voltage ripple of C a, vca, is given by 1 v I m t m t dt t1 Ca d a1sin asin 90 C t 0 a m I m I sin t sint sin t sin t a1 d a d Ca Ca (6.1) For practical applications when is much larger than 1, the effect of the second terms of (6.5) and (6.1) are negligible and sin t 1, t 11 1 sin 1, therefore, 10 1 m I (6.13) a1 d vca 1C a The above equation is also applicable for the case when is even multiples of 1 as sin t sin t. The voltage across C a is therefore presented by 1 0 m I v t V t Ca a1 d sin C a 1 1 (6.14) 1C a The output voltage of the voltage compensator v ab is obtained by

198 Chapter ma 1I d vab t VC a sin 1t1 ma1sin 1t190ma sin t 90 1C a m I Ca a1sin asin 90 sin 1 1 1C a a1 d V m t m t t (6.15) The first term of (6.15) is used to cancel the dc-link voltage ripple while the second term is a double frequency ripple that generates voltage variation on v d. 6.5 Design of Capacitors for DC-Link and the Voltage Compensator Design of the DC-Link Capacitor The reduction of the dc-link capacitance is limited by the voltage stresses on the input capacitor and switching devices of the voltage compensator. Fig. 6.5 plots the tradeoff design curve. Without the proposed voltage compensator, it requires a capacitance of C norm meeting the design specification. Practically, the required one may be larger than C norm to sustain ripple current stress. Moreover, the dc-link voltage ripple will increase from v, to v C C nom due to the aging process with a decay of the capacitance value. With the proposed voltage compensator, the selection of the dc-link capacitance C is independent of the required dc-link voltage ripple, but is compromised with the allowable voltage stress on the capacitor C a and MOSFETs S 1 -S 4. A smaller value of C requires higher voltage ratings of C a and S 1 -S 4. Moreover, a boundary capacitance C bd can be determined based on specifications of power electronic systems, availability, cost and volume of different type of capacitors. It provides guideline on the selection of capacitor type. For instance, power film capacitors are applied in Selection 1 with a higher level of the dc component of v Ca, V Ca, compared to that of Selection in which E-caps are used.

199 Chapter With the aid of the proposed voltage compensator, the required dc-link capacitance can be reduced, making it possible to achieve long lifetime power electronic systems (i.e., by using power film capacitors) as well as maintaining high power density and comparable low cost. Fig. 6.5 V Ca -C curve for capacitance selection of the dc-link capacitor ( v Cnom, -half of the design specification of the dc-link voltage ripple, C nom -required dc-link capacitance without the voltage compensator, C nom - dc-link capacitance after certain degree of aging, C bd - boundary of the selected type of dc-link capacitor according to specifications, availability, cost and volume, V bd - value of V Ca corresponding to C bd Design of the Input Capacitor of the Voltage Compensator As illustrated in Fig. 6., the voltage compensator generates a voltage v ab that exactly follows the voltage ripple of the dc-link capacitor. However, in practical case, as revealed by (6.15), there is an undesirable voltage ripple with doubled frequency in v ab,

200 Chapter leading to variations in the output voltage of the proposed dc-link module. Therefore, the value of C a is designed to suppress the voltage ripple across the output terminals of the dclink module within the specification of v,. Cnom As the capacitor C a withstands a low voltage stress, there are many choices for practical implementation. One choice is to use low voltage E-caps with high ripple current and long lifetime. Unlike the ones with high voltage ratings, they are available and costeffective. Another choice is to use ceramic capacitor tank or low voltage film capacitors. 6.6 Simulation and Experimental Verifications Simulations Various type of power conversion systems are simulated with and without the proposed dc-link module. Table 6.1 tabulates the study cases. It covers both 400 V and 800 V dc-link systems with diode rectifier or PWM converter front-end stage and resistive load, inductive load or switching load. Fig. 6.6 presents the simulation results accordingly. It verifies the feasibility and applicability to apply the proposed dc-link module in various power electronic systems.

201 Chapter Front-end topology Table 6.1 Simulation cases Descriptions Case 1 Current sources (dc + ac) kw 400 V dc-link, inductive load Case Three-phase uncontrolled rectifier kw 800 V dc-link, resistive load. Case 3 Boost PFC front-end 1 kw, 400 V dc-link, resistive load Case 4 Case 5 Case 6 Single-phase full-bridge PWM rectifier Single-phase full-bridge PWM rectifier Boost PFC front-end kw 800 V dc-link, resistive load. kw 800 V dc-link, inductive load. 1 kw, 400 V dc-link, full-bridge converter load v Ca (V) (a) Simulation results with current source front-end and 400 V dc-link (I A = 5 A, I a = 1 A, Z L : 80+j0.063 Ω, C: 450 V/ 40 µf, C a : 50 V/1000 µf) (Case 1).

202 Chapter 6-19 v Ca (V) (b) Simulation on three-phase uncontrolled diode bridge rectifier with 800V dc-link voltage (P o = kw, load R L : 30 Ω, C: 900 V/ 40 µf, C a : 100 V /0 µf) (Case ). v Ca (V) (c) Simulation on boost PFC with controlled 400 V dc-link voltage (P o = 1 kw, R L : 160 Ω, C: 450 V/ 100 µf, C a : 50 V/1000 µf) (Case 3).

203 Chapter v Ca (V) (d) Simulation on PWM rectifier with 800 V dc-link voltage and resistive load (P o = kw, R L : 30 Ω, C: 900 V/ 50 µf, C a : 100 V/470 µf) (Case 4). v Ca (V) (e) Simulation on PWM rectifier with 800 V dc-link voltage and inductive load (P o = kw, load R L : 30 Ω, load L: 1 H, C: 900 V / 50 µf, C a : 100 V /470 µf) (Case 5).

204 Chapter v Ca (V) (f) Simulation on Boost PFC with 400 V dc-link voltage and full-bridge converter load (P o = 1 kw, V o = 48 V, R L :.3 Ω, C: 450 V/ 100 µf, C a : 50 V/1000 µf) (Case 6). Fig. 6.6 Simulation results of different application cases Experimental Verifications Two prototypes of the dc-link module have been built and implemented by analog circuit and low cost MCU, respectively, as shown in Fig The designed dc-link module is used to replace the E-caps in a PFC conversion system. The input of the voltage compensator is implemented by two 63 V E-caps with rated lifetime of 18,000 hours at nominal voltage and current stresses under 85 C. Their lifetime is comparable with that of the film capacitors used in the prototypes. To reduce the conduction losses, four low voltage (i.e., 100 V) MOSFETs are used in the FB inverter. Therefore, all of the components in the voltage compensator withstand very low voltage stresses.

205 Chapter (a) Voltage compensator implemented by an analog controller. (b) dc-link module implemented by a low cost MCU Fig. 6.7 Photos of the prototypes. Fig. 6.8 presents the experimental waveforms on a PFC product by using the prototype shown in Fig. 6.8(a). Fig. 6.8(a) shows the feedback control signal and output voltage v ab. It reveals that v ab is in phase with the feedback voltage ripple signal, therefore, in phase with the dc-link voltage ripple. The 450 V/940 µf E-caps used in the PFC board are replaced by a 450 V/ 110 µf power film capacitor with the proposed voltage compensator. Fig. 6.8(b) gives the captured waveforms tested at 500 W load. It can be