Design of a constant-voltage and constant-current controller with dual-loop and adaptive switching frequency control

Transcription

1 Vol. 36, No. 5 Journal of Semiconductors May 205 Design of a constant-voltage and constant-current controller with dual-loop and adaptive switching frequency control Chen Yingping( 陈映平 ) and Li Zhiqian( 李志谦 ) Sigma Micro Co. Ltd., Beijing 00029, China Abstract: A 5.0-V 2.0-A flyback power supply controller providing constant-voltage (CV) and constant-current (CC) output regulation without the use of an optical coupler is presented. Dual-close-loop control is proposed here due to its better regulation performance of tolerance over process and temperature compared with open loop control used in common. At the same time, the two modes, CC and CV, could switch to each other automatically and smoothly according to the output voltage level not sacrificing the regulation accuracy at the switching phase, which overcomes the drawback of the digital control scheme depending on a hysteresis comparator to change the mode. On-chip compensation using active capacitor multiplier technique is applied to stabilize the voltage loop, eliminate an additional package pin, and save on the die area. The system consumes as little as 00 mw at no-load condition without degrading the transient response performance by utilizing the adaptive switching frequency control mode. The proposed controller has been implemented in a commercial 0.35-m 40-V BCD process, and the active chip area is.5.0 mm 2. The total error of the output voltage due to line and load variations is less than.7%. Key words: constant voltage; constant current; dual-loop; adaptive switching frequency DOI: 0.088/ /36/5/ EEACC: Introduction More than half of the external power supplies that are used for portable electronics require both a constant output voltage and current regulations for battery charging. Traditionally, current sensing on the secondary side is always necessary, which needs an optical coupler. Although it offers a direct and easy way to capture the output voltage, the transfer function is highly nonlinear and dependent on both time and ambient temperature. This drawback imposes an upper constraint on the converter operating temperature, efficiency, and size Œ. Therefore, a primary side sensing technique was suggested by Nalepa et al. Œ in 200 to eliminate the optical coupler. The idea of primary side regulation (PSR) has since been further developed by others Œ2 6, which is also employed in this work due to its low cost and practice. Usually, for a constant-voltage (CV) and constant-current (CC) controller, a feedback loop with external compensation is utilized to control the output voltage while an open loop control method Œ7 is employed for the output current regulation by which the peak output current is regulated with a comparator and the duty cycle is fixed according to the demagnetization time detection. Its advantage is that only one compensation package pin needed. However, because the actual duty cycle would fluctuate as a result of the circuit s delay changing with process and temperature, the output current regulation turns out being very sensitive to the circuit parameters Œ3. Another control candidate is the digital method with an hysteresis comparator to realize the mode switching Œ. The output voltage is sensed and the control mode switches from CC to CV as the output voltage increases to a certain level, and vice versa. Thus, the regulation accuracy would be influenced at the transmitting phase. Additional control circuits are needed to limit the output current under CV mode, which complicates the system design. Therefore, a dual-close-loop control is designed carefully to overcome these drawbacks without increasing the package and chip cost. The Energy Star program was started by the Environmental Protection Agency in 992, and it promotes the use of energy efficient products and practices. The third element of the Energy Star specification is the no-load power requirement, which specifies a maximum AC power of less than 300 mw when the output power ranges from 0 to 50 W. In this work, an adaptive switching frequency control mode is implemented to reduce the no-load power to as little as 00 mw, which is much lower than the Energy Star s requirement. An advanced flyback CV/CC controller is proposed here. The detailed operation principle will be illustrated in Section 2. Section 3 discusses the design issues, including dual-loop compensation and the realization of the adaptive switching control. Section 4 exhibits the experimental results, which verify the design quite well. Section 5 gives a comparison with other typical products from international semiconductor giants to give an intuition of the performance of this work. 2. Principle of operation A constant-on-time (COT) control mode is applied to implement the dual-loop architecture and discontinuous conduction mode (DCM) with quasi-resonant switching control, which reduces the switching losses. Adaptive switching frequency control lowers the no-load power dissipation without sacrificing the transient response performance. A simplified block diagram of the converter is shown in Figure. A circuit samples the auxiliary winding s voltage, which reflects the out- Corresponding author. yingpingchen@hotmail.com Received 7 October 204, revised manuscript received 7 November Chinese Institute of Electronics

2 Figure. Block diagram of CV/CC controller. put voltage during the demagnetization period. The operational transconductance amplifier (OTA) GM consists of the output voltage regulation loop. On the other hand, the current loop includes the output current estimator, which works by sensing the peak primary current and secondary demagnetization time and OTA GM2. The conduction time of power switch MN is proportional to the difference of the outputs of GM2 and GM. A voltage control oscillator (VCO) extends the off time of MN at light load conditions to implement the adaptive switching frequency control. Its input is the output of GM, which characterizes the loading conditions, and it is reset at the start of every switching cycle. Figure 2 shows the main switching waveforms in detail. It is obvious that every switching cycle contains three periods: conduction, demagnetization, and valley detection. Figure 2. Switching waveforms. 2.. Output current regulation The controller works at CC mode when the output voltage is lower than the target value. The output of GM in Figure is clamped to a constant level, V CV_CLMP, and GM2 regulates the output current to a constant level through the feedback loop. Figure 3 shows a simplified diagram of the converter at CC mode. The output current estimator is a sampling and holding circuit, as shown in Figure 3. The switch K is closed during the conduction period and opened at the end point of conduction of MN. The peak primary current is sampled by this. A buffer is inserted to multiply the peak primary current by a coefficient k. The switch K2 is closed during the secondary demagnetization period and opened at another time of every cycle while K3 is just the opposite. A square wave exists at the node A and a low-pass filter is needed to smooth it as the negative input of GM2. At the steady state both of the inputs of GM2 are equal to each other. Therefore, the peak primary current is I ppk D k V ref_cc R sen T t dm ; () where I ppk is the peak primary current, T the switching period, and t dm the secondary demagnetization time. Figure 3. Equivalent diagram of CC control mode. As seen from Figure 2, the output current (the average secondary current) is calculated as I out D 2 I t dm spk T ; (2) where I out is the output current, and I spk the peak secondary current. I ppk and I spk are related as I spk D N ps I ppk ; (3)

3 2.3. Adaptive switching frequency control Figure 4. Equivalent diagram of CV control mode. where N PS is the primary-secondary turns ratio of the flyback transformer. By substituting Equations () and (3) into Equation (2), the output current is I out D 2k N V ref_cc ps : (4) R sen It can be seen from Equation (4) that the output current is determined by N PS, R sen, and V ref_cc. The first two parameters are estimated by discrete elements whose accuracy could be controlled to within %. The reference voltage is set to a reasonable range, i.e. 2%. As a result, the output current could be regulated accurately, i.e. 5% Output voltage regulation As the output voltage increases to the regulation level, the output voltage loop begins to respond. The output voltage of GM in Figure starts to rise up to reduce the conduction time of MN. On the other hand, the current loop attempts to maintain the output current at the maximum level, therefore the output of GM2 is also pulled up. Finally, the output of GM2 is clamped to a constant level acting as a reference voltage for the voltage loop. The controller enters the CV regulation mode. Figure 4 shows a simplified diagram of the converter at CV mode. It is seen from Figure 2 that the auxiliary winding voltage V aux at the end of the demagnetization is accurately proportional to the output voltage because it canceled the error induced by the forward voltage of the secondary diode. The sampling switch K4 is closed during the demagnetization period and opened at the end of demagnetization. At the steady state, V aux is equal to V ref_cv and the output voltage is regulated as V out D R ZD C R ZU V ref_cv ; (5) N AS R ZD where N AS is the auxiliary-secondary turns ratio of the flyback transformer, R ZU is the upper divider resistance, and R ZD is the down divider resistance of the auxiliary winding. Generally speaking there are two methods to reduce the no-load power dissipation. The first is to cut off the conduction time of the power FET, MN. However, a limitation exists for this control mode. As described in Section 2.2, the output voltage is sensed at the end of the secondary demagnetization. The current and voltage in the secondary winding would oscillate for some time (for example s) when MN switches off due to the leakage inductance of the primary winding. Therefore, leading edge blanking is necessary to prevent a wrong detection of the demagnetization time. This means that there is a minimum limitation of the conduction time to make sure that t dm is always longer than the leading edge blanking time, t LEB. Instead, the second method, which reduces the switching frequency adaptively according to the loading, is applied. As the load decreases the conduction time is reduced by the dualloop control and finally reaches the minimum level. The output of GM is then pulled up to extend the off time of MN through VCO in Figure. The control mode switches smoothly from valley switching to adaptive switching frequency control when the switching-off time determined by the VCO is larger than the sum of the demagnetization time and valley detection time. However, the switching frequency could not be reduced limitlessly because it would degrade the transient response performance severely, as explained in Section 3.. Hence, the minimum frequency is set to 2.0 khz. 3. Design considerations Two design considerations will be discussed in detail here. The first one is the dual loop compensation, and the other one is the tradeoff exiting between the no-load power dissipation and transient response performance. 3.. Dual-loop compensation Each loop in dual-loop system should be compensated to be stable separately to enable the system to work normally at any application conditions Œ8. Two criterions must be satisfied to ensure a stable loop of switching mode power supply under worst-case variation of the associated components Œ9. Firstly, the total open-loop phase shift must be less than 80 ı at the crossover frequency where the total open-loop gain achieves unity. Secondly, the gain slope at the crossover frequency must be 20 db/decade. The DC and low-frequency gain of a flyback converter is Œ9 P out D 2 L pippk 2 T D V O 2 ; (6) R O where is the efficiency of the converter, L p the primary inductance of transformer, R O the output resistor, and the peak primary current I ppk is I ppk D p 2Vrms L p t on ; (7) where V rms is the AC voltage and t on is the conduction time of the MN. By substituting Equation (7) into Equation (6) we get

4 2 L p p 2Vrms t on L p! 2 T D V 2 O R O : (8) As shown in Figure 2, the cycle time includes three parts: the conduction time t on, the secondary demagnetization time t dm, and the valley detection time. If we ignore the last part (in fact it is much less than the former two), the cycle time is: T t on C t dm : (9) Based on the relationship between the primary current and secondary current of flyback converter, t dm is related to t on as t dm D V ac V o N ps t on : (0) t on is decided by the difference of the outputs of GM2 and GM and it is calculated as t on D m.v GM2 V GM /; () where m is the coefficient set by the on-timer circuit, V GM2 the output of GM2, and V GM the output of GM. By combining Equations (8) (), the output voltage is derived as V O D 2 R Vac 2 O m.v GM2 V GM /: (2) L p V O C V ac =N ps The voltage loop V GM2 acts as a reference voltage for the on-timer, as described in Section 2.2. Therefore, the DC gain at CV mode is derived as A v_cv D 2 R Vac 2 O mg m_cv r o_cv ; (3) L p V O C V ac =N ps where A v_cv is the voltage loop DC gain, g m_cv is the transconductance, and r o_cv is the output resistance of GM. The minimum frequency is 5 khz, which is determined by the maximum conduction time and maximum switchingoff time at valley switching mode. Accordingly, the cross-over frequency is set to 5 khz. There is a pole located at the output node and the pole frequency is P O D 2R O C O : (4) And a left-half-plane zero that results from the ESR of the output capacitance locates at Z O D 2R ESR C O : (5) The electrolytic output capacitance is chosen to be 660 F as a result of the tradeoff between no-load power and transient response, as detailed in Section 3.2. The ESR of the output capacitance is estimated to be about 50 m. The output zero then locates at about 5 khz. The output pole is proportional to the output resistance inversely, while the voltage loop gain is proportional to the output resistance. This means that the influence of the output resistance on the bandwidth could be ignored, which simplifies the Figure 5. Magnitude curve of Bode plot. compensation procedure. Here, R O is set to be 2.5 when designing the compensation parameters. The output pole locates at 00 Hz in this case. The voltage loop DC gain s maximum value exists when V rms reaches the peak value, 264 V. For adaptor application, V o D 5.0 V, N ps D 6.0 and L p D mh. m is determined by the inner circuit as 24. According to Equation (3) the voltage loop DC gain is A v_cv D 62:3g m_cv r o_cv : (6) In order to stabilize the voltage loop, A v_cv is designed to be 64 db, which means that the GM s DC gain, g m_cv r O_CV, should be 30 db. R o_cv consists of a PMOS conductance resistance parallel with an NMOS conductance, whose value is about 7 M. Then, g m_cv is set as 5 S. The pole at the output node of GM is located at about.5 khz, and type compensation is applied to stabilize the voltage loop, which determines the compensation capacitance as.6 nf. The Bode plot after compensation is shown in Figure 5. It is seen that the magnitude curve crosses over 5 khz with a slope of 20 db/decade and the phase margin is about 45 ı due to the effect of the two poles and the ESR being zero. To decrease the number of package pins, the voltage loop compensation capacitor is implemented on chip. An active current-mode capacitor multiplier Œ0 is applied to reduce the capacitance and save the chip area. The principle circuit is shown in Figure 6. The aspect ratios of MP to MP2, MP3 to MP4, MN3 to MN4 and MN to MN2 are equal to n larger than. Basically, the current flowing through Miller capacitor, C m, is sensed by MN2 and multiplied by the factor n through the function of the mirror transistors MN. It is obvious that the equivalent capacitance at node A is equal to. C n/c m. In this case n is set to 40 and C m 40 pf to implement the voltage loop compensation. The same design procedure is followed to compensate the current loop. In contrast, the voltage loop is compensated with an off-chip capacitor and the compensation capacitance is estimated at 3.3 nf Tradeoff between no-load power and transient response As mentioned in Section 2.3, there is a tradeoff between the minimum switching frequency determined by adaptive fre

5 The maximum cycle is set to 700 s, which determines the VCO s parameters. In applications the primary inductance is advised to be larger than 0.5 mh. The minimum t on is designed as 400 ns. The maximum power dissipation at no-load condition is then calculated as 37 mw according to Equation (7). However, some other circuits, such as the rectifierbridge shown in Figure and a RCD clamper, dissipate power as well as the transformer and controller. As a result, the actual minimum no-load power dissipation is 00 mw. 4. Experimental results Figure 6. Current-mode capacitor multiplier. quency control mode and transient response performance. The minimum switching frequency should be designed carefully. The input power of the flyback converter is calculated as P in D Vac 2 ton 2 2 L p T : (7) It is seen that the power dissipation is proportional to the conduction time, t on, and proportional inversely to cycle time, T. In fact t on could not be reduced without limitation in order to ensure that the controller works normally, as described in Section 2.3. Therefore, an adaptive switching frequency control mode is applied to reduce the power dissipation at the no-load state. If the load changes from light to full after the demagnetizing period, then the output voltage would decrease continuously until the next demagnetization period because before that the controller could not detect the output voltage and would not react to the load changing. The worst case happens when the load increases from 0 to 2 A at the end point of demagnetization. For a 5-V output adaptor application, the output voltage should not be less than 3.2 V during transient response. The output capacitance is chosen as 660 F due to the trade off between the transient response and bulk. The maximum switching-off time is then determined as t off-max D C out V I full-load D 660 F :8 V 2 A D 590 s: (8) A new chip is developed based on the design idea in previous sections. The primary inductance is mh and the turnsratio of primary to secondary to auxiliary is 6 : : 3. A 5-k resistance is connected to the output as a pre-bias resistor in order to satisfy the requirement of 00 mw no-load power dissipation. The output capacitance is 660 F with electrolytic capacitors. As the input AC voltage rises from 85 to 264 V with a step 0 V, and the output load rises from no-load to full-load (2 A) with a step 0. A, the controller works stably. The total input power is tested to be nearly 00 mw when the input is 264 Vrms with an empty load. Figures 7(a) and 7(b) show the output curves at no-load and full-load, respectively, where the line voltage is 0 Vrms. It is seen from Figure 7 that a start-up delay exists. This is caused by charging the input capacitor of the controller through a large resistor (a M resistance used here) connected to the bus line. Once the input voltage reaches the start-up threshold voltage (set by the inner circuits) the controller begins to work and the output voltage rises. The difference between the delay of Figures 7(a) and 7(b) results from the different initial charges of the input capacitor. Figures 8(a) and 8(b) show the transient response curves when the load current changes from 0. to 0.5 A and from 0.5 to 0. A at 0 Vrms. It should be noted that the signal of Channel in Figure 8 represents the AC component of the output voltage. As seen from Figure 8, both the overshot and undershot voltages are less than 00 mv. Figures 9(a) and 9(b) show the load regulation and line regulation of the output voltage, respectively. As seen from Figure 9(a), the voltage decreases along with output current increasing at light loading. This results from the finite output resistance of the controller. However, as the output current rises even further, the output voltage ripples largely increase and dominate the influence, which leads to the increase of average voltage. Figure 9(b) illustrates that the output voltage increases with AC voltage, V rms, in general. According to the test results the load regulation is within.% and the line regulation within 0.6%. This should increase the open-loop gain of the voltage control loop to reduce the error that results from load regulation and line regulation. However, a large open-loop gain would enlarge the compensation capacitance in order to stabilize the loop since the cross-over frequency, and hence the unity-gain-bandwidth, has been determined by the minimum switching frequency requirement. 5. Comparison with typical products In order to give an intuitive insight to the performance of this work, Table lists the key features of four typical products

6 Figure 7. Start-up procedure at 0 Vrms. (a) Output voltage at no-load state. (b) 2 A full-load state. Figure 8. Transient response at 0 Vrms changing current load from (a) 0.5 to 0. A and (b) 0. to 0.5 A. Figure 9. Regulating performance. (a) Load regulation at different line voltages. (b) Line regulation at different load conditions. Table. Comparison with other typical products. Product Corporation CV accuracy (%) CC accuracy (%) No-load power (mw) UCC287 Texas Instruments Incorporated 5 5 < 0 AP3706 Diodes Incorporated < 200 MP020-5 Monolithic Power Systems 5 6 < 30 OB2520M On-Bright Electronics 5 6 < 200 This work Sigma Micro 5 5 < 00 by international semiconductor giants together with our work. The CV and CC accuracies include errors due to reference voltage error, line regulation, load regulation, and sampling error. Table illustrates that the regulation performance of our work is as good as the advanced products while the no-load power is intermediate among them. A chip based on this work has now passed the wafer-level test and been produced in massive quantities

7 6. Conclusions tron, 202, 27(): 4602 [4] Zhang J, Zeng H, Jiang T. A primary-side control scheme for An AC DC flyback controller is developed with primary high-power-factor LED driver with triac dimming capability. side control and dual loops to simultaneously regulate the output voltage and output current. Using current-mode capaci- [5] Xie X. Primary side constant output current controller for iso- IEEE Trans Power Electron, 202, 27(): 469 tor multiplier and off-chip capacitor compensation, the voltage loop and current loop separately save on the chip area and the number of pins. An adaptive switching frequency control mode is applied to make the no-load power as low as 00 mw lated high power factor flyback LED driver. China Patent, No , 200 [6] Xie X. Primary side constant output current controller with constant on-time for high power factor flyback LED driver. China without degrading the transient response performance. The total error of the output voltage due to the line regulation and Patent, No , 200 [7] Du S, Zhu F, Qian P. Primary side control circuit of a flyback converter for HBLED. Proc 2nd IEEE Int Symp Power Electron load regulation is.7%. Disturb Generation Syst, 200: 339 [8] Middlebrook R D. Topics in multiple-loop regulators and currentmode programming. IEEE Trans Power Electron, 987, PE-2(2): References [] Nalepa R, Barry N, Meaney P. Primary side control circuit of a flybackconvert. 6th Annual IEEE Applied Power Electronics Conference and Exposition, 200: [9] Pressman A I, Billings K, Morey T. Switching power supply design. 3rd ed. New York: Mc Grawl Hill, Inc, 2009 [2] Chang C W, Tzou Y Y. Primary-side sensing error analysis for [0] Rincon-Mora G A. Active capacitor multiplier in millcompensated flyback converters. Proc IEEE 6th International Conference on Power Electronics and Motion Control, 2009: 524 [3] Xie X, Wang J, Zhao C, et al. A novel output current estimation and regulation circuit for primary side controlled high power factor singled-stage flyback LED driver. IEEE Trans Power Elec- circuits. IEEE Trans Solid-State Circuits, 2000, 35(): 26 [] Chen Chen, He Lenian. Chip design of Li-ion battery charger operating in constant-current/constant-voltage modes. Chinese Journal of Semiconductors, 2007, 28(7):