DESIGN OF LOW POWER CMOS THREE INPUT XOR/XNOR
|
|
- Anastasia Leonard
- 6 years ago
- Views:
Transcription
1 DESIGN OF LOW POWER CMOS THREE INPUT XOR/XNOR D.lakshmaiah 1 (Ph.D),T.sai baba 2 M.Tech,B.sravani #, M. kalyani #, G.priya darshini #, D.shashi kumar # 1 Asso. Professor, 2 Assit.Professor # B.Tech students Christu Jyothi Institute of Technology and Science, Jangaon(Mdl.), Warangal(Dist.)T.S,INDIA Abstract: In this paper, we propose a new threeinput XOR/XNOR circuits to improve the speed and power as these circuits is basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. We start with selecting a basic cell including three independent inputs and two complementary outputs. Next we combine this basic cell with various correction and optimization techniques to build a perfect XOR-XNOR circuit with full swing operation. The performance of the XOR-XNOR circuits based on 90 nm CMOS technology process models at all range of the supply voltage is evaluated by the comparison of the simulation results obtained from MICRO WIND. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs. Key words : Binary Decision Diagram, 3-input XOR/XNOR circuits, CMOS. I.INTRODUCTION While the growth of the electronics market has driven the VLSI industry towards very high integration density and system on chip designs and beyond few GHz operating frequencies, critical concerns have been arising to the severe increase in power consumption and the need to further reduce it. Moreover, with the explosive growth th demand and popularity of portable electronics is driving designers to strive for smaller silicon area, higher speeds, longer battery life, and more reliability. Power is one of the premium resources a designer tries to save when designing a system. The XOR-XNOR circuits are basic building blocks in various circuit especially- Arithmetic circuits (Full adder, and multipliers), Compressors, Comparators, Parity Checkers, Code converters, Error-detecting or Error-correcting codes, and Phase detector circuit in PLL. We focus on XOR XNOR circuits as they are often used to obtain optimized performances for full adders. Balanced XOR XNOR circuits along with multiplexers are also the main components of compressors in parallel multiplication circuits. Also these circuits play an important role in comparator and parity checker blocks. Balanced XOR XNOR circuits, which serve as critical components in balanced complimentary outputs, eliminate power dissipated by the glitches. In any type of logic design, the non full swing outputs play a decisive role in cell weak drivability. Full swing outputs impact multi-stage structured arithmetic circuit performance. Therefore designers consider achieving full swing output operations as an important factor in arithmetic circuit basic block design. The performance of the complex logic circuits is affected by the individual performance of the XOR- XNOR circuits that are included in them [1]-[6]. Therefore, careful design and analysis is required for XOR-XNOR circuits to obtained full output voltage swing, lesser power consumption and delay in the critical path. Additionally, the design should have a lesser number of transistors to implement XOR- XNOR circuits and simultaneous generation of the two non-skewed outputs. In this paper a PTL based XOR and XNOR circuits were considers. Despite the saving in transistor count, the output voltage level is degraded at certain input combinations. The reduction in voltage swing, on one hand, is beneficial
2 to power consumption. On the other hand, this may lead to slow switching in the case of cascaded operation. We propose and compare new XOR- XNOR circuit designs which produce the XOR- XNOR outputs simultaneously with full output voltage swing. The NMOS and PMOS transistors are added to the basic circuits to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. We see many published papers that compete in designing better circuits [7]- [12]. Such studies mostly rely on creative design ideas but do not follow a systematic approach. As a consequence, most of them suffer from some different disadvantages [8]. 1) They are implemented with logic styles that have an incomplete voltage swing in some internal nodes, which leads to static power dissipation. 2) Most of them suffer from severe output signal degradation and cannot sustain lowvoltage operation. 3) They predominantly have dynamic power consumption for nonbalanced propagation delay inside and outside circuits, which results in glitches at the outputs. Therefore, a well-organized design methodology can be regarded as a strong solution for the challenge.cell design methodology (CDM) has been presented to design some limited functions, such as two-input XOR/XNOR and carry inverse carry in the hybrid- CMOS style [13] [15]. The predominant results persuade us to improve CDM through two stages: 1) generating more complex functions and 2) rectifying some remaining flaws. The flaws in previously published CDM include containing some manual steps in the design flow and generating a large number of designs in which the predominant ones would be determined after the completion of simulations. CDM is matured as systematic CDM (SCDM) in designing the three-input XOR/XNORs for the first time. It systematically generates elementary basic cell (EBC) using binary decision diagram (BDD), and wisely chooses circuit components based on a specific target. Therefore, after the systematic generation, the SCDM considers circuit optimization based on our target in three steps: 1) wise selection of the basic cell; 2) wise selection of the amend mechanisms; and 3) transistor sizing. We consider the power-delay product (PDP) as the design target. This method has some advantages. 1. It increases the driving capability and avoids the degradation on the output voltage. 2. It uses only less number of transistors in the critical path which results in less delay and power- delay product(pdp). 3. The dynamic consumption optimization comes from the fact of well-balanced propagation delay. 4. Power-ground-free main structure leads to power reduction. 5. The methodology has high flexibility in target and systematically consider it in the three design steps. This can lead to efficient circuits in terms of performance, power, PDP, EDP, area, or a combination of them. II.EXISTING WORK In this section, we will see the three-input XOR/XNOR circuits to examine their highperformance[16]. In complementary CMOS logic [16], the pull-down and pull-up networks used in the circuit perform the function in a complementary way. It has high noise margin and no static power consumption. In the CMOS with transmission gate,[16]there is a advantage of using less number of transistors. In complementary pass-transistor, it has a good output driving capability and pass-transistor logics gain their speed over the CMOS due to their high logic functionality. The XNOR-XOR circuit by using CMOS transistor and compare it with the proposed design of XNOR-XOR circuit using transmission gate with CMOS inverter circuit. Figure-1[16] shows the XNOR- XOR combine gate using CMOS transistor circuit. There are total sixteen transistors used in which 8 transistors are PMOS and rest are the NMOS transistors. The NMOS transistor can give the LOW signal completely, but it has very poor performance at HIGH signal. Similarly PMOS transistor can gives the HIGH signal completely, but poor performance at LOW signal. The a concept of transmission gates and CMOS inverter[17]. The CMOS inverter is driving the transmission gate to achieve the perfect output voltage swing. P and Q are given as the input of transmission gates through CMOS inverter. Output
3 of transmission gates gives the XNOR output and using an inverter we get the XOR output. The transmission gate allows to passes the signal through it, when the enable signal of transmission gate is high. The transmission gate has a n-channel device and a p-channel device, the n-channel MOS is situated on the bottom of the p-channel MOS. When zero signals apply to the enable (i.e. en) pin the transmission gate is off, and no signal is transferred through it. When enable signal is asserted high, the input signal appears to the output. III. PROPOSED WORK 1. INTRODUCTION OF CELLS In this section we introduce different basic cells which are used as a basis for designing various circuits. To pro-vide better understanding we first introduce the elementary structure, referred to as the elementary basic cell. 2. The Elementary Basic Cell In order to generate the EBC of three-input XOR/XNOR circuits, four steps are taken from. Initially, three-input XOR and its complement is represented by one binary decision tree (BDT) [18] in order to share common sub circuits. The step is followed by applying reduction rules to simplify the BDT representation[19]. These include elimination, merging, and coupling rules. The result of applied reduction rules to the tree is shown in Fig. 1(c). as the inputs into the first level are 0 s and 1 s of the function s truth table, the 0 and 1 can be replaced by the Y and Y, respectively. Then the simplified symbol can be divided into two distinct symbols: 1) the plus sign with the x input control and 2) the minus sign with the x input control. The result of applying steps 3 and 4 is shown in Fig. 1(d). The EBC, which is extracted from the above procedure, has been presented in Fig. 1(e). feedback pull up-down, bootstrap-feedback, inverterfeedback, and inverter-pull up-down]. Introduction of Feedback Networks All circuits with complementary outputs have the ability to optionally determine the state of an output or amplify it through the use of another output and a suitable transistor. Transistor or transistors which are placed between the two outputs to influence the second output through activating the first one, are called feedback networks. This feedback network is placed between the two complementary out-puts and causes the high impedance output states to be eliminated and replaced by the desired levels. Also, it is possible to ensure full swing operation at the outputs. As different basic cell versions presented in this work come with different short comings, the required feedback net-work should be different. We use four different feed back networks and they are: Fp, Fn, Fc and Fnp. Fp is a feedback network using two pmos transistors. Fn is a feedback network with two nmos transistors. Fc is a complementary feedback network and Fnp includes nmos and pmos transistors placed between the two complementary outputs Y and Y. Note that we improve the driving capability of feedback networks as we use VDD and GND connections. MECHANISMS Different mechanisms are optimization mechanisms to resolve non full swing [inverter and feedback ], correction mechanisms to resolve high impedance [pull up-down network and feedback ], or the combinations of them [bootstrap-pull up-down, Pull Up and Pull Down Networks
4 The use of pull up and pull down networks as a means of eliminating the critical states of a circuit is common and has been used in several reports[20]. The high impedance states should be replaced by 0 or 1.One possible solution is to use pull up and pull down networks. When facing output high impedance states, it is possibleto use a pull up network to connect Y or Y to the supply voltage.this results in replacing the high impedance state by logic 1.T o replace a high impedance state with logic 0, a pull down network is used to connect the output to ground. Output Inverters One way to ensure full swing operation at the outputs is to use output inverters. Adding inverters to the original circuit increases the number of transistors, power dissipation, area and the overall delay of the circuit. Meantime using inverters results in signal level restoration but enhances the circuit drive according to transistor sizes. Using this mechanism for the basic cells eliminates the non full swing operation but cannot replace high impedance states. Fig: Cmos Three-input XOR/XNOR circuit I. Bootstrap Technique By placing a boot transistor between the input and the gate terminal of the transistor we shift the gate voltage of the transistor.if the value of this shift is greater than or equal to the threshold transistor voltage (V T ) the transistor can transfer data to the outputs perfectly and there will be no voltage drop due to transistor s threshold voltages. Experimental results and analysis of the circuit reveals that in order to provide the capacitive property and for the boot phenomenon to occur, boot transistors and main transistors should be of the same type. Fig: Cmos Three input XOR/XNOR circuit II. Fig: Cmos Three input XOR/XNOR circuit III. IV.PERFORMANCE AND SIMULATION
5 The performance of our proposed designs of threeinput XOR/XNOR are simulated below. Based on the performance of the proposed designs the power, delay and PDP values are tabulated and compared with the existing circuits power delay 0 Cmos 90nm Cmos 65nm Fig : output waveform of circuit I Fig: power and delay of CMOS circuit I Cmos 90nm Cmos 65nm Power Delay Fig: power and delay of CMOS circuit II Fig: output waveform of circuit II Cmos 90nm Cmos 65nm Power Delay Fig: Power and Delay of CMOS circuit III Fig: output waveform of circuit III The performance results show that the feedback networks are better to produce full output swing.
6 TABLE : COMPARISIONS OF THE DELAY, POWER,PDP,AREA OF THREE-INPUT XOR/XNOR CIRCUITS. PROPOSED WORKS Cmos Circuit I Cmos Circuit II Cmos Circuit III V.CONCLUSION Power Delay PDP(femito) Area (mw) (ns) µm The use of XOR XNOR circuits has been the topic of numerous reports in the form of full adder circuits, compressors, parity checkers and comparators. The proposed designs have the better performance than the existing three input XOR/XNOR circuits. In this paper, we have used different types of optimization and correction mechanisms which has reduced the PDP, delay, and the number of transistors compared to the previous circuits[17]. ACKNOWLEDGEMENT We are thankful to our guide Mr. D.Lakshmaiah whose personal enrollment in the project has been a major source of inspiration for me to be flexible in my approach and thinking for tackling various issues. We express our sincere thanks to Mr. Rev. Y.PAPI REDDY and J.B.V SUBRAMANYAM, for providing necessary facilities in order to complete our project successfully. REFERENCES: [1] N. Weste, and K. Eshranghian, Principles of CMOS VLSI Design: A System Perspective, Reading MA: Addison-Wesley, 1993 [2] S.M. Kang, and Y. Leblibici, CMOS Digital Integrated Circuits: Analysis and Design, Tata McGraw Hill, [3] J.Rabaey, Digital Integrated Circuits: A Design Prospective, Prentice- Hall, Englewood Cliffs, NJ, [4] Sung-Chuan Fang, Jyh-Ming Wang, and Wu- Shiung Feng, A New Direct design for three input XOR function on the transistor level, IEEE trans. Circuits Syst. I: Fundamental theory and Applications, vol. 43, no. 4, April [5] H. T. Bui, Y. Wang, and Y. Jiang, Design and analysis of low-power 10 transistor full adders using XOR-XNOR gates, IEEE trans. Circuits Syst. II, Analog Digit. Signal Process, vol.49, no. 1, pp , Jan [6] D. Radhakrishanan, Low-voltage low-power CMOS full adder, in Proc. IEE Circuits Devices Syst., vol. 148, Feb [7] C.-K. Tung, S.-H. Shieh, and C.-H. Cheng, Lowpower high-speed full adder for portable electronic applications, Electron. Lett., vol. 49, no. 17, pp , Aug [8] M. Aguirre-Hernandez and M. Linares-Aranda, CMOS full-adders for energy-efficient arithmetic applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp , Apr [9] M. H. Moaiyeri, R. F. Mirzaee, K. Navi, T. Nikoubin, and O. Kavehei, Novel direct designs for 3-input XOR function for low-power and highspeed applications, Int. J. Electron., vol. 97, no. 6, pp , [10] S. Goel, M. A. Elgamel, M. A. Bayoumi, and Y. Hanafy, Design methodologies for highperformance noise-tolerant XOR-XNOR circuits, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp , Apr [11] S. Goel, A. Kumar, and M. Bayoumi, Design of robust, energy-efficient full adders for deepsubmicrometer design using hybrid-cmos logic style, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp , Dec [12] C.-H. Chang, J. Gu, and M. Zhang, A review of 0.18-μm full adder performances for tree structured arithmetic circuits, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp , Jun [13] T. Nikoubin, M. Grailoo, and S. H. Mozafari, Cell design methodology based on transmission gate for low-power high-speed balanced XOR-XNOR circuits in hybrid-cmos logic style, J. Low Power Electron., vol. 6, no. 4, pp , [14] T. Nikoubin, A. Baniasadi, F. Eslami, and K. Navi, A new cell design methodology for balanced XOR-XNOR circuits for hybrid- CMOS logic, J. Low Power Electron., vol. 5, no. 4, pp , [15] T. Nikoubin, M. Grailoo, and C. Li, Cell design methodology (CDM) for balanced Carry
7 InverseCarry circuits in hybrid-cmos logic style, Int. J. Electron., vol. 101, no. 10, pp , [16]Chien-Cheng Yu, Design of High Performance Three-input XOR/XNOR Circuit,HSIUPING JOURNAL. VOL.2.PP.197~208. [17]swati Sharma, Rajesh Mehra Area & Power Efficient Design of XNOR-XOR Logic Using 65 nm Technology. [18] C. Yang and M. Ciesielski, BDS: A BDD-based logic optimization system, IEEE Trans. Comput.- Aided Design Integr. Circuits Syst.,vol. 21, no. 7, pp , Jul B.Sravani,currently she is a final year student in Electronics and communication engineering branch from CJITS,Warangal(Dist.). D.Shashi Kumar,currently he is a final year student in Electronics and communication engineering branch from CJITS,Warangal (Dist.). Dayadi.Lakshmaiah(ph.D) is the Research scholar at JNTUK, Kakinada, Andhra Pradesh, India. He Received B.Tech Degree in ECE from National Institute of Technology, Warangal (RECW) and M.Tech (DSCE) Degree from JNTUA Anantapur. He has published 25 technical papers in International Journals..His area of interest is in Low Power VLSI. India. M.Kalyani,currently she is a final year student in Electronics and communication engineering branch from CJITS,Warangal (Dist). G.Priya Darshini,currently she is a final year student in Electronics and communication engineering branch from CJITS,Warangal (Dist.).
POWER DELAY PRODUCT AND AREA REDUCTION OF FULL ADDERS USING SYSTEMATIC CELL DESIGN METHODOLOGY
This work by IJARBEST is licensed under Creative Commons Attribution 4.0 International License. Available at https://www.ijarbest.com ISSN (ONLINE): 2395-695X POWER DELAY PRODUCT AND AREA REDUCTION OF
More informationEnergy Efficient high Performance Three INPUT EXCLUSIVE- OR/NOR Gate Design
2017 IJSRST Volume 3 Issue 6 Print ISSN: 2395-6011 Online ISSN: 2395-602X Themed Section: Science and Technology Energy Efficient high Performance Three INPUT EXCLUSIVE- OR/NOR Gate Design Aditya Mishra,
More informationLow Power Three-Input XOR/XNOR with Systematic Cell Design Methodology
Low Power Three-Input XOR/XNOR with Systematic Cell Design Methodology 1 G. Nagasundari, 2 S.R. Prabakar 1 PG student, Department of ECE, Vivekanandha College of engineering for women, Tiruchengode 2 AP/ECE,
More informationISSN:
343 Comparison of different design techniques of XOR & AND gate using EDA simulation tool RAZIA SULTANA 1, * JAGANNATH SAMANTA 1 M.TECH-STUDENT, ECE, Haldia Institute of Technology, Haldia, INDIA ECE,
More informationA Low-Power 12 Transistor Full Adder Design using 3 Transistor XOR Gates
A Low-Power 12 Transistor Full Adder Design using 3 Transistor XOR Gates Anil Kumar 1 Kuldeep Singh 2 Student Assistant Professor Department of Electronics and Communication Engineering Guru Jambheshwar
More informationCELL DESIGN METHODOLOGY FOR LOW-POWER HIGH-SPEED BALANCED THREE-INPUT XOR- XNOR IN HYBRID-CMOS LOGIC STYLE
CELL DESIGN METHODOLOGY FOR LOWPOWER HIGHSPEED BALANCED THREEINPUT XOR XNOR IN HYBRIDCMOS LOGIC STYLE. Abstract In this paper, a systematic design methodology based on pass transistor and transmission
More informationDesign of Low Power High Speed Hybrid Full Adder
IJECT Vo l. 6, Is s u e 4, Oc t - De c 2015 ISSN : 2230-7109 (Online) ISSN : 2230-9543 (Print) Design of Low Power High Speed Hybrid Full Adder 1 P. Kiran Kumar, 2 P. Srikanth 1,2 Dept. of ECE, MVGR College
More informationImplementation of Carry Select Adder using CMOS Full Adder
Implementation of Carry Select Adder using CMOS Full Adder Smitashree.Mohapatra Assistant professor,ece department MVSR Engineering College Nadergul,Hyderabad-510501 R. VaibhavKumar PG Scholar, ECE department(es&vlsid)
More informationDesign and Implementation of Complex Multiplier Using Compressors
Design and Implementation of Complex Multiplier Using Compressors Abstract: In this paper, a low-power high speed Complex Multiplier using compressor circuit is proposed for fast digital arithmetic integrated
More informationLow power high speed hybrid CMOS Full Adder By using sub-micron technology
Low power high speed hybrid CMOS Full Adder By using sub-micron technology Ch.Naveen Kumar 1 Assistant professor,ece department GURUNANAK institutions technical campus Hyderabad-501506 A.V. Rameshwar Rao
More informationComparative Study on CMOS Full Adder Circuits
Comparative Study on CMOS Full Adder Circuits Priyanka Rathore and Bhavna Jharia Abstract The Presented paper focuses on the comparison of seven full adders. The comparison is based on the power consumption
More informationDESIGN OF EXTENDED 4-BIT FULL ADDER CIRCUIT USING HYBRID-CMOS LOGIC
DESIGN OF EXTENDED 4-BIT FULL ADDER CIRCUIT USING HYBRID-CMOS LOGIC 1 S.Varalakshmi, 2 M. Rajmohan, M.Tech, 3 P. Pandiaraj, M.Tech 1 M.Tech Department of ECE, 2, 3 Asst.Professor, Department of ECE, 1,
More informationInvestigation on Performance of high speed CMOS Full adder Circuits
ISSN (O): 2349-7084 International Journal of Computer Engineering In Research Trends Available online at: www.ijcert.org Investigation on Performance of high speed CMOS Full adder Circuits 1 KATTUPALLI
More informationDesign and Analysis of CMOS based Low Power Carry Select Full Adder
Design and Analysis of CMOS based Low Power Carry Select Full Adder Mayank Sharma 1, Himanshu Prakash Rajput 2 1 Department of Electronics & Communication Engineering Hindustan College of Science & Technology,
More informationTwo New Low Power High Performance Full Adders with Minimum Gates
Two New Low Power High Performance Full Adders with Minimum Gates M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani Abstract with increasing circuits complexity and demand to use portable devices, power consumption
More informationTwo New Low Power High Performance Full Adders with Minimum Gates
Two New Low Power High Performance Full Adders with Minimum Gates M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani Abstract with increasing circuits complexity and demand to use portable devices, power consumption
More information& POWER REDUCTION IN FULL ADDER USING NEW HYBRID LOGIC V.
POWER REDUCTION IN FULL ADDER USING NEW HYBRID LOGIC V. Kayathri*, C. Kumar**, P. Mari Muthu*** & N. Naveen Kumar**** Department of Electronics and Communication Engineering, RVS College of Engineering
More informationDesign of Robust and power Efficient 8-Bit Ripple Carry Adder using Different Logic Styles
Design of Robust and power Efficient 8-Bit Ripple Carry Adder using Different Logic Styles Mangayarkkarasi M 1, Joseph Gladwin S 2 1 Assistant Professor, 2 Associate Professor 12 Department of ECE 1 Sri
More informationA Literature Survey on Low PDP Adder Circuits
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 4, Issue. 12, December 2015,
More informationISSN: [Narang* et al., 6(8): August, 2017] Impact Factor: 4.116
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY PERFORMANCE ANALYSIS OF A LOW-POWER HIGH-SPEED HYBRID 1-BIT FULL ADDER CIRCUIT AND ITS IMPLEMENTATION Swati Narang Electronics
More informationAn Efficient and High Speed 10 Transistor Full Adders with Lector Technique
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 12, Issue 5, Ver. II (Sep.- Oct. 2017), PP 68-73 www.iosrjournals.org An Efficient and
More informationDesign of High Speed Six Transistor Full Adder using a Novel Two Transistor XOR Gates
Design of High Speed Six Transistor Full Adder using a Novel Two Transistor XOR Gates 1 Pakkiraiah Chakali, 2 Adilakshmi Siliveru, 3 Neelima Koppala Abstract In modern era, the number of transistors are
More informationFull Adder Circuits using Static Cmos Logic Style: A Review
Full Adder Circuits using Static Cmos Logic Style: A Review Sugandha Chauhan M.E. Scholar Department of Electronics and Communication Chandigarh University Gharuan,Punjab,India Tripti Sharma Professor
More informationHigh Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells
High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi Abstract In this paper we present two novel 1-bit full adder cells in dynamic logic
More informationInternational Journal of Advance Engineering and Research Development
Scientific Journal of Impact Factor (SJIF): 5.71 International Journal of Advance Engineering and Research Development Volume 5, Issue 05, May -2018 e-issn (O): 2348-4470 p-issn (P): 2348-6406 COMPARATIVE
More informationEnergy Efficient Full-adder using GDI Technique
Energy Efficient Full-adder using GDI Technique Balakrishna.Batta¹, Manohar.Choragudi², Mahesh Varma.D³ ¹P.G Student, Kakinada Institute of Engineering and technology, korangi, JNTUK, A.P, INDIA ²Assistant
More informationAn energy efficient full adder cell for low voltage
An energy efficient full adder cell for low voltage Keivan Navi 1a), Mehrdad Maeen 2, and Omid Hashemipour 1 1 Faculty of Electrical and Computer Engineering of Shahid Beheshti University, GC, Tehran,
More informationA REVIEW PAPER ON HIGH PERFORMANCE 1- BIT FULL ADDERS DESIGN AT 90NM TECHNOLOGY
I J C T A, 9(11) 2016, pp. 4947-4956 International Science Press A REVIEW PAPER ON HIGH PERFORMANCE 1- BIT FULL ADDERS DESIGN AT 90NM TECHNOLOGY N. Lokabharath Reddy *, Mohinder Bassi **2 and Shekhar Verma
More informationImpact of Logic and Circuit Implementation on Full Adder Performance in 50-NM Technologies
Impact of Logic and Circuit Implementation on Full Adder Performance in 50-NM Technologies Mahesh Yerragudi 1, Immanuel Phopakura 2 1 PG STUDENT, AVR & SVR Engineering College & Technology, Nandyal, AP,
More informationDESIGN OF PARALLEL MULTIPLIERS USING HIGH SPEED ADDER
DESIGN OF PARALLEL MULTIPLIERS USING HIGH SPEED ADDER Mr. M. Prakash Mr. S. Karthick Ms. C Suba PG Scholar, Department of ECE, BannariAmman Institute of Technology, Sathyamangalam, T.N, India 1, 3 Assistant
More informationCHAPTER - IV. Design and analysis of hybrid CMOS Full adder and PPM adder
CHAPTER - IV Design and analysis of hybrid CMOS Full adder and PPM adder Design and analysis of hybrid CMOS Full adder and PPM adder 63 CHAPTER IV DESIGN AND ANALYSIS OF HYBRID CMOS FULL ADDER AND PPM
More informationII. Previous Work. III. New 8T Adder Design
ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: High Performance Circuit Level Design For Multiplier Arun Kumar
More informationDesign a Low Power CNTFET-Based Full Adder Using Majority Not Function
Design a Low Power CNTFET-Based Full Adder Using Majority Not Function Seyedehsomayeh Hatefinasab * Department of Electrical and Computer Engineering, Payame Noor University, Sari, Iran. *Corresponding
More informationDesign of Delay-Power Efficient Carry Select Adder using 3-T XOR Gate
Adv. Eng. Tec. Appl. 5, No. 1, 1-6 (2016) 1 Advanced Engineering Technology and Application An International Journal http://dx.doi.org/10.18576/aeta/050101 Design of Delay-Power Efficient Carry Select
More informationLow Power &High Speed Domino XOR Cell
Low Power &High Speed Domino XOR Cell Payal Soni Electronics and Communication Department, FET- Mody University Lakshmangarh, Dist.-Sikar, India E-mail: payal.soni3091@gmail.com Abstract Shiwani Singh
More information4-BIT RCA FOR LOW POWER APPLICATIONS
4-BIT RCA FOR LOW POWER APPLICATIONS Riya Garg, Suman Nehra and B. P. Singh Department of Electronics and Communication, FET-MITS (Deemed University), Lakshmangarh, India ABSTRACT This paper presents low
More informationA Low-Power High-speed Pipelined Accumulator Design Using CMOS Logic for DSP Applications
International Journal of Research Studies in Computer Science and Engineering (IJRSCSE) Volume. 1, Issue 5, September 2014, PP 30-42 ISSN 2349-4840 (Print) & ISSN 2349-4859 (Online) www.arcjournals.org
More informationGdi Technique Based Carry Look Ahead Adder Design
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 6, Ver. I (Nov - Dec. 2014), PP 01-09 e-issn: 2319 4200, p-issn No. : 2319 4197 Gdi Technique Based Carry Look Ahead Adder Design
More informationAnalysis of Different CMOS Full Adder Circuits Based on Various Parameters for Low Voltage VLSI Design
International Journal of Engineering and Technical Research (IJETR) Analysis of Different CMOS Full Adder Circuits Based on Various Parameters for Low Voltage VLSI Design Mr. Kapil Mangla, Mr. Shashank
More informationPERFORMANANCE ANALYSIS OF A 1-BIT FULL ADDER USING 45nm TECHNOLOGY
Research Manuscript Title PERFORMANANCE ANALYSIS OF A 1-BIT FULL ADDER USING 45nm TECHNOLOGY A.NIVETHA, M.Hemalatha, P.G.Scholar, Assistant Professor, M.E VLSI Design, Department of ECE Vivekanandha College
More informationLow power 18T pass transistor logic ripple carry adder
LETTER IEICE Electronics Express, Vol.12, No.6, 1 12 Low power 18T pass transistor logic ripple carry adder Veeraiyah Thangasamy 1, Noor Ain Kamsani 1a), Mohd Nizar Hamidon 1, Shaiful Jahari Hashim 1,
More informationDesign of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders
Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders B. Madhuri Dr.R. Prabhakar, M.Tech, Ph.D. bmadhusingh16@gmail.com rpr612@gmail.com M.Tech (VLSI&Embedded System Design) Vice
More informationInternational Journal of Scientific & Engineering Research, Volume 4, Issue 8, August ISSN
International Journal of Scientific & Engineering Research, Volume 4, Issue 8, August-2013 1156 Novel Low Power Shrikant and M Pattar, High H V Ravish Speed Aradhya 8T Full Adder Abstract - Full adder
More informationDesign of Two High Performance 1-Bit CMOS Full Adder Cells
Int. J. Com. Dig. Sys. 2, No., 47-52 (23) 47 International Journal of Computing and Digital Systems -- An International Journal @ 23 UOB CSP, University of Bahrain Design of Two High Performance -Bit CMOS
More informationInternational Journal on Emerging Technologies 1(1): 1-10(2010) ISSN :
e t International Journal on Emerging Technologies 1(1): 1-10(2010) ISSN : 0975-8364 comparative performance analysis of various CMOS design techniques for and circuits Shiv Shankar Mishra, darsh Kumar
More informationDesign & Analysis of Low Power Full Adder
1174 Design & Analysis of Low Power Full Adder Sana Fazal 1, Mohd Ahmer 2 1 Electronics & communication Engineering Integral University, Lucknow 2 Electronics & communication Engineering Integral University,
More informationDesign and Performance Analysis of High Speed Low Power 1 bit Full Adder
Design and Performance Analysis of High Speed Low Power 1 bit Full Adder Gauri Chopra 1, Sweta Snehi 2 PG student [RNA], Dept. of MAE, IGDTUW, New Delhi, India 1 PG Student [VLSI], Dept. of ECE, IGDTUW,
More informationEnhancement of Design Quality for an 8-bit ALU
ABHIYANTRIKI An International Journal of Engineering & Technology (A Peer Reviewed & Indexed Journal) Vol. 3, No. 5 (May, 2016) http://www.aijet.in/ eissn: 2394-627X Enhancement of Design Quality for an
More informationDesign of New Full Swing Low-Power and High- Performance Full Adder for Low-Voltage Designs
International Academic Institute for Science and Technology International Academic Journal of Science and Engineering Vol. 2, No., 201, pp. 29-. ISSN 2-9 International Academic Journal of Science and Engineering
More informationDesign and Analysis of Low-Power 11- Transistor Full Adder
Design and Analysis of Low-Power 11- Transistor Full Adder Ravi Tiwari, Khemraj Deshmukh PG Student [VLSI, Dept. of ECE, Shri Shankaracharya Technical Campus(FET), Bhilai, Chattisgarh, India 1 Assistant
More information2-BIT COMPARATOR WITH 8-TRANSISTOR 1-BIT FULL ADDER WITH CAPACITOR
2-BIT COMPARATOR WITH 8-TRANSISTOR 1-BIT FULL ADDER WITH CAPACITOR C.CHANDAN KUMAR M.Tech-VLSI, Department of ECE, Sree vidyanikethan Engineering college A.Rangampet, Tirupati, India chennachandu123@gmail.com
More informationLow-Power High-Speed Double Gate 1-bit Full Adder Cell
INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2016, VOL. 62, NO. 4, PP. 329-334 Manuscript received October 15, 2016; revised November, 2016. DOI: 10.1515/eletel-2016-0045 Low-Power High-Speed Double
More informationA HIGH SPEED DYNAMIC RIPPLE CARRY ADDER
A HIGH SPEED DYNAMIC RIPPLE CARRY ADDER Y. Anil Kumar 1, M. Satyanarayana 2 1 Student, Department of ECE, MVGR College of Engineering, India. 2 Associate Professor, Department of ECE, MVGR College of Engineering,
More informationA Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI)
A Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI) Mahendra Kumar Lariya 1, D. K. Mishra 2 1 M.Tech, Electronics and instrumentation Engineering, Shri G. S. Institute of Technology
More informationDesign of an Energy Efficient, Low Power Dissipation Full Subtractor Using GDI Technique
Design of an Energy Efficient, Low Power Dissipation Full Subtractor Using GDI Technique ABSTRACT: Rammohan Kurugunta M.Tech Student, Department of ECE, Intel Engineering College, Anantapur, Andhra Pradesh,
More informationINTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN ENGINEERING AND TECHNOLOGY (IJARET)
INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN ENGINEERING AND TECHNOLOGY (IJARET) International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 ISSN 0976-6480 (Print) ISSN
More informationCHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS
70 CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS A novel approach of full adder and multipliers circuits using Complementary Pass Transistor
More informationImplementation of High Performance Carry Save Adder Using Domino Logic
Page 136 Implementation of High Performance Carry Save Adder Using Domino Logic T.Jayasimha 1, Daka Lakshmi 2, M.Gokula Lakshmi 3, S.Kiruthiga 4 and K.Kaviya 5 1 Assistant Professor, Department of ECE,
More informationStudy of Threshold Gate and CMOS Logic Style Based Full Adders Circuits
IEEE SPONSORED 3rd INTERNATIONAL CONFERENCE ON ELECTRONICS AND COMMUNICATION SYSTEMS (ICECS 2016) Study of Threshold Gate and CMOS Logic Style Based Full Adders Circuits Raushan Kumar Department of ECE
More informationAustralian Journal of Basic and Applied Sciences. Optimized Embedded Adders for Digital Signal Processing Applications
ISSN:1991-8178 Australian Journal of Basic and Applied Sciences Journal home page: www.ajbasweb.com Optimized Embedded Adders for Digital Signal Processing Applications 1 Kala Bharathan and 2 Seshasayanan
More informationOPTIMIZATION OF LOW POWER ADDER CELLS USING 180NM TG TECHNOLOGY
OPTIMIZATION OF LOW POWER ADDER CELLS USING 180NM TG TECHNOLOGY Nitasha Jaura 1, Balraj Singh Sidhu 2, Neeraj Gill 3 1, 2, 3 Department Of Electronics and Communication Engineering, Giani Zail Singh Punjab
More information/$ IEEE
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 12, DECEMBER 2006 1309 Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic
More informationInternational Journal of Advanced Research in Biology Engineering Science and Technology (IJARBEST)
Abstract NEW HIGH PERFORMANCE 4 BIT PARALLEL ADDER USING DOMINO LOGIC Department Of Electronics and Communication Engineering UG Scholar, SNS College of Engineering Bhuvaneswari.N [1], Hemalatha.V [2],
More informationDESIGN OF ENERGY-EFFICIENT FULL ADDER USING HYBRID-CMOS LOGIC STYLE
DESIGN OF ENERGY-EFFICIENT FULL ADDER USING HYBRID-CMOS LOGIC STYLE 1 Mohammad Shamim Imtiaz, 2 Md Abdul Aziz Suzon, 3 Mahmudur Rahman 1 Part-Time Lecturer, Department of EEE, A.U.S.T, Dhaka, Bangladesh
More informationImplementation of Efficient 5:3 & 7:3 Compressors for High Speed and Low-Power Operations
Volume-7, Issue-3, May-June 2017 International Journal of Engineering and Management Research Page Number: 42-47 Implementation of Efficient 5:3 & 7:3 Compressors for High Speed and Low-Power Operations
More informationLow Power 32-bit Improved Carry Select Adder based on MTCMOS Technique
Low Power 32-bit Improved Carry Select Adder based on MTCMOS Technique Ch. Mohammad Arif 1, J. Syamuel John 2 M. Tech student, Department of Electronics Engineering, VR Siddhartha Engineering College,
More informationPERFORMANCE ANALYSIS OF LOW POWER FULL ADDER CELLS USING 45NM CMOS TECHNOLOGY
International Journal of Microelectronics Engineering (IJME), Vol. 1, No.1, 215 PERFORMANCE ANALYSIS OF LOW POWER FULL ADDER CELLS USING 45NM CMOS TECHNOLOGY K.Dhanunjaya 1, Dr.MN.Giri Prasad 2, Dr.K.Padmaraju
More informationA New High Speed - Low Power 12 Transistor Full Adder Design with GDI Technique
International Journal of Scientific & Engineering Research Volume 3, Issue 7, July-2012 1 A New High Speed - Low Power 12 Transistor Full Design with GDI Technique Shahid Jaman, Nahian Chowdhury, Aasim
More informationImplementation of 1-bit Full Adder using Gate Difuision Input (GDI) cell
International Journal of Electronics and Computer Science Engineering 333 Available Online at www.ijecse.org ISSN: 2277-1956 Implementation of 1-bit Full Adder using Gate Difuision Input (GDI) cell Arun
More informationDESIGN AND ANALYSIS OF LOW POWER 10- TRANSISTOR FULL ADDERS USING NOVEL X-NOR GATES
DESIGN AND ANALYSIS OF LOW POWER 10- TRANSISTOR FULL ADDERS USING NOVEL X-NOR GATES Basil George 200831005 Nikhil Soni 200830014 Abstract Full adders are important components in applications such as digital
More informationADIABATIC LOGIC FOR LOW POWER DIGITAL DESIGN
ADIABATIC LOGIC FOR LOW POWER DIGITAL DESIGN Mr. Sunil Jadhav 1, Prof. Sachin Borse 2 1 Student (M.E. Digital Signal Processing), Late G. N. Sapkal College of Engineering, Nashik,jsunile@gmail.com 2 Professor
More information12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders
12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders Mr.Devanaboina Ramu, M.tech Dept. of Electronics and Communication Engineering Sri Vasavi Institute of
More informationPerformance Analysis of High Speed CMOS Full Adder Circuits For Embedded System
ISSN (O): 2349-7084 International Journal of Computer Engineering In Research Trends Available online at: www.ijcert.org Performance Analysis of High Speed CMOS Full Adder Circuits For Embedded System
More informationA SURVEY OF LOW POWER HIGH SPEED ONE BIT FULL ADDER
A SURVEY OF LOW POWER HIGH SPEED ONE BIT FULL ADDER N. M. CHORE 1, R. N. MANDAVGANE 2 Department of Electronic Engineering B. D. College of Engineering Rashtra Sant Tukdoji Maharaj Nagpur University Wardha,
More informationA NOVEL 4-Bit ARITHMETIC LOGIC UNIT DESIGN FOR POWER AND AREA OPTIMIZATION
A NOVEL 4-Bit ARITHMETIC LOGIC UNIT DESIGN FOR POWER AND AREA OPTIMIZATION Mr. Snehal Kumbhalkar 1, Mr. Sanjay Tembhurne 2 Department of Electronics and Communication Engineering GHRAET, Nagpur, Maharashtra,
More informationArea and Power Efficient Pass Transistor Based (PTL) Full Adder Design
This work by IJARBEST is licensed under Creative Commons Attribution 4.0 International License. Available at https://www.ijarbest.com Area and Power Efficient Pass Transistor Based (PTL) Full Adder Design
More informationPower Efficient adder Cell For Low Power Bio MedicalDevices
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 2, Ver. III (Mar-Apr. 2014), PP 39-45 e-issn: 2319 4200, p-issn No. : 2319 4197 Power Efficient adder Cell For Low Power Bio MedicalDevices
More informationInternational Journal of Advance Research in Computer Science and Management Studies
Volume 2, Issue 8, August 2014 ISSN: 2321 7782 (Online) International Journal of Advance Research in Computer Science and Management Studies Research Article / SurveyPaper / Case Study Available online
More informationLow Power and High Performance ALU using Dual Mode Transmission Gate Diffusion Input (DMTGDI)
International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 8958, Volume-6 Issue-6, August 2017 Low Power and High Performance ALU using Dual Mode Transmission Gate Diffusion Input
More informationInternational Journal of Scientific & Engineering Research, Volume 4, Issue 5, MAY-2013 ISSN
High-Speed 64-Bit Binary using Three Different Logic Styles Anjuli (Student Member IEEE), Satyajit Anand Abstract--High-speed 64-bit binary comparator using three different logic styles is proposed in
More informationA Efficient Low-Power High Speed Digital Circuit Design by using 1-bit GDI Full Adder Circuit
Efficient Low-Power High Speed Digital Circuit Design by using 1-bit GDI Full dder Circuit Rohit Tripati #1, Paresh Rawat # PG Student [VLSI], Dept. of ECE, Truba College of Science and Technology hopal
More information2-Bit Magnitude Comparator Design Using Different Logic Styles
International Journal of Engineering Science Invention ISSN (Online): 2319 6734, ISSN (Print): 2319 6726 Volume 2 Issue 1 ǁ January. 2013 ǁ PP.13-24 2-Bit Magnitude Comparator Design Using Different Logic
More informationIMPLEMANTATION OF D FLIP FLOP BASED ON DIFFERENT XOR /XNOR GATE DESIGNS
IMPLEMANTATION OF D FLIP FLOP BASED ON DIFFERENT XOR /XNOR GATE DESIGNS 1 MADHUR KULSHRESTHA, 2 VIPIN KUMAR GUPTA 1 M. Tech. Scholar, Department of Electronics & Communication Engineering, Suresh Gyan
More informationA Novel Multi-Threshold CMOS Based 64-Bit Adder Design in 45nm CMOS Technology for Low Power Application
A Novel Multi-Threshold CMOS Based 64-Bit Adder Design in 45nm CMOS Technology for Low Power Application Rumi Rastogi and Sujata Pandey Amity University Uttar Pradesh, Noida, India Email: rumi.ravi@gmail.com,
More informationPerformance Comparison of High-Speed Adders Using 180nm Technology
Steena Maria Thomas et al. 2016, Volume 4 Issue 2 ISSN (Online): 2348-4098 ISSN (Print): 2395-4752 International Journal of Science, Engineering and Technology An Open Access Journal Performance Comparison
More informationDomino CMOS Implementation of Power Optimized and High Performance CLA adder
Domino CMOS Implementation of Power Optimized and High Performance CLA adder Kistipati Karthik Reddy 1, Jeeru Dinesh Reddy 2 1 PG Student, BMS College of Engineering, Bull temple Road, Bengaluru, India
More informationDesign of Modified Shannon Based Full Adder Cell Using PTL Logic for Low Power Applications
Design of Modified Shannon Based Full Adder Cell Using PTL Logic for Low Power Applications K.Purnima #1, S.AdiLakshmi #2, M.Sahithi #3, A.Jhansi Rani #4,J.Poornima #5 #1 M.Tech student, Department of
More informationDesign & Simulation of Half Adder Circuit Using AVL technique based on CMOS Technology
Design & Simulation of Half Adder Circuit Using AVL technique based on CMOS Technology Mateshwar Singh1, Surya Deo Choudhary 2, Ashutosh kr.singh3 1M.Tech Student, Dept. of Electronics & Communication,
More informationDesign a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Nano-Technology
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735. Volume 8, Issue 1 (Sep. - Oct. 2013), PP 19-26 Design a Low Power High Speed Full Adder Using
More informationPower-Area trade-off for Different CMOS Design Technologies
Power-Area trade-off for Different CMOS Design Technologies Priyadarshini.V Department of ECE Sri Vishnu Engineering College for Women, Bhimavaram dpriya69@gmail.com Prof.G.R.L.V.N.Srinivasa Raju Head
More informationDesign of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer
Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer Mr. Y.Satish Kumar M.tech Student, Siddhartha Institute of Technology & Sciences. Mr. G.Srinivas, M.Tech Associate
More informationPardeep Kumar, Susmita Mishra, Amrita Singh
Study of Existing Full Adders and To Design a LPFA (Low Power Full Adder) Pardeep Kumar, Susmita Mishra, Amrita Singh 1 Department of ECE, B.M.S.E.C, Muktsar, 2,3 Asstt. Professor, B.M.S.E.C, Muktsar Abstract
More informationA SUBSTRATE BIASED FULL ADDER CIRCUIT
International Journal on Intelligent Electronic System, Vol. 8 No.. July 4 9 A SUBSTRATE BIASED FULL ADDER CIRCUIT Abstract Saravanakumar C., Senthilmurugan S.,, Department of ECE, Valliammai Engineering
More informationSophisticated design of low power high speed full adder by using SR-CPL and Transmission Gate logic
Scientific Journal of Impact Factor(SJIF): 3.134 International Journal of Advance Engineering and Research Development Volume 2,Issue 3, March -2015 e-issn(o): 2348-4470 p-issn(p): 2348-6406 Sophisticated
More informationPower and Area Efficient CMOS Half Adder Using GDI Technique
Power and Area Efficient CMOS Half Adder Using GDI Technique 1 Ranbirjeet Kaur, 2 Rajesh Mehra 1 M.E.Scholar, 2 Associate Professor 1, 2, Department of Electronics & Communication Engineering NITTTR, Chandigarh,
More informationP. Sree latha, M. Arun kumar
International Journal of Scientific & Engineering Research Volume 9, Issue 3, March-2018 1 Performance Analysis of Comparator using Different Design Techniques P. Sree latha, M. Arun kumar Abstract - As
More informationADVANCES in NATURAL and APPLIED SCIENCES
ADVANCES in NATURAL and APPLIED SCIENCES ISSN: 1995-0772 Published BYAENSI Publication EISSN: 1998-1090 http://www.aensiweb.com/anas 2017 Special 11(6): pages 599-604 Open Access Journal Design A Full
More informationAnalysis of Different Full Adder Designs with Power using CMOS 130nm Technology
Analysis of Different Full Adder Designs with Power using CMOS 130nm Technology J. Kavitha 1, J. Satya Sai 2, G. Gowthami 3, K.Gopi 4, G.Shainy 5, K.Manvitha 6 1, 2, 3, 4, 5, St. Ann s College of Engineering
More informationDesign of Low Power CMOS Adder, Serf, Modified Serf Adder
P P Associate P P P P P Assistant P Associate P Assistant IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 2 Issue 7, July 2015. Design of Low Power CMOS Adder, Serf,
More informationA REVIEW OF THE 0.09 µm STANDARD FULL ADDERS
A REVIEW OF THE 0.09 µm STANDARD FULL ADDERS V. Vijay 1, J. Prathiba 2, S. Niranjan Reddy 3 and P. Praveen kumar 4 1 School of Electronics, Vignan University, Vadlamudi, Guntur vijayqiscet@gmail.com 2
More information