A7128 Data Sheet, high data rate Sub 1GHz Transceiver with 100K~2Mbps data rate

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1 Document Title A7128 Data Sheet, high data rate Sub 1GHz Transceiver with 100K~2Mbps data rate Revision History Rev. No. History Issue Date Remark 0.0 Initial issue. Sep., 2008 Preliminary 0.1 Add register tables Mar., 2009 Preliminary 0.2 Update technical data and timing diagram Jun., 2010 Preliminary, 0.3 Update 868MHz technical data Nov., 2010 Preliminary 0.4 Update min operation voltage to 2.0V Apr., 2011 Preliminary Update block diagram, ACK packet, App. circuit and correct Bit 7 of RX gain IV (1Dh). Modify tape and reel information and add Shenzhen office address. July, 2011 Preliminary 1.0 Update Fdev formula and setting. Mar Full production. Important Notice: AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such applications is understood to be fully at the risk of the customer. 1

2 Table of Contents 1. Typical Application General Description Features PIN Configuration PIN Description (I: Input, O: Output, I/O: Input or Output, G: Ground, D: Digital) Block Diagram Absolution Maximum Rating Electrical Specifications General Phase Locked Loop Transmitter Receiver Regulator...11 Digital IO DC characteristics Control Register Control Register Table Control Register Description Mode Register (Address: 00h) Mode Control Register (Address: 01h) Calibration Control Register (Address: 02h) FIFO Register I (Address: 03h) FIFO Register II (Address: 04h) FIFO DATA Register II (Address: 05h) ID DATA Register (Address: 06h) RC OSC Register I (Address: 07h) RC OSC Register II (Address: 08h) RC OSC Register III (Address: 09h) CKO Pin Control Register (Address: 0Ah) GIO1 Pin Control Register (Address: 0Bh) GIO2 Pin Control Register (Address: 0Ch) Data Rate Clock Register (Address: 0Dh) PLL Register I (Address: 0Eh) PLL Register II (Address: 0Fh) PLL Register III (Address: 10h) PLL Register IV (Address: 11h) PLL Register V (Address: 12h) Channel Group Register I (Address: 13h) Channel Group Register II (Address: 14h) TX Register I (Address: 15h) TX Register II (Address: 16h) Delay Register I (Address: 17h) Delay Register II (Address: 18h) RX Register (Address: 19h) RX Gain Register I (Address: 1Ah) RX Gain Register II (Address: 1Bh) RX Gain Register III (Address: 1Ch) RX Gain Register IV (Address: 1Dh) RSSI Threshold Register (Address: 1Eh) ADC Control Register (Address: 1Fh) Code Register I (Address: 20h) Code Register II (Address: 21h) Code Register III (Address: 22h) IF Calibration Register I (Address: 23h) IF Calibration Register II (Address: 24h) VCO Current Calibration Register (Address: 25h) VCO Bank Calibration Register I (Address: 26h) VCO Bank Calibration Register II (Address: 27h) VCO Deviation Calibration Register I (Address: 28h) VCO Deviation Calibration Register II (Address: 29h)

3 VCO Deviation Calibration Register III (Address: 2Ah) VCO Modulation Delay Register (Address: 2Bh) Battery Detect Register (Address: 2Ch) TX Test Register (Address: 2Dh) RX DEM Test Register I (Address: 2Eh) RX DEM Test Register II (Address: 2Fh) Charge Pump Current Register I (Address: 30h) Charge Pump Current Register II (Address: 31h) Crystal Test Register (Address: 32h) PLL Test Register (Address: 33h) VCO Test Register (Address: 34h) RF Analog Test Register (Address: 35h) IFAT Register (Address: 36h) Channel Selct Register (Address: 37h) VRB Register (Address: 38h) Data Rate Clock Register (Address: 39h) FCR Register (Address: 3Ah) ARD Register (Address: 3Bh) AFEP Register (Address: 3Ch) WMUX Register (Address: 3Dh) FCB Register (Address: 3Eh) SPI SPI Format SPI Timing Characteristic SPI Timing Chart Timing Chart of 3-wire SPI Timing Chart of 4-wire SPI Strobe Commands Strobe Command - Sleep Mode Strobe Command - ldle Mode Strobe Command - Standby Mode Strobe Command - PLL Mode Strobe Command - RX Mode Strobe Command - TX Mode Strobe Command FIFO Write Pointer Reset Strobe Command FIFO Read Pointer Reset Strobe Command Deep Sleep Mode Reset Command ID Accessing Command ID Write Command ID Read Command FIFO Accessing Command TX FIFO Write Command Rx FIFO Read Command State machine Key states Standby mode Sleep mode ldle mode PLL mode TX mode RX mode CAL mode Deep Sleep mode FIFO Mode Direct Mode Crystal Oscillator Circuit Use External Crystal Use External Clock System Clock Derive System Clock Data Rate Tranceiver Frequency

4 14.1 LO Frequency Setting IF Side Band Select Auto IF Exchange Fast Exchange AFC function Calibration Calibration Procedure Channel Group Function Ring Oscillator Calibration FIFO (First In First Out) TX Packet Format in FIFO mode Basic FIFO mode Advanced FIFO mode Bit Stream Process in FIFO mode Transmission Time Usage of TX and RX FIFO Easy FIFO Segment FIFO FIFO Extension ADC (Analog to Digital Converter) Temperature Measurement RSSI Measurement Auto RSSI measurement for TX Power Auto RSSI measurement for Background Power Carrier Detect External Voltage Measurement WOR Function WOR Function TWOR Function Battery Detect Auto-act and Auto-resend Basic FIFO plus auto-ack auto-resend Advanced FIFO plus auto-ack and auto-resend WTR Behavior during Auto-ack and Auot-resend Examples of Auto-ack and Auto-resend Application Circuit (Reference Only) MD7128-A90 (915MHz Band) MD7128-A80 (868MHz Band) MD7128-A40 (433MHz Band) Abbreviations Ordering Information Package Information Top Marking Information Reflow Profile Tape Reel Information Product Status

5 1. Typical Application Sub 1GHz ISM band Communication System Wireless audio/vedio streaming Sub 1GHz Remote Control Wireless Toy and Gaming Wireless Home Automation Wireless Alarm and Security 2. General Description A7128 is a high data rate and low cost Sub 1GHz ISM band wireless FSK/GFSK transceiver. It integrates high sensitivity receiver / MHz), high efficiency power amplifier (up to 10 dbm), frantional-n frequency synthesizer and baseband modem. In typical system, A7128 is used together with MCU (microcontroller) with very few external passive components. A7128 supports both FIFO mode and direct mode. In direct mode, A7128 supports recovery clock (CKO pin) to MCU for data latching. For packet handling, A7128 has built-in separated 64-bytes TX/RX FIFO (could be extended to 256 bytes) for data buffering and burst transmission, Auto-ack and Auto-resend scheme (max 15 cycles), dynamic FIFO length, CRC error detection, FEC error correction (1-bit data correction per code word), digital RSSI for clear channel assessment, data whitening for payload encryption / decryption, thermal sensor to monitor relative temperature, one channel 8-bits ADC for RSSI and external analog voltage conversion. Those functions are very easy to use while developing a wireless system. All features are integrated in a small QFN 4X4 20 pins package. Additional device features such as CRC filtering, Manchester encoding, carrier detect, preamble detect, frame sync of FIFO mode, AIF (Auto IF), AFC (Auto Frequency compensation), Auto calibration (VCO, IF Filter, RSSI), prgrammalbe IF Filter, multi Xtal sources, Xtal sharing are used to simplify system development and cost. A7128 supports programmable data rate is up to 2Mbps (100Kbps ~ 2Mbps) via 3-wire or 4-wire SPI.For power saving, A7128 supports deep sleep mode (no register retention), sleep mode (with register retention), idle mode, standby mode. For easy-to-use, A7128 has a unique SPI command set called Strobe command that are used to control A7128 s state machine. Based on Strobe commands (via SPI), from power saving, TX delivery, RX receiving, channel monitoring, frequency hopping to auto calibrations, MCU only needs to read/write A7128 s control registers and then issue Strobe commands for everything. For MCU feedback signal, A7128 has two general purpose I/O pins (GIO1 and GIO2) to inform MCU its status so that MCU could either use polling or interrupt scheme to do radio control. Interface between MCU and A7128 is digital, it leads a simple way to develop a wireless system as well as transmission status. 3. Features Small size (QFN4 X4, 20 pins). Support 433M / 868M / 915 MHz ISM band. Support FSK/GFSK modulation. Programmable data rate from 100kbps to 2Mbps. Low current consumption: RX 18.5mA, TX 36mA (at 10dBm output power). Low deep sleep current (0.1 ua). Low sleep current (2.0 ua). Programmable RF output power -20dBm ~ 10dBm. Programmable IF Filter 2MHz / 1MHz / 500KHz / 250KHz High 915MHz RX sensitivity (-88dBm@2Mbps, -96dBm@500Kbps, -101 dbm@ 100Kbps). On chip regulator, supports input voltage 2.0 ~ 3.6V. Easy to use u Support 3-wire or 4-wire SPI. u Unique Strobe command via SPI. u Change frequency channel by ONE register setting. u 8-bits Digital RSSI for clear channel indication. u Auto RSSI measurement. u Auto Calibrations (VCO, IF Filter, RSSI). u Auto IF function. u Auto Frequency Compensation. u Auto CRC Filtering. u Auto FEC by (7, 4) Hamming code (1 bit error correction / code word). u Auto-resend (max 15 cycles). u Auto-acknowlegaement. u Manchester encoding u Data Whitening for payload encryption and decryption. 5

6 u Separated 64 bytes RX and TX FIFO. u Dynamic FIFO Length u Easy FIFO / Segment FIFO / FIFO Extension (up to 256 bytes). u Support direct mode with recovery clock output to MCU. u Support FIFO mode with frame sync to MCU. Support low cost crystal (12 / 16MHz). Support low accuracy crystal within ± 50 ppm. Support crystal sharing, (1 / 2 / 4 / 8MHz) to MCU. Fast settling time 110 us synthesizer for frequency hopping system. Built-in thermal sensor to monitor relative ambient temperature. Built-in 1 channel 8-bits ADC to convert external voltage (0.3 V ~ 1.5 V). Built-in Battery Detector. 4. PIN Configuration CP GND_PLL VDD_PLL XI XO VDD_A REGI CKO GIO2 GIO1 Figure 4.1 A7128 QFN 4x4 Package Top View 6

7 5. PIN Description (I: Input, O: Output, I/O: Input or Output, G: Ground, D: Digital) Pin No. Symbol I/O Function Description 1 BP_RSSI I/O I: ADC input. O: RSSI bypass. Connect to bypass capacitor. 2 BP_BG O Band-gap bypass. Connect to bypass capacitor. 3 RFI I RF input. Connect to matching circuit. 4 RFO O RF output. Connect to matching circuit. 5 VDD_VCO I VCO supply voltage input. 6 CP O Charge-pump output. Connect to loop filter. 7 GND_PLL O PLL ground pin. 8 VDD_PLL O PLL supply voltage input. 9 XI I Crystal oscillator input. Connect to tank capacitor. 10 XO O Crystal oscillator output. Connect to tank capacitor. 11 SCS DI SPI chip select input. 12 SCK DI SPI clock input. 13 VDD_D O Digital supply voltage output. Connect to bypass capacitor. 14 SDIO DI/O SPI data IO. 15 GND G Ground. 16 GIO1 DI/O Multi-function IO 1 / SPI data output. 17 GIO2 DI/O Multi-function IO 2 / SPI data output. 18 CKO DO Multi-function clock output. 19 REGI I Regulator input. Connect to VDD supply. 20 VDD_A O Analog supply voltage output. Connect to bypass capacitor. Back side plate G Ground. Back side plate shall be well-solder to ground; otherwise, it will impact RF performance. 7

8 6. Block Diagram Figure 6.1 A7128 Block Diagram 8

9 7. Absolution Maximum Rating Parameter With respect to Rating Unit Supply voltage range (VDD) GND -0.3 ~ 3.6 V Other I/O pins range GND -0.3 ~ VDD+0.3 V Maximum input RF level 10 dbm Storage Temperature range -55 ~ 125 C ESD Rating HBM 1) ±2K V ESD Rating MM 1) ±100 V *Stresses above those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. *Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-STD-883F Method MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A. *Device is Moisture Sensitivity Level III (MSL 3). *Pin 4 (RFO) is -2KV and -100V of HBM and MM respectively. 9

10 8. Electrical Specifications (Ta=25, VDD=3.3V, data rate= 500Kbps, F XTAL =16MHz, On Chip Regulator = 1.8V, with Matching Network and low and high pass filter, unless otherwise noted.) Parameter Description Minimum Typical Maximum Unit General Operating Temperature C Supply Voltage (VDD) Regulator supply input V Current Consumption Deep Sleep 0.1 (1*) ua (no data retention) Sleep 2.0 (1*) ua (Regulator on) Idle Mode 0.2 (1*) ma Standby Mode (XOSC on, 2.9 ma Clock generator on) PLL Mode 10.5 ma RX Mode 18.5 ma TX Mode (@10dBm output) 36 ma TX Mode (@6dBm output) 28 ma TX Mode (@1dBm output) 22 ma TX Mode (@-9dBm output) 18 ma TX Mode (@-20dBm output) 15.5 ma Phase Locked Loop XTAL Settling Time (2*) Idle to standby 1 ms XTAL Frequency (F XTAL) Recommend Cload = 18pF 12, 16 MHz XTAL ESR 80 Ohm XTAL Tolerance including initial tolerance, aging and temperature drift ± 50 ppm VCO Operation Frequency MHz Phase Noise 100K 90 MHz 500K 110 MHz 2M 115 MHz PLL Settling Time (3*) 30 Standby to Loop Filter by 560pF / 1K / 10nF ms Transmitter TX Power Control Range With low pass filter dbm Data rate 100K 500K 2M bps Frequency Deviation 2Mbps 500 KHz 1Mbps 372 KHz 500Kbps KHz 100Kbps 38.7 KHz Out Band Spurious Emission (4*) 30MHz~1GHz -36 dbm 1GHz~12.75GHz GHz~ 1.9GHz GHz~ 5.3GHz -54 TX Ready Time (5*) LO Fixed (PLL to TX) 90 Loop Filter by 560pF / 1K / 10nF Hopping (plus PLL settling) ms Sleep to TX (5*) 1.1 ms Receiver IF Frequency (F IF) > 500Kbps 2 MHz 10

11 < = 500Kbps 0.5 MHz Spurious Emission (5*) 915MHz % 2Mbps (Fdev = ± 500KHz) -88 dbm 1Mbps (Fdev = ± 250KHz) -93 dbm 500Kbps (Fdev = ± 180KHz) -96 dbm 100kbps (Fdev = ± 180KHz) -101 dbm 868MHz % 500Kbps (Fdev = ± 180KHz) -96 dbm 100kbps (Fdev = ± 90KHz) -101 dbm 433MHz % 2Mbps (Fdev = ± 500KHz) -85 dbm 500Kbps (Fdev = ± 183KHz) -93 dbm Maximum Operating Input input (BER=0.1%) 10 dbm Interference (6*) Co-Channel (C/I 0) 11.5 dbc ±0.5MHz -4.5 dbc ±1MHz dbc ±2MHz dbc ±5MHz dbc ±10MHz -44 dbc Image (C/I IM) -16 dbc 30MHz~1GHz -57 dbm 1GHz~12.75GHz -47 RSSI input dbm RX Settling Time Standby to RX 100 Loop Filter by 560pF / 1K / 10nF Sleep to RX 1.1 ms Regulator Regulator settling time Sleep to idle 40 Pin 2 connected to 1.5nF Band-gap reference voltage 1.25 V Regulator output voltage V Digital IO DC characteristics High Level Input Voltage (V IH) 0.8*VDD VDD V Low Level Input Voltage (V IL) 0 0.2*VDD V High Level Output Voltage (V OH= -0.5mA VDD-0.4 VDD V Low Level Output Voltage (V OL= 0.5mA V Note 1: When digital I/O pins are configed as input, those pins shall NOT be floating but pull either high or low (SCS shall be pulled high only); otherwise, more leakage current will be induced in all operation modes. Note 2: Refer to Delay Register II (0x18) to set up crystal settling delay. Note 3: Refer to Delay Register I (0x17) to set up PDL (PLL settling delay). Note 4: With external RF filter that provides minimum 17dB of attenuation in the band: 30MHz ~ 2GHz and 3GHz ~12.75GHz. Note 5: Refer to Delay Register I (0x17) to set up TDL delay. Note 6: The power level of wanted signal is set at sensitivity +3dB. The modulation data for wanted signal and interferer is PN9 and PN15, respectively. Channel spacing is 2MHz. 11

12 9. Control Register A7128 has totally built-in 62 control registers that cover all radio control. MCU can access those control registers via 3-wire or 4-wire SPI (Support max. SPI data rate up to 10 Mbps). User can refer to chapter 10 for details of SPI interface. A7128 is simply controlled by registers and outputs its status to MCU by GIO1 and GIO2 pins. 9.1 Control Register Table Address / Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h W RESETN RESETN RESETN RESETN RESETN RESETN RESETN RESETN Mode R - FECF CRCF CER XER PLLER TRSR TRER 01h W DDPC ARSSI AIF DFCD WORE FMT FMS ADCM Mode control R DDPC ARSSI AIF CD WORE FMT FMS ADCM 02h Calc R/W VCC VBC VDC FBC RSSC 03h W FEP7 FEP6 FEP5 FEP4 FEP3 FEP2 FEP1 FEP0 FIFO I R LENF7 LENF6 LENF5 LENF4 LENF3 LENF2 LENF1 LENF0 04h FIFO II W FPM1 FPM0 PSA5 PSA4 PSA3 PSA2 PSA1 PSA0 05h FIFO Data R/W FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0 06h ID Data R/W ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 07h W WOR_SL7 WOR_SL6 WOR_SL5 WOR_SL4 WOR_SL3 WOR_SL2 WOR_SL1 WOR_SL0 RC OSC I R - - RCOC5 RCOC4 RCOC3 RCOC2 RCOC1 RCOC0 08h RC OSC II W WOR_SL9 WOR_SL8 WOR_AC5 WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1 WOR_AC0 09h RC OSC III W BBCKS1 BBCKS0 - - CALWC RCOSC_E TSEL TWOR_E 0Ah CKO Pin W ECKOE CKOS3 CKOS2 CKOS1 CKOS0 CKOI CKOE SCKI 0Bh GIO1 Pin I W - - GIO1S3 GIOS2 GIO1S1 GIO1S0 GIO1I GIO1OE 0Ch GIO2 Pin II W - - GIO2S3 GIO2S2 GIO2S1 GIO2S0 GIO2I GIO2OE 0Dh W IFS BWS GRC3 GRC1 GRC1 GRC0 CGS XS Data Rate Clock R IFS BWS GRC3 GRC2 GRC1 GRC Eh PLL I R/W CHN7 CHN6 CHN5 CHN4 CHN3 CHN2 CHN1 CHN0 0Fh W DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 BIP8 PLL II R DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 IP8 10h W BIP7 BIP6 BIP5 BIP4 BIP3 BIP2 BIP1 BIP0 PLL III R IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 11h W BFP15 BFP14 BFP13 BFP12 BFP11 BFP10 BFP9 BFP8 PLL IV R -FP15 AC14-FP14 AC13-FP13 AC12-FP12 AC11-FP11 AC10-FP10 AC9-FP9 AC8-FP8 12h W BFP7 BFP6 BFP5 BFP4 BFP3 BFP2 BFP1 BFP0 PLL V R AC7-FP7 AC6-FP6 AC5-FP5 AC4-FP4 AC3-FP3 AC2-FP2 AC1-FP1 AC0-FP0 13h Channel Group I R/W CHGL7 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 CHGL1 CHGL0 14h Channel Group II R/W CHGH7 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 CHGH1 CHGH0 15h TX I W GDR GF TMDE TXDI TME FDP2 FDP1 FDP0 16h TX II W FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 17h Delay I W DPR2 DPR1 DPR0 TDL1 TDL0 PDL2 PDL1 PDL0 18h Delay II W WSEL2 WSEL1 WSEL0 RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0 12

13 19h RX W - RXSM1 RXSM0 AFC RXDI DMG DMS ULS 1Ah RX Gain I R/W CRCINV CRCDNP VGC IGS MGS1 MGS0 LGS1 LGS0 1Bh R RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 RX Gain II W RAW LMCS CSXTL4 CSXTL3 CSXTL2 CSXTL1 CSXTL0 INTXC 1Ch R RL7 RL6 RL5 RL4 RL3 RL2 RL1 RL0 RX Gain III W EDRL HECS STS RGC1 RGC0 VRPL1 VRPL0 INTRPC 1Dh RX Gain IV W ERSSM AVSEL1 AVSEL0 MVSEL1 MVSEL0 MHC LHC NS1 1Eh W RTH7 RTH6 RTH5 RTH4 RTH3 RTH2 RTH1 RTH0 RSSI Threshold R ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 1Fh ADC Control W RSM1 RSM0 - RADC FSARS XADS RSS CDM 20h Code I W MCS WHTS FECS CRCS IDL1 IDL0 PML1 PML0 21h Code II W DCL2 DCL1 DCL0 ETH2 ETH1 ETH0 PMD1 PMD0 22h Code III W DCH WS6 WS5 WS4 WS3 WS2 WS1 WS0 23h W - RMP1 RMP0 MFBS MFB3 MFB2 MFB1 MFB0 IF Calibration I R FBCF FB3 FB2 FB1 FB0 24h IF Calibration II W - TRT2 TRT1 TRT0 ASMV2 ASMV1 ASMV0 AMVS R FCD4 FCD3 FCD2 FCD1 FCD0 25h W - VCRLS VBS MVCS VCOC3 VCOC2 VCOC1 VCOC0 VCO current Calibration R VCCF VCB3 VCB2 VCB1 VCB0 26h W DDC1 DDC0 MDAGS CWS MVBS MVB2 MVB1 MVB0 VCO band Calibration I R VBCF VB2 VB1 VB0 27h W MDAG7 MDAG6 MDAG5 MDAG4 MDAG3 MDAG2 MDAG1 MDAG0 VCO band Calibration II R ADAG7 ADAG6 ADAG5 ADAG4 ADAG3 ADAG2 ADAG1 ADAG0 28h VCO deviation W DEVS3 DEVS2 DEVS1 DEVS0 DAMR_M VMTE_M VMS_M MSEL Calibration I R DEVA7 DEVA6 DEVA5 DEVA4 DEVA3 DEVA2 DEVA1 DEVA0 29h VCO deviation W MVDS MDEV6 MDEV5 MDEV4 MDEV3 MDEV2 MDEV1 MDEV0 Calibration II R ADEV7 ADEV6 ADEV5 ADEV4 ADEV3 ADEV2 ADEV1 ADEV0 2Ah VCO deviation W VMG7 VMG6 VMG5 VMG4 VMG3 VMG2 VMG1 VMG0 Calibration III 2Bh VCO modulation W DMV1 DMV0 DEVFD2 DEVFD1 DEVFD0 DEVD2 DEVD1 DEVD0 Delay 2Ch W ECKS RGV1 RGV0 QDS BVT2 BVT1 BVT0 BD_E Battery detect R - RGV1 RGV0 BDF BVT2 BVT1 BVT0 BD_E 2Dh TX test W ASKS PAC1 PAC0 TDC1 TDC0 TBG2 TBG1 TBG0 2Eh Rx DEM test I 2Fh Rx DEM test II 30h Charge Pump Current I 31h Charge Pump Current II W DMT DCM1 DCM0 MLP1 MLP0 SLF2 SLF1 SLF0 W DCV7 DCV6 DCV5 DCV4 DCV3 DCV2 DCV1 DCV0 W CPM3 CPM2 CPM1 CPM0 CPT3 CPT2 CPT1 CPT0 W CPTX3 CPTX2 CPTX1 CPTX0 CPRX3 CPRX2 CPRX1 CPRX0 13

14 32h Crystal test W LVR RGS MD1 MD0 DBD XCC XCP1 XCP0 33h PLL test W SDMS CPS PRRC1 PRRC0 PRIC1 PRIC0 SDPW NSDO 34h VCO test W DEVGD2 DEVGD1 DEVGD0 LOB1 LOB0 DIVRF1 DIVRF0 VCBS 35h RF Analog test W ASDAR MDEN OLM CPH CPCS RFT2 RFT1 RFT0 36h IFAT W IGFI2 IGFI1 IGFI0 IGFQ2 IGFQ1 IGFQ0 AGCT LIMC 37h Channel Select W CHI3 CHI2 CHI1 CHI0 CHD3 CHD2 CHD1 CHD0 38h VRB W VTRB3 VTRB2 VTRB1 VTRB0 VMRB3 VMRB2 VMRB1 VMRB0 39h Data rate W SDR7 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 3Ah R ARTEF VPOAK RCR3 RCR2 RCR1 RCR0 EAK EAR FCR W FCL1 FCL0 ARC3 ARC2 ARC1 ARC0 EAK EAR 3Bh ARD W ARD7 ARD6 ARD5 ARD4 ARD3 ARD2 ARD1 ARD0 3Ch R 0 0 EARTS2 EARTS1 EARTS0 SID2 SID1 SID0 AFEP W EAF SPSS ACKFEP5 ACKFEP4 ACKFEP3 ACKFEP2 ACKFEP1 ACKFEP0 3Dh WMUX R/W WMUXH7 WMUXH6 WMUXH5 WMUXH4 WMUXL3 WMUXL2 WMUXL1 WMUXL0 3Eh FCB R/W FCB7 FCB6 FCB5 FCB4 FCB3 FCB2 FCB1 FCB0 Legend: - = unimplemented 14

15 9.2 Control Register Description Mode Register (Address: 00h) R HCF FECF CRCF CER XER PLLER TRSR TRER Name W RESETN RESETN RESETN RESETN RESETN RESETN RESETN RESETN Reset RESETN: Write to this register by 0x00 to issue reset command, then it is auto clear HCF: HEC Flag. (Clear by any Strobe command.) HCF is CRC-8 result of Header (FCB + DFL) and shows its integirity. (Refer to chaper 16 for details.) DFL is dynamic FIFO header. [0]: HCF pass. [1]: HCF error. FECF: FEC flag. (FECF is read clear.) [0]: FEC pass. [1]: FEC error. CRCF: CRC flag. (CRCF is read clear.) [0]: CRC pass. [1]: CRC error. CER: Chip Status. (Read only) [0]: Chip is disabled. [1]: Chip is enabled. XER: Xtal Status. (Read only) [0]: Crystal oscillator is disabled. [1]: Crystal oscillator is enabled. PLLE: PLL Status. (Read only) [0]: PLL is disabled. [1]: PLL is enabled after PLL strobe command. TRER: TRX Status I. (Read only) [0]: TRX is disabled. [1]: TRX is enabled. TRSR: TRX Status II. (Read only) [0]: RX mode. [1]: TX mode. Serviceable when TRER=1 (TRX is enable) Mode Control Register (Address: 01h) R DDPC ARSSI AIF CD WORE FMT FMS ADCM Name W DDPC ARSSI AIF DFCD WORE FMT FMS ADCM Reset DDPC (Direct mode data pin control): Direct mode modem data can be accessed via SDIO pin. [0]: Disable. [1]: Enable. ARSSI: Auto RSSI measurement enable whenever in RX mode. [0]: Disable. [1]: Enable. AIF: Auto IF. [0]: Disable. [1]: Enable. RF LO frequency will auto offset one IF frequency whenever in RX mode. CD: Carrier detector (Read only). [0]: Input power below threshold. [1]: Input power above threshold. DFCD: Data Filter by CD : The received packet would be filtered if the input power level is below RTH (1Eh). [0]: Disable. [1]: Enable. WORE: Reserved for internal usage, shall be set to [0]. FMT: Reserved for internal usage only. Shall be set to [0]. FMS: Direct/FIFO mode select. [0]: Direct mode. [1]: FIFO mode. ADCM: ADC measurement (Auto clear when done). [0]: Disable. [1]: Enable. 15

16 ADCM Standby mode RX mode [0] Disable ADC Disable ADC [1] Measure temperature or external voltage Measure RSSI, carrier detect Refer to chapter 17 for details Calibration Control Register (Address: 02h) Name R/W VCC VBC VDC FBC RSSC Reset VCC: VCO Current calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. VBC: VCO Bank calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. VDC: VCO Deviation calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. FBC: IF Filter Bank calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. RSSC: RSSI calibration enable (Auto clear when done). [0]: Disable. [1]: Enable FIFO Register I (Address: 03h) Name W FEP7 FEP6 FEP5 FEP4 FEP3 FEP2 FEP1 FEP0 R LENF7 LENF6 LEN5 LENF4 LENF3 LENF2 LENF1 LENF0 Reset FEP [7:0]: FIFO End Pointer for TX FIFO and Rx FIFO. Refer to chapter 16 for details. LENF [7:0]: Received FIFO Length = LENF + 1. Used in dynamic length mode. (EDRL = 1). Refer to chapter 16 for details FIFO Register II (Address: 04h) Name W FPM1 FPM0 PSA5 PSA4 PSA3 PSA2 PSA1 PSA0 Reset FPM [1:0]: FIFO Pointer Margin. Used in FIFO extension mode. PSA [5:0]: Used for Segment FIFO. Used in FIFO segment mode. Refer to chapter 16 for details FIFO DATA Register II (Address: 05h) Name W TX-FIFO[7:0] R/W RX-FIFO[7:0] Reset

17 FIFO [7:0]: TX FIFO / RX FIFO TX FIFO and RX FIFO share the same address (05h). TX FIFO and RX FIFO have independent physical 64 Bytes. Refer to chapter 16 for details ID DATA Register (Address: 06h) Name R/W ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Reset ID [7:0]: ID data. (R/W). Programmble to 2 / 4 / 6 / 8 bytes according to IDL[1:0] (20h). Refer to section 10.6 and chapter 16 for details RC OSC Register I (Address: 07h) R -- CALWR RCOC5 RCOC4 RCOC3 RCOC2 RCOC1 RCOC0 Name W WOR_SL7 WOR_SL6 WOR_SL5 WOR_SL4 WOR_SL3 WOR_SL2 WOR_SL1 WOR_SL0 Reset CALWR: RC Calibration Flag. [0]: Calibration finished. [1]: calibration underway. RCOC [5:0]: RC Oscillator Calibration result (read only). WOR_SL [7:0]: Reserved for internal usage RC OSC Register II (Address: 08h) Name W WOR_SL9 WOR_SL8 WOR_AC5 WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1 WOR_AC0 Reset WOR_AC [5:0]: Reserved for internal usage. WOR_SL [9:8]: Reserved for internal usage RC OSC Register III (Address: 09h) Name W BBCKS1 BBCKS0 RCOT1 RCOT0 CALWC RCOSC_E TSEL TWOR_E Reset BBCKS [1:0]: Clock select for digital block. Recommend BBCKS = [00]. [00]: F SYCK. [01]: F SYCK / 2. [10]: F SYCK / 4. [11]: F SYCK / 8. RCOSC_E: RC Oscillator Enable. [0]: Disable. [1]: Enable. RCOT[1:0]: RC OSC current select. [00]: 240nA [01]: 280nA [10]: 320nA [11]: 360nA TSEL: Reserved for internal usage TWOR_E: Reserved for internal usage. CALWC: RC Oscillator Calibration Enable. [0]: Disable. [1]: Enable CKO Pin Control Register (Address: 0Ah) 17

18 Name W ECKOE CKOS3 CKOS2 CKOS1 CKOS0 CKOI CKOE SCKI Reset ECKOE: External Clock Output Enable for CKOS [3:0]= [0100] ~ [0111]. [0]: Disable. [1]: Enable. CKOS [3:0]: CKO pin output select. [0000]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode. [0001]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode. [0010]: FPF (FIFO pointer flag for FIFO extension). [0011]: Logic OR gate by EOP, EOVBC, EOFBC, EOVCC, EOVDC and RSSC_OK. (Internal usage only). [0100]: F SYCK. [0101]: F SYCK / 2. [0110]: F SYCK / 4. [0111]: F SYCK / 8. [1000]: WCK (Internal usage only). [1001]: PF8M (Internal usage only). [1010]: ROSC (Internal usage only). [1011]: EOADC (Internal usage only). [1100]: OKADCN (Internal usage only). [1101]: VPOAK. [111x]: Reserved. CKOI: CKO pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. CKOE: CKO pin Output Enable. [0]: High Z. [1]: Enable. SCKI: SPI clock input invert. [0]: Non-inverted input. [1]: Inverted input GIO1 Pin Control Register (Address: 0Bh) Name W VPM VPW GIO1S3 GIO1S2 GIO1S1 GIO1S0 GIO1I GIO1OE Reset VPM: Valid Packet (VPOAK) Mode select. [0]: event trigger. [1]: pulse trigger. VPW: VPOAK pulse width select. [0]: 20u. [1]: 40u. GIO1S [3:0]: GIO1 pin function select. GIO1S [3:0] TX state RX state [0000] WTR (Wait until TX or RX finished) [0001] EOAC (end of access code) FSYNC(frame sync) [0010] TMEO(TX modulation enable) CD(carrier detect) [0011] Preamble Detect Output (PMDO) [0100] MCU wakeup signal (TWOR) [0101] In phase demodulator input(dmii) [0110] SDO ( 4 wires SPI data out) [0111] TRXD In/Out ( Direct mode ) [1000] RXD ( Direct mode ) [1001] TXD ( Direct mode ) [1010] PDN_RX [1011] External FSYNC input in RX direct mode * [1100] INC [1101] FPF(FIFO pointer flag for FIFO extension) [1110] VPOAK (Valid Packet or Auto-resend OK Ouput) [1111] FMTDO (FIFO mode TX Data Output testing) GIO1I: GIO1 pin output signal invert. 18

19 [0]: Non-inverted output. [1]: Inverted output. GIO1OE: GIO1pin output enable. Recommend GIO1OE = [1] [0]: High Z. [1]: Enable GIO2 Pin Control Register (Address: 0Ch) Name W GIO2S3 GIO2S2 GIO2S1 GIO2S0 GIO2I GIO2OE Reset GIO2S [3:0]: GIO2 pin function select. GIO2S [3:0] TX state RX state [0000] WTR (Wait until TX or RX finished) [0001] EOAC (end of access code) FSYNC(frame sync) [0010] TMEO(TX modulation enable) CD(carrier detect) [0011] Preamble Detect Output (PMDO) [0100] MCU wakeup signal (TWOR) [0101] Quadrature phase demodulator output (DMIQ). [0110] SDO ( 4 wires SPI data out) [0111] TRXD In/Out ( Direct mode ) [1000] RXD ( Direct mode ) [1001] TXD ( Direct mode ) [1010] PDN_TX [1011] External FSYNC input in RX direct mode * [1100] DEC [1101] FPF(FIFO pointer flag for FIFO extension) [1110] VPOAK (Valid Packet or Auto-resend OK Ouput) [1111] FMRDI. (FIFO mode RX input for testing) GIO2I: GIO2 pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. GIO2OE: GIO1pin output enable. Recommend GIO2OE = [1] [0]: High Z. [1]: Enable. TX Mode (disable Auto-resend, EAR=0). RX Mode (disable Auto-ack, EAK =0). 19

20 Note1, If Auto-resend is enabled (EAR = 1), WTR behavior is different while output to GIO1 and GIO2. Note2, If Auto-ack is enabled (EAK = 1), WTR behavior is different while output to GIO1 and GIO2. Note3, VPOAK s behavior is controlled by VPM (0Bh) and VPW (0Bh). Refer to chapter 20 for details Data Rate Clock Register (Address: 0Dh) R IFS BWS GRC3 GRC2 GRC1 GRC Name W IFS BWS GRC3 GRC2 GRC1 GRC0 CGS XS Reset IFS: IF Frequency Select. [0]: 500KHz. [1]: 2MHz. BWS: Bandwidth Select. [1]: 2MHz when IFS =1. [1]: 500KHz when IFS =0. [0]: 1MHz when IFS =1. [0]: 250KHz when IFS =0. GRC [3:0]: Generator Reference Counter. Clock generation reference = F CRYSTAL / (GRC+1). GRC is max 15. Refer to chapter 13 for details. CGS: Clock generator enable. Shall be set to [1]. [0]: Disable. [1]: Enable. XS: Crystal oscillator select. Recommend XS = [1] [0]: Use external clock. [1]: Use external crystal PLL Register I (Address: 0Eh) Name R/W CHN7 CHN6 CHN5 CHN4 CHN3 CHN2 CHN1 CHN0 Reset CHN [7:0]: RF LO channel number. Refer to chapter 14 for details. 20

21 PLL Register II (Address: 0Fh) R DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 IP8 Name W DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 BIP8 Reset DBL: Crystal frequency doubler enable. [0]: Disable. F XREF = F XTAL. [1]: Enable. F XREF =2 * F XTAL. RRC [1:0]: RF PLL reference counter setting. RRC is the R-counter for the PLL comparison frequency F PFD FXTAL = ( DBL + 1) RRC[1: 0] + 1 CHR [3:0]: PLL channel step setting. Refer to chapter 14 for details PLL Register III (Address: 10h) R IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 Name W BIP7 BIP6 BIP5 BIP4 BIP3 BIP2 BIP1 BIP0 Reset BIP [8:0]: (write) LO base frequency integer part setting. BIP [8:0] are from address (0Fh) and (10h), IP [8:0]: (read) LO frequency integer part value. IP [8:0] are from address (0Fh) and (10h), The wanted RF formula F LO_BASE 1 BFP[15 : 0] = FPFD ( BIP[8: 0] + ) 16 n 2 1 F = ( DBL + 1) ( BIP[8: 0] n RRC[1: 0] + 1 where f dev XTAL + BFP[15 : 0] ) 16 2 is the wanted TX frequency deviation. Where n = 2 for MD = [10] or [11], 868M / 915MHz band Where n = 4 for MD = [01], 433M band Where n = 6 for MD = [00], 315MHz band MD[1:0] is located at address 32h [Bit12, Bit8]. DBL and RRC[1:0] are located at address 0Fh. Refer to chapter 14 for details PLL Register IV (Address: 11h) R AC15/FP15 AC14/FP14 AC13/FP13 AC12/P12 AC11/ FP11 AC10/FP10 AC9/FP9 AC8/FP8 Name W BFP15 BFP14 BFP13 BFP12 BFP11 BFP10 BFP9 BFP8 Reset PLL Register V (Address: 12h) Name R AC7/FP7 AC6/FP6 AC5/FP5 AC4/FP4 AC3/FP3 AC2/FP2 AC1/FP1 AC0/FP0 21

22 W BFP7 BFP6 BFP5 BFP4 BFP3 BFP2 BFP1 BFP0 Reset BFP [15:0]: LO base frequency fractional part setting. (BFP = [0000] is forbidden.) BFP [15:0] are from address (11h) and (12h), AC [14:0] (Read): Frequency compensation value if AFC (19h) =1. Refer to chapter 14 for details Channel Group Register I (Address: 13h) Name R/W CHGL7 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 CHGL1 CHGL0 Reset CHGL [7:0]: PLL channel group low boundary setting. Refer to chapter 15 for details Channel Group Register II (Address: 14h) Name R/W CHGH7 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 CHGH1 CHGH0 Reset CHGH [7:0]: PLL channel group high boundary setting. Used for VCO calibration. PLL frequency is divided into 3 groups: Channel Group1 0 ~ CHGL-1 Group2 CHGL ~ CHGH-1 Group3 CHGH ~ 255 Note 1. Refer to chapter 15 and App Note (reference code) for details 2. Each group needs its own VCO current, bank and deviation calibration. 3. Use the same calibration value for the frequency in the same group TX Register I (Address: 15h) Name W GDR GF TMDE TXDI TME FDP2 FDP1 FDP0 Reset GDR: Gaussian Filter Oversampling Rate Select. [0]: BT= 0.7 [1]: BT= 0.5 GF: Gaussian Filter Select. [0]: Disable. [1]: Enable. TMDE: TX Modulation Enable for VCO Modulation. [0]: Disable. [1]: Enable. TXDI: TX data invert. Recommend TXDI = [0]. [0]: Non-invert. [1]: Invert. TME: TX modulation enable. [0]: Disable. [1]: Enable. FDP [2:0]: Frequency deviation power setting. Recommend FDP = [111]. 22

23 TX Register II (Address: 16h) Name W FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 Reset FD [7:0]: TX Frequency deviation setting. For both Gaussian filter is on (GS =1) or off(gs = 0): dev 1 = f n f PFD 2 FD[7 : 0] ( FDP[2:0] -1) f (unit: Hz) where dev is the wanted TX frequency deviation. Where n = 2 for MD = [10] or [11], 868M / 915MHz band Where n = 4 for MD = [01], 433M band Where n = 6 for MD = [00], 315MHz band MD[1:0] is located at address 32h [Bit12, Bit8]. FDP[2:0] is located at address 15h [Bit2, Bit1, Bit0] Freq. Band Data Rate FD[7:0] (16h) 915MHz FDP[2:0] (15h) MD[1:0] (32h) 2Mbps 0x40 [111] [10] 500 1Mbps 0x20 [111] [10] Kbps 0x17 [111] [10] Fdev (KHz) (result) 100Kbps 0x17 [111] [10] Freq. Band Data Rate FD[7:0] (16h) FDP[2:0] (15h) MD[1:0] (32h) Fdev (KHz) (result) 868MHz 500Kbps 0x17 [111] [10] Kbps 0x17 [110] [10] Freq. Band Data Rate FD[7:0] (16h) 433MHz FDP[2:0] (15h) MD[1:0] (32h) 2Mbps 0x80 [111] [01] 500 1Mbps 0x40 [111] [01] Kbps 0x2F [111] [01] Fdev (KHz) (result) 100Kbps 0x2F [111] [01] Delay Register I (Address: 17h) Name W DPR2 DPR1 DPR0 TDL1 TDL0 PDL2 PDL1 PDL0 Reset DPR [2:0]: Delay scale. Recommend DPR = [000]. TDL [1:0]: Delay for TRX settling from WPLL to TX/RX. Delay= 20 * (TDL [1:0]+1)*(DPR [2:0]+1) us. DPR [2:0] TDL [1:0] TX settling Note us us us Recommend us PDL [2:0]: Delay for TX settling from PLL to WPLL. Delay= * (PDL [2:0]+1)*(DPR [1:0]+1) us. 23

24 DPR [2:0] PDL [2:0] PLL settling PLL settling Note (LO freq. fixed) (LO freq changed) us 50 us us 70 us Recommend us 90 us us 110 us GIO 1 Pin (WTR) RFO Pin PLL Mode TX Strobe TX Mode Packet (Preamble + ID + Payload) PDL TDL Delay Register II (Address: 18h) Name W WSEL2 WSEL1 WSEL0 RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0 Reset WSEL [2:0]: XTAL settling delay setting (200us ~ 2.5ms). Recommend WSEL = [010]. [000]: 200us. [001]: 400us. [010]: 600us, [011]: 800us. [100]: 1ms. [101]: 1.5ms. [110]: 2ms. [111]: 2.5ms. Crystal Oscillator GIO1 Pin (WTR) Id le mode 350 us WSEL TX or RX mode RFO Pin PDL TDL Packet (Preamble + ID + Payload) RSSC_D [1:0]: RSSI calibration switching time (10us ~ 40us). Recommend RSSC_D = [00]. [00]: 10us. [01]: 20us. [10]: 30us. [11]: 40us. RS_DLY [2:0]: RSSI measurement delay (10us ~ 80us). Recommend RS_DLY = [010]. [000]: 10us. [001]: 20us. [010]: 30us. [011]: 40us. [100]: 50us. [101]: 60us. [110]: 70us. [111]: 80us RX Register (Address: 19h) Name W MSCRC RXSM1 RXSM0 AFC RXDI DMG DMS ULS Reset MSCRC: Mask Select CRC (CRC Filtering Enable). [0]: Disable. [1]: Enable. RXSM1: RX clock recovery circuit moving average filter length. Recommend RXSM1 = [1]. [0]: 4 bits. [1]: 8 bits. RXSM0: Demodulator LPF Bandwidth Select. Recommend RXSM0 = [1]. [0]: 2MHz. [1]: 1MHz. AFC: Auto Frequency compensation. [0]: Disable. [1]: Enable. Refer to section 14.4 for details. RXDI: RX data output invert. Recommend RXDI = [0]. 24

25 [0]: Non-inverted output. [1]: Inverted output. DMG: Demodulator Gain Select. [0]: x 1. [1]: x 3. Recommend DMG = [0] for data rate > 250Kbps. Recommend DMG = [1] for data rate 250Kbps. DMS: Reserved. Recommend DMS=[0] ULS: RX Up/Low side band select. Recommend ULS = [0]. [0]: Up side band, [1]: Low side band. Refer to section 14.2 for details RX Gain Register I (Address: 1Ah) Name R/W CRCINV CRCDNP VGC IGS MGS1 MGS0 LGS1 LGS0 Reset CRCINV: CRC Inverted Select. [0]: disable. [1]: enable If CRCS = 1 (CRC enable), CRC (two bytes) is processing in 1 s complement.) CRCDNP: CRC Mode Select. [0]: CRC-CCITT (X 16 + X 12 + X 5 + 1). [1]: CRC-DNP (X 16 + X 13 + X 12 + X 11 + X 10 + X 8 + X 6 + X 5 + X 2 + 1). VGC: Auto LNA Gain Control Select. [0]: Disable. [1]: Enable. IGS: IFA Attenuation Select. Recommend IGS = [1]. [0]: 0 db. [1]: -6dB. MGS [1:0]: Mixer Gain Attenuation select. Recommend MGS = [11]. [00]: 0dB. [01]: -6dB. [10]: -12dB. [11]: -18dB. LGS [1:0]: Reserved. Recommend LGS = [11] RX Gain Register II (Address: 1Bh) Name R RHC7 RHC6 RHC5 RHC4 RHC3 RHC2 RHC1 RHC0 W RAW LMCS CSXTL4 CSXTL3 CSXTL2 CSXTL1 CSXTL0 INTXC Reset RHC [7:0]: RSSI Calibration High Threshold (read only). RAW: Raw Data Output Select. Recommend RAW = [1]. [0]: latch data output. [1]: RAW data output. LMCS: Limiter DC offset corner selection. Recommend LMCS = [0]. [0]: 500k mode. [1]: 2MHz mode. CSXTAL[4:0]: On-chip Crystal loading select. Recommend CSXTAL = [10110] for 18pF Xtal C-load. Every step is 1.68 pf CSXTAL[4:0] C load (pf) INTXC: Reseved. Shall be set to [0]. 25

26 RX Gain Register III (Address: 1Ch) Name R RLC7 RLC6 RLC5 RLC4 RLC3 RLC2 RLC1 RLC0 W EDRL HECS STS RGC1 RGC0 VRPL1 VRPL0 INTPRC Reset RLC [7:0]: RSSI Calibration Low Threshold (read only). EDRL Enable Dynamic FIFO Function. [0]: Disable. [1]: Enable. Refer to chapter 16 for details. HECS: Header CRC-8 Enable.. [0]: Disbale. [1]: enable If HECS = 1, HEC (one byte) is added into TX-Packet. Refer to chapter 16 for details. STS: Reserved for internal usage. Recommend STS = [0]. RGC[1:0]: Reserved for internal usage. Recommend RGC = [00]. VRPL[1:0]: Reserved for internal usage. Recommend VRPL = [00]. INTPRC: Reserved for internal usage. Recommend INTPRC = [0] RX Gain Register IV (Address: 1Dh) Name W ERSSM AVSEL1 AVSEL0 MVSEL1 MVSEL0 MHC LHC NS1 Reset ERSSM: Ending Mode Select in RSSI Measurement. Recommend ERSSM = [0]. [0]: RSSI value fronzen before leaving RX. [1]: RSSI value fronzen when valid frame sync (ID and header check ok). AVSEL [1:0]: ADC average mode. Recommend AVSEL = [10]. [00]: No average. [01]: 2. [10]: 4. [11]: 8. MVSEL [1:0]: ADC average mode for VCO calibration and RSSI. Recommend MVSEL = [10]. [00]: 8. [01]: 16. [10]: 32. [11]: 64. MHC: Mixer Current Select. Recommend MHC = [1]. [0]: 0.6mA. [1]: 1mA. LHC: LNA Current Select. Recommend LHC = [1]. [0]: 0.5mA. [1]: 1mA. NS1: Reserve. Shall be set to [0] RSSI Threshold Register (Address: 1Eh) R ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Name W RTH7 RTH6 RTH5 RTH4 RTH3 RTH2 RTH1 RTH0 Reset ADC [7:0]: ADC digital output value (read only). ADC input voltage= * ADC [7:0] / 256 V. Refer to chapter 17 for details. RTH [7:0]: Carrier detect threshold. CD (Carrier Detect)=1 when RSSI RTH. CD (Carrier Detect)=0 when RSSI < RTL. 26

27 Refer to chapter 17 for details ADC Control Register (Address: 1Fh) Name W RSM1 RSM0 RADC FSARS XADS RSS CDM Reset RSM [1:0]: RSSI Margin = RTH RTL. Recommend RSM = [11]. [00]: 5. [01]: 10. [10]: 15. [11]: 20. Refer to chapter 17 for details. RADC: ADC Read Out Average Mode. [0]: 1, 2, 4, 8 average mode. If RADC = 0, ADC average is set by AVSEL[1:0] (1Dh). [1]: 8, 16, 32, 64 average mode. If RADC = 1, ADC average is set by MVSEL[1:0] (1Dh). FSARS: ADC Clock Select. Recommend FSARS = [0]. [0]: 4MHz. [1]: 8MHz. XADS: External ADC Input Signal Select. [0]: Disable. [1]: Enable. RSS: RSSI measurement select. [0]: Thermal sensor. [1]: RSSI or carrier detector. CDM: RSSI measurement mode. Recommend CDM = [0]. [0]: Single mode. [1]: Continuous mode Code Register I (Address: 20h) Name W MCS WHTS FECS CRCS IDL1 IDL0 PML1 PML0 Reset MCS: Manchester Enable. [0]: Disable. [1]: Enable. WHTS: Data Whitening (Data Encryption) Select. [0]: Disable. [1]: Enable (The data is whitening by multiplying PN7). FECS: FEC Select. [0]: Disable. [1]: Enable (The FEC is (7, 4) Hamming code). CRCS: CRC Select. [0]: Disable. [1]: Enable. The CRC is set by CRCDNP (1Ah) for either CCITT-16 CRC or CRC-DNP IDL [1:0]: ID Code Length Select. Recommend IDL= [01]. [00]: 2 bytes. [01]: 4 bytes. [10]: 6 bytes. [11]: 8 bytes. PML [1:0]: Preamble Length Select. Recommend PML= [11]. [00]: 1 byte. [01]: 2 bytes. [10]: 3 bytes. [11]: 4 bytes Code Register II (Address: 21h) Name W DCL2 DCL1 DCL0 ETH2 ETH1 ETH0 PMD1 PMD0 Reset DCL2: DC Estimation Average Length after frame sync. Recommend DCL2= [1]. [0]: 128 bits. [1]: 256 bits. DCL[1:0]: DC Estimation Average Length Before ID Detected. Recommend DCL= [10]. [00]: 8 bits. [01]: 16 bits. [10]: 32 bits. [11]: 64 bits. ETH [1:0]: Received ID Code Error Tolerance. Recommend ETH = [001]. [000]: 0 bit, [001]: 1 bit. [010]: 2 bit. [011]: 3 bit. [100]: 4 bit, [101]: 5 bit. [110]: 6 bit. [111]: 7 bit. 27

28 PMD [1:0]: Preamble Pattern Detection Length. Recommend PMD = [10]. [00]: 0bit. [01]: 4bits. [10]: 8bits. [11]: 16bits Code Register III (Address: 22h) Name W DCH WS6 WS5 WS4 WS3 WS2 WS1 WS0 Reset DCH: DC Estimation Waiting Time for DC Estimation Hold before ID Detected. Recommend DCH= [0]. [0]: 4bit data after preamble is OK. [1]: 8bit data after preamble is OK. WS [6:0]: Data Whitening Seed (data encryption key). Refer to chapter 16 for details IF Calibration Register I (Address: 23h) R FBCF FB3 FB2 FB1 FB0 Name W -- RMP1 RMP0 MFBS MFB3 MFB2 MFB1 MFB0 Reset FBCF : IF Filter Band Auto Calibration Flag. [0]: Pass. [1]: Fail. FB [3:0] : IF filter bank (read only). RMP[1:0]: TX ramp up scaler. Recommend RMP= [00]. [00]: 1. [01]: 2. [10]: 4. [11]: 8. MFBS : IF Filter Calibration Select. Recommend MFBS = [0]. [0]: Auto. [1]: Manual Setting by MFB[3:0]. MFB [3:0]: IF Filter Manual Calibration Setting IF Calibration Register II (Address: 24h) R FCD4 FCD3 FCD2 FCD1 FCD0 Name W TRT2 TRT1 TRT0 ASMV2 ASMV1 ASMV0 AMVS Reset FCD [4:0]: IF Filter Auto Calibration Deviation from Goal (read only). TRT [2:0]: TX Ramp down discharge current select. Recommand TRT=[111]. ASMV [2:0]: TX Ramp up timing select. Recommand ASMV=[111]. [000]: 2us. [001]: 4us. [010]: 6us. [011]: 8us. [100]: 10us, [101]: 12us. [110]: 14us. [111]: 16us. Actual TX ramp up time = ASMV [2:0] x RMP[1:0] AMVS : TX Ramp Up Enable. Recommand AMVS=[1]. [0]: Disable. [1]: Enable VCO Current Calibration Register (Address: 25h) R VCCF VCB3 VCB2 VCB1 VCB0 Name W -- VCRLS VBS MVCS VCOC3 VCOC2 VCOC1 VCOC0 Reset VCCF : VCO Current Auto Calibration Flag. [0]: Pass. [1]: Fail. VCB [3:0]: VCO Current Bank Calibration result. 28

29 If MVCS= 0, VCB[3:0] is auto calibration result. If MVCS= 1, VCB[3:0] is manual calibration setting. VCRLS : VCO Current Resistor Select. Recommand VCRLS=[0]. [0]: low current. [1]: high current. VBS : VCO Band Select. [0]: 915MHz. [1]: 868MHz / 433MHz. MVCS: VCO current calibration select. Recommend MVCS = [0]. [0]: Auto. [1]: Manual. VCOC [3:0]: VCO Current Bank Manual Calibration setting. Refer to chapter 15 for details VCO Bank Calibration Register I (Address: 26h) R VBCF VB2 VB1 VB0 Name W DCD1 DCD0 DAGS CWS MVBS MVB2 MVB1 MVB0 Reset VBCF: VCO Band Auto Calibration Flag. [0]: Pass. [1]: Fail. VB [2:0]: VCO Bank Calibration Value (read only). If MVBS= 0, VB[2:0] is auto calibration result. If MVBS= 1, VB[2:0] is manual calibration setting. DCD [1:0]: VCO Deviation Calibration Delay. Delay time = PDL (Delay Register I, 17h) ( DCD + 1 ). Please refer to AMICCOM reference code for optimization in different RF band. CWS: Clock Disable for VCO Modulation. Recommend CWS = [0]. [0]: Enable. [1]: Disable. DAGS: DAG Calibration Value Select. Recommend DAGS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. MVBS: VCO Bank Calibration Select. Recommend MVBS = [0]. [0]: Auto. [1]: Manual. MVB [2:0]: Manual VCO Band Setting. VCO frequency increases when MVB increases. Refer to chapter 15 for details VCO Bank Calibration Register II (Address: 27h) R DAGB7 DAGB6 DAGB5 DAGB4 DAGB3 DAGB2 DAGB1 DAGB0 Name W DAGM7 DAGM6 DAGM5 DAGM4 DAGM3 DAGM2 DAGM1 DAGM0 Reset DAGB [7:0]: Auto DAG Calibration result. DAGM [7:0]: DAG Manual Setting Value. Recommend DAGM = [0x80] VCO Deviation Calibration Register I (Address: 28h) R DEVA7 DEVA6 DEVA5 DEVA4 DEVA3 DEVA2 DEVA1 DEVA0 Name W DEVS3 DEVS2 DEVS1 DEVS0 DAMR_M VMTE_M VMS_M MSEL Reset

30 DEVA [7:0]: Deviation Calibration result (read only). If MVDS (29h) = 0, DEVA [7:0] is auto calibration result ((DEVC / 8) (DEVS + 1)). If MVDS (29h) = 1, DEVA [7:0] is manual calibration result (DEVM [6:0]). DEVS [3:0]: Deviation Output Scaling. Freq. Band Data Rate DEVS[3:0] 915MHz 2Mbps Mbps Kbps Kbps 0111 Freq. Band Data Rate DEVS[3:0] 868MHz 500Kbps Kbps 0111 Freq. Band Data Rate DEVS[3:0] 433MHz 2Mbps Mbps Kbps Kbps 0111 DAMR_M: DAMR Manual Enable. Recommend DAMR_M = [0]. [0]: Disable. [1]: Enable. VMTE_M: VMT Manual Enable. Recommend VMTE_M = [0]. [0]: Disable. [1]: Enable. VMS_M: VM Manual Enable. Recommend VMS_M = [0]. [0]: Disable. [1]: Enable. MSEL: VMS, VMTE and DAMR control select. Recommend MSEL = [0]. [0]: Auto control. [1]: Manual control VCO Deviation Calibration Register II (Address: 29h) R DEVC7 DEVC6 DEVC5 DEVC4 DEVC3 DEVC2 DEVC1 DEVC0 Name W MVDS DEVM6 DEVM5 DEVM4 DEVM3 DEVM2 DEVM1 DEVM0 Reset DEVC [7:0]: VCO Deviation Auto Calibration result. MVDS: VCO Deviation Calibration Select. Recommend MVDS = [0]. [0]: Auto. [1]: Manual. DEVM [6:0]: VCO Deviation Manual Calibration Setting. Refer to chapter 15 for details VCO Deviation Calibration Register III (Address: 2Ah) Name W/R VMG7 VMG6 VMG5 VMG4 VMG3 VMG2 VMG1 VMG0 Reset VMG [7:0]: VM Center Value for Deviation Calibration. Recommend VMG[7:0] = [0x80] VCO Modulation Delay Register (Address: 2Bh) Name W DMV1 DMV0 DEVFD2 DEVFD1 DEVFD0 DEVD2 DEVD1 DEVD0 Reset

31 DMV [1:0]: Demodulator Voltage Range Select. [00]: 1/32*1.2. [01]: 1/16*1.2. [10]: 1/8*1.2. [11]: 1/4*1.2. DEVFD [2:0]: VCO Modulation Data Delay by 8x over-sampling Clock. DEVD [2:0]: VCO Modulation Data Delay by XCPCK Clock. Freq. Band Data Rate VCO Mod. Delay Setting 915MHz 2M 0xE0 1M 0xE0 500K 0x98 100K 0x98 868MHz 500K 0x98 100K 0x98 433MHz 2M 0xE8 1M 0xE8 500K 0x8E 100K 0x8E Battery Detect Register (Address: 2Ch) R -- RGV1 RGV0 BDF BVT2 BVT1 BVT0 BD_E Name W ECKS RGV1 RGV0 QDS BVT2 BVT1 BVT0 BD_E Reset ECKS : Clock phae delay selection. Recommend ECKS = [0]. [0]: no delay. [1]: delay 1/2 cycle. RGV [1:0]: Regulator Voltage Select. Recommend RGV = [11]. [00]: 2.1V. [01]: 2.0V. [10]: 1.9V. [11]: 1.8V. QDS: VDD_A Quick Discharge Select. Recommend QDS = [1]. [0]: Disable. [1]: Enable. BDF : Low Battery Detection Flag. [0]: battery low. [1]: battery high. BVT [2:0]: Battery Voltage Threshold Select. [000]: 2.1V, [001]: 2.2V. [010]: 2.3V. [011]: 2.4V. [100]: 2.5V. [101]: 2.6V. [110]: 2.7V. [111]: 2.8V. (Typical +-0.1V detection inaccuracy.) BD_E: Battery Detect Enable. [0]: Disable. [1]: Enable. It will be clear after battery detection is triggered TX Test Register (Address: 2Dh) Name W ASKS PAC1 PAC0 TDC1 TDC0 TBG2 TBG1 TBG0 Reset ASKS : Reserved for internal useage only. Recommend ASKS = [0]. PAC [1:0]: PA Current Setting. TDC [1:0]: TX Current Setting. TBG [2:0]: TX Buffer Gain Setting. RF Band Typical power (dbm) TBG TDC PAC Typical current 915MHz ma ma 31

32 ma ma ma ma ma ma ma RF Band Typical power (dbm) TBG TDC PAC Typical current 868MHz ma ma ma ma ma ma ma ma ma RF Band Typical power (dbm) TBG TDC PAC Typical current 433MHz ma ma ma ma ma ma ma ma ma Also, refer to App. Note for more details RX DEM Test Register I (Address: 2Eh) Name W DMT DCM1 DCM0 MLP1 MLP0 SLF2 SLF1 SLF0 Reset DMT: Reserved for internal usage only. Shall be set to [0]. DCM [1:0]: Demodulator DC estimation mode. Recommend DCM = [10]. [00]: DC set by DCV in Rx Demodulator Test Register II (2Fh). [01]: DC holds after preamble detected. [10]: DC holds after ID detected. [11]: No hold. 32

33 MLP [1:0]: Reserved for internal usage only. Shall be set to [00]. SLF [2:0]: Symbol Recovery Loop Filter Setting. Shall be set to [111] RX DEM Test Register II (Address: 2Fh) Name W DCV7 DCV6 DCV5 DCV4 DCV3 DCV2 DCV1 DCV0 Reset DCV [7:0]: Demodulator Fix mode DC value. Recommend DCV = [0x80] Charge Pump Current Register I (Address: 30h) Name W CPM3 CPM2 CPM1 CPM0 CPT3 CPT2 CPT1 CPT0 Reset CPM [3:0]: Charge Pump Current Setting for VM loop. Recommend CPM = [1111]. Charge pump current = (CPM + 1) / 16 ma. CPT [3:0]: Charge Pump Current Setting for VT loop. Recommend CPT = [0100]. Charge pump current = (CPT + 1) / 16 ma Charge Pump Current Register II (Address: 31h) Name W CPTX3 CPTX2 CPTX1 CPTX0 CPRX3 CPRX2 CPRX1 CPRX0 Reset CPTX [3:0]: Charge Pump Current Setting for TX mode. Charge pump current = (CPTX + 1) / 16 ma. CPRX [3:0]: Charge Pump Current Setting for RX mode. Charge pump current = (CPRX + 1) / 16 ma Crystal Test Register (Address: 32h) Name W LVR RGS MD1 MD0 DBD XCC XCP1 XCP0 Reset LVR : Low Power Bandgap Select. Recommend LVR = [0]. RGS : Low Power Regulator Voltage Select. LVR RGS Low Power Regulator Voltage Note 0 0 3/5 *REGI Recommended 0 1 3/4 * REGI V V MD [1:0]: VCO Divider Select. [00]: 1/6. [01]: 1/4. [10]: 1/2. [11]: 1/2. Freq Band VBS (25h) MD [1:0] Note 315MHz MHz MHz 1 10 or MHz 0 10 or 11 DBD : Crystal Frequency Doubler High Level Pulse Width Select. Recommend DBD = [0]. [0]: about 8 ns. [1]: about 16 ns. 33

34 XCC : Crystal Startup Current Selection. Recommend XCC = [1]. [0]: 0.7 ma. [1]: 1.5 ma. XCP [1:0]: Crystal Oscillator Regulated Couple Setting. Recommend XCP = [00]. [00]: 1.5mA. [01]: 0.5mA. [10]: 0.35mA. [11]: 0.3mA PLL Test Register (Address: 33h) Name W SDMS CPS PRIC1 PRIC0 PRRC1 PRRC0 SDPW NSDO Reset SMDS: Reserved for internal usage only. Shall be set to [0]. CPS : Charge Pump Select. Shall be set to [1]. [0]: charge-pump tri-state. [1]: Normal. PRIC [1:0]: Prescaler IF Part Current Setting. Shall be set to [01]. [00]: 0.95mA. [01]: 1.05mA. [10]: 1.15mA. [11]: 1.25mA. PRRC [1:0]: Prescaler RF Part Current Setting. Shall be set to [00]. [00]: 1.0mA. [01]: 1.2mA. [10]: 1.4mA. [11]: 1.6mA. SDPW : Clock Delay For Sigma Delta Modulator. Shall be set to [0]. [0]: 13 ns. [1]: 26 ns. NSDO : Sigma Delta Order Setting. Shall be set to [1]. [0]: order 2. [1]: order VCO Test Register (Address: 34h) Name W DEVGD2 DEVGD1 DEVGD0 LOB1 LOB0 DIVRF1 DIVRF0 VCBS Reset DEVGD [2:0]: Sigma Delta Modulator Data Delay Setting. Recommend DEVGD = [000]. LOB [1:0]: LO Buffer Current Select. Shall be set to [10]. [00]: 0.6mA. [01]: 0.75mA. [10]: 0.9mA. [11]: 1.05mA. DIVRF [1:0]: RF divider Current Select. Shall be set to [00]. [00]: 1.2mA. [01]: 1.5mA. [10]: 1.8mA. [11]: 2.1mA. VCBS : VCO Buffer Current Setting. Shall be set to [0]. [0]: 1mA. [1]: 1.5mA RF Analog Test Register (Address: 35h) Name W ASDAR MDEN OLM CPH CPCS RFT2 RFT1 RFT0 Reset ASDAR : Internal Comparator Reference Enable. Shall be set to [0]. MDEN : Use for Manual VCO Calibration. Shall be set to [0]. OLM : Open Loop Modulation Enable. Shall be set to [0]. [0]: Disable. [1]: Enable. CPH : Charge Pump High Current. Shall be set to [0]. [0]: Normal. [1]: High. CPCS : Charge Pump Current Select. Shall be set to [1]. [0]: Use CPM for TX, CPT for RX. [1]: Use CPTX for TX, CPRX for RX. RFT [2:0]: RF Analog Pin Configuration. Recommend RFT= [000]. {XADS, RFT[2:0]} BP_BG (pin 2) BP_RSSI (pin 1) 34

35 [0000] Band-gap voltage RSSI voltage [0001] Analog temperature voltage RSSI voltage [0010] Band-gap voltage No connection [0011] Analog temperature voltage No connection [0100] BPF positive in phase output BPF negative in phase output [0101] BPF positive quadrature phase output BPF negative quadrature phase output [0110] RSSI voltage No connection [0111] RSSI voltage No connection [1000] Band-gap voltage External ADC input source [1001] Analog temperature voltage External ADC input source [1010] Band-gap voltage External ADC input source [1011] Analog temperature voltage External ADC input source [1100] No connection External ADC input source [1101] No connection External ADC input source [1110] No connection External ADC input source [1111] No connection External ADC input source IFAT Register (Address: 36h) Name W IGFI2 IGFI1 IGFI0 IGFQ2 IGFQ1 IGFQ0 AGCT LIMC Reset IGFI [2:0]: Norminal IFA-I Gain Setting. Shall be set to [111] [000]: -2.8dB. [001]: -2.4dB. [010]: -2.0dB. [011]: -1.6dB. [100]: -1.2dB, [101]: -0.8dB. [110]: -0.4dB. [111]: Norminal. IGFQ [2:0]: Norminal IFA-Q Gain Setting. Shall be set to [111] [000]: -2.8dB. [001]: -2.4dB. [010]: -2.0dB. [011]: -1.6dB. [100]: -1.2dB, [101]: -0.8dB. [110]: -0.4dB. [111]: Norminal. AGCT: Reserved for internal usage only. Shall be set to [0]. LIMC: Reserved for internal usage only. Shall be set to [1] Channel Selct Register (Address: 37h) Name W CHI3 CHI2 CHI1 CHI0 CHD3 CHD2 CHD1 CHD0 Reset CHI [3:0]: Auto IF Offset Channel Number Setting. CHI = [0001] for 500K mode. CHI = [0111] for 2M mode. F CHSP ( CHI + 1 ) = F IF CHD [3:0]: Channel Frequency Offset for Deviation Calibration. CHD = [0101] for 500K mode. CHD = [0111] for 2M mode. Offset channel number = +/- (CHD + 1). Freq. Band Data Rate CHD[3:0] Setting 915MHz / 868MHz 2M [0111] 500K [0111] 433MHz 2M [0111] 500K [0101] 35

36 VRB Register (Address: 38h) Name W VTRB3 VTRB2 VTRB1 VTRB0 VMRB3 VMRB2 VMRB1 VMRB0 Reset VTRB [3:0]: Resistor Bank for VT RC Filtering. Shall be set to [0000]. VMRB [3:0]: Resistor Bank for VM RC Filtering. Shall be set to [0000] Data Rate Clock Register (Address: 39h) Name W SDR7 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 Reset SDR [1:0]: Data Rate Setting. Data rate = F IF / (SDR+1). IFS (0Dh) F IF (Hz) SDR [7:0] Data Rate 1 2M 0x00 2M 1 2M 0x01 1M 0 500K 0x00 500K 0 500K 0x01 250K 0 500K 0x03 125K 0 500K 0x04 100K FCR Register (Address: 3Ah) R ARTEF VPOAK RCR3 RCR2 RCR1 RCR0 EAK EAR Name W FCL1 FCL0 ARC3 ARC2 ARC1 ARC0 EAK EAR Reset ARTEF : Auto-resend Ending flag. [0]: resend on going [1]: complete resend procedures VPOAK : Valid Packet or ACK OK Flag. (clear by any Strobe command.) VPOAK is also able to output to GIO1/GIO2 to inform MCU by setting GIO1S/GIO2S. [0]: Neither valid packet nor ACK OK. [1]: Valid packet or ACK OK. RCR [3:0] : Decremental of ARC[3:0]. ARC [3:0] : Auto-resend Cycle. [0000]: no resend. [0001]: 1 [0010]: 2 [0011]: 3 [0100]: 4 [0101]: 5... [1111]: 15 FCL [1:0] : Frame Control Length. [00]: No Frame Control [01]: 1 byte Frame Control. (FCB0), refer to 3Dh. [10]: 2 byte Frame control. (FCB0+FCB1), refer to 3Dh. [11]: 4 byte Frame control. (FCB0+FCB1+FCB2+FCB3), refer to 3Dh. EAK : Enable Auto-ack. [0]: Disable. [1]: Enable. EAR : Enable Auto-resend. [0]: Disable. [1]: Enable. 36

37 ARD Register (Address: 3Bh) Name W ARD7 ARD6 ARD5 ARD4 ARD3 ARD2 ARD1 ARD0 Reset ARD[7:0] : Auto-resend Delay ARD Delay = 200 us * (ARD+1) à (200us ~ 51.2 ms) [ ]: 200 us. [ ]: 400 us. [ ]: 600 us. [ ]: 51.2 ms AFEP Register (Address: 3Ch) Name R 0 0 EARTS2 EARTS1 EARTS0 SID2 SID1 SID0 ACKFEP ACKFEP ACKFEP ACKFEP ACKFEP ACKFEP W EAF SPSS Reset EAF: Enable ACK FIFO. [0]: Disable. [1]: Enable. SPSS : Mode Back Select after Auto-ack or Auto-resend. [0]: Standby mode. [1]: PLL mode. ACKFEP [5:0]: FIFO End Point for Auto-ack. Reserved for internal usage. EARTS [2:0]: Enable Auto-resend Read. Reserved for internal usage WMUX Register (Address: 3Dh) WMUXH WMUXH WMUXH WMUXH WMUXL WMUXL WMUXL WMUXL Name R Reset WMUXH[7:4]: Reserved for internal usage. Recommend WMUXH = [0000]. WMUXL[3:0]: Reserved for internal usage. Recommend WMUXL = [0000] FCB Register (Address: 3Eh) Name R/W FCB7 FCB6 FCB5 FCB4 FCB3 FCB2 FCB1 FCB0 Reset FCB [7:0]: Frame Control Buffer Length of Frame Control Buffer is set by FCL (31h), max 4 bytes (FCB0 ~ FCB3) FCB0 FCB1 FCB2 FCB3 For Auto-resend User definition (default value is 0x00) FCB0 [7:0]: Reserved for Auto-resend usage. FCB SID2 SID1 SID0 SID [2:0]: Serial Package ID. The transmitter increments the SID field each time it generates a new packet and uses the same SID on packets 37

38 which are resent. Noted that to program FCB, If FCL=[00], no frame control buffer. (Auto-resend is inactive.) If FCL=[01], FCB= (FCB0), FCB0 is internal usage for Auto-resend. If FCL=[10], FCB= (FCB0+FCB1), user can define 1 bytes data to FCB1 and the first byte is a dummy byte. If FCL=[11], FCB= (FCB0+FCB1+FCB2+FCB3), user can define 3 bytes data to FCB1~FCB3 and the first byte is a dummy byte. Refer to chapter 20 for details. 38

39 10. SPI A7128 only supports one SPI interface with max. data rate 10Mbps. MCU should assert SCS pin low (SPI chip select) to active accessing of A7128. Via SPI interface, user can access control registers and issue Strobe command. Figure 10.1 gives an overview of SPI access manners. 3-wire SPI (SCS, SCK and SDIO) or 4-wire SPI (SCS, SCK, SDIO and GIO1/GIO2) configuration is provided. For 3-wire SPI, SDIO pin is configured as bi-direction to be data input and output. For 4-wire SPI, SDIO pin is data input and GIO1 (or GIO2) pin is data output. In such case, GIO1S (0bh) or GIO2S (0ch) should be set to [0110]. For SPI write operation, SDIO pin is latched into A7128 at the rising edge of SCK. For SPI read operation, if input address is latched by A7128, data output is aligned at falling edge of SCK. Therefore, MCU can latch data output at the rising edge of SCK. To control A7128 s internal state machine, it is very easy to send Strobe command via SPI interface. The Strobe command is a unique command set with total 8 commands. See section 10.3, 10.4 and 10.5 for details. SPI chip select Data In Data Out 3-Wire SPI SCS pin = 0 SDIO pin SDIO pin 4-Wire SPI SCS pin = 0 SDIO pin GIO1 (GIO1S=0110) GIO2 (GIO2S=0110) SCS Read/Write register ADDR reg DataByte ADDR reg DataByte ADDR reg DataByte Read/Write RF FIFO Read/Write ID register Sleep Mode Idle Mode STBY Mode PLL Mode RX Mode ADDR FIFO DataByte 0 DataByte 1 DataByte 2 DataByte 3 ADDR ID DataByte 0 DataByte 1 DataByte 2 DataByte 3 Strobe Command Sleep Mode Strobe Command Idle Mode Strobe Command STBY Mode Strobe Command PLL Mode Strobe Command RX Mode DataByte n TX Mode FIFO Write Reset Strobe Command TX Mode Strobe Command FIFO Write Reset FIFO Read Reset Strobe Command FIFO Read Reset Figure 10.1 SPI Access Manners 39

40 10.1 SPI Format The first bit (A7) is critical to indicate A7128 the following instruction is Strobe command or control register. See Table 10.1 for SPI format. Based on Table 10.1, if A7=0, A7128 is informed for control register accessing. So, A6 bit is used to indicate read (A6=1) or write operation (A6=0). See Figure 10.2 and Figure 10.3 for details. Address Byte (8 bits) Data Byte (8 bits) CMD R/W Address Data A7 A6 A5 A4 A3 A2 A1 A Address byte: Bit 7: Command bit [0]: Control register command. [1]: Strobe command. Table 10.1 SPI Format Bit 6: R/W bit [0]: Write data to control register. [1]: Read data from control register. Bit [5:0]: Address of control register Data Byte [7:0]: SPI input or output data, see Figure 10.2 and Figure 10.3 for details SPI Timing Characteristic No matter 3-wire or 4-wire SPI interface is configured, the maximum SPI data rate is 10 Mbps. To active SPI interface, SCS pin must be set to low. For correct data latching, user has to take care hold time and setup time between SCK and SDIO. See Table 10.2 for details. Parameter Description Min. Max. Unit F C FIFO clock frequency. 10 MHz T SE Enable setup time. 50 ns T HE Enable hold time. 50 ns T SW TX Data setup time. 50 ns T HW TX Data hold time. 50 ns T DR RX Data delay time ns Table 10.2 SPI Timing Characteristic 10.3 SPI Timing Chart In this section, 3-wire and 4-wire SPI interface read / write timing are described. 40

41 Timing Chart of 3-wire SPI SCS SCK SDIO A7 A6 A5 A4 A3 A2 A1 A0 D W 7 D W 6 D W 5 D W 1 D W 0 RF IC will latch address bit at rising edge of SCK RF IC will latch data bit at the rising edge of SCK 3-Wire serial interface - Write operation SCS SCK SDIO A7 A6 A5 A4 A3 A2 A1 A0 D R 7 D R 6 D R 5 D R 1 D R 0 RF IC will latch address bit at rising edge of SCK RF IC will change the data when falling edge of SCK MCU can latch data at rising edge of SCK 3-Wire serial interface - Read operation Figure 10.2 Read/Write Timing Chart of 3-Wire SPI Timing Chart of 4-wire SPI SCS SCK SDIO A7 A6 A5 A4 A3 A2 A1 A0 D W 7 D W 6 D W 5 D W 1 D W 0 RF IC will latch address bit at rising edge of SCK RF IC will latch data bit at rising edge of SCK 4-Wire serial interface - Write operation SCS SCK SDI A7 A6 A5 A4 A3 A2 A1 A0 x x GIOx D R 7 D 6 D R 5 D 2 D R 1 D R 0 R R RF IC will latch address bit at rising edge of SCK RF IC will change the data when falling edge of SCK MCU can latch data at the rising edge of SCK 4-Wire serial interface - Read operation Figure 10.3 Read/Write Timing Chart of 4-Wire SPI 41

42 10.4 Strobe Commands A7128 supports 8 Strobe commands to control internal state machine for chip s operations. Table 10.3 is the summary of Strobe commands. Be notice, Strobe command could be defined by 4-bits (A7~A4) or 8-bits (A7~A0). If 8-bits Strobe command is selected, A3 ~ A0 are don t care conditions. In such case, SCS pin can be remaining low for asserting next commands. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description x x x Sleep mode x x x x Idle mode x x x x Standby mode x x x x PLL mode x x x x RX mode x x x x TX mode x x x x FIFO write pointer reset x x x x FIFO read pointer reset c Deep sleep mode (Tri-state of GIO1 / GIO2) Deep sleep mode (Internal Pull-High of GIO1 / GIO2) Table 10.3 Strobe Commands by SPI interface Strobe Command - Sleep Mode Refer to Table 10.3, user can issue 4 bits (1000) Strobe command directly to set A7128 into Sleep mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description x x x x Sleep mode Figure 10.4 Sleep mode Command Timing Chart Strobe Command - ldle Mode Refer to Table 10.3, user can issue 4 bits (1001) Strobe command directly to set A7128 into Idle mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command Description 42

43 A7 A6 A5 A4 A3 A2 A1 A x x x x Idle mode SCS SCS SCK SCK SDIO A7 A6 A5 A4 SDIO A7 A6 A5 A4 A3 A2 A1 A0 Idle mode Idle mode Figure 10.5 Idle mode Command Timing Chart Strobe Command - Standby Mode Refer to Table 10.3, user can issue 4 bits (1010) Strobe command directly to set A7128 into Standby mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description x x x x Standby mode Figure 10.6 Standby mode Command Timing Chart Strobe Command - PLL Mode Refer to Table 10.3, user can issue 4 bits (1011) Strobe command directly to set A7128 into PLL mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description x x x x PLL mode 43

44 Figure 10.7 PLL mode Command Timing Chart Strobe Command - RX Mode Refer to Table 10.3, user can issue 4 bits (1100) Strobe command directly to set A7128 into RX mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description x x x x RX mode Figure 10.8 RX mode Command Timing Chart Strobe Command - TX Mode Refer to Table 10.3, user can issue 4 bits (1101) Strobe command directly to set A7128 into TX mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description x x x x TX mode 44

45 Figure 10.9 TX mode Command Timing Chart Strobe Command FIFO Write Pointer Reset Refer to Table 10.3, user can issue 4 bits (1110) Strobe command directly to reset A7128 FIFO write pointer. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description x x x x FIFO write pointer reset Figure FIFO write pointer reset Command Timing Chart Strobe Command FIFO Read Pointer Reset Refer to Table 10.3, user can issue 4 bits (1111) Strobe command directly to reset A7128 FIFO read pointer. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description x x x x FIFO read pointer reset Figure FIFO read pointer reset Command Timing Chart Strobe Command Deep Sleep Mode Refer to Table 10.3, user can issue a (8 bits) deep sleep Strobe command directly to switch off power supply to A7128.In this mode, A7128 is staying minimum current consumption. All registers are no data retention and re-calibration flow is necessary. Below are the Strobe command table and timing chart. 45

46 Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description Tri-state of GIO1 / GIO2 (no register retention) Internal Pull-High of GIO1 / GIO2 (no register retention) Figure Deep Sleep Mode Timing Chart 10.5 Reset Command In addition to power on reset (POR), MCU could issue software reset to A7128 by setting Mode Register (00h) through SPI interface as shown below. As long as 8-bits address (A7~A0) are delivered zero and data (D7~D0) are delivered zero, A7128 is informed to generate internal signal RESETN to initial itself. After reset command, A7128 is in standby mode. SCS SCK SDIO A7 A6 A5 A4 A3 A2 A1 A0 D W 7 D W 6 D W 5 D W 1 D W 0 RESETN Reset RF chip Figure Reset Command Timing Chart 10.6 ID Accessing Command A7128 has built-in 32-bits ID Registers for customized identification code. It is accessed via SPI interface. ID length is recommended to be 32 bits by setting IDL (20h). Therefore, user can toggle SCS pin to high to terminate ID accessing command when ID data is output completely. Figure and are timing charts of 32-bits ID accessing via 3-wire SPI ID Write Command User can refer to Figure 10.2 for SPI write timing chart in details. Below is the procedure of ID write command. Step1: Deliver A7~A0 = (A6=0 for write control register and issue ID addr = 06h). 46

47 Step2: By SDIO pin, deliver 32-bits ID into A7128 in sequence by Data Byte 0, 1, 2 and 3. Step3: Toggle SCS pin to high when step2 is completed. Figure ID Write Command Timing Chart ID Read Command User can refer to Figure 10.2 for SPI read timing chart in details. Below is the procedure of ID read command. Step1: Deliver A7~A0 = (A6=1 for read control register and issue ID addr = 06h). Step2: SDIO pin outputs 32-bits ID in sequence by Data Byte 0, 1, 2 and 3. Step3: Toggle SCS pin to high when step2 is completed. Figure ID Read Command Timing Chart 10.7 FIFO Accessing Command To use A7128 s FIFO mode, just needs to set FMS (01h) =1 via SPI interface. In FIFO mode, before TX delivery, user only needs to write wanted data into TX FIFO in advance. Similarly, user can read RX FIFO once payload data is received. MCU can use polling or interrupt scheme to do FIFO accessing. FIFO status is output via GIO1 (or GIO2) pin by setting GIO1 (0Bh) or GIO2 (0Ch). Figure and are timing charts of FIFO accessing via 3-wire SPI TX FIFO Write Command User can refer to Figure 10.2 for SPI write timing chart in details. Below is the procedure of TX FIFO write command. Step1: Deliver A7~A0 = (A6=0 for write control register and issue FIFO addr = 05h). Step2: By SDIO pin, deliver (n+1) bytes TX data into TX FIFO in sequence by Data Byte 0, 1, 2 to n. Step3: Toggle SCS pin to high when step2 is completed. Step4: Send Strobe command of TX mode to do TX delivery. Refer to Figure

48 Figure TX FIFO Write Command Timing Chart Rx FIFO Read Command User can refer to Figure 10.2 for SPI read timing chart in details. Below is the procedure of RX FIFO read command. Step1: Deliver A7~A0 = (A6=1 for read control register and issue FIFO addr = 05h). Step2: SDIO pin outputs RX data from RX FIFO in sequence by Data Byte 0, 1, 2 to n. Step3: Toggle SCS pin to high when RX FIFO is read completely. Figure RX FIFO Read Command Timing Chart 48

49 11. State machine In chapter 9 and chapter 10, user can not only learn A7128 s control registers but also know how to issue Strobe command. From section 10.2 ~ 10.6, it is clear to know configurations of 3-wire SPI and 4-wire SPI, Strobe command, software reset, and how to access ID Registers as well as TX/RX FIFO. In section 11.1, built-in state machine is introduced. Then, combined with Strobe command, software reset and A7128 s control registers, section 11.2, 11.3 and 11.4 demonstrate 3 state diagrams to explain how transitions of A7128 s operation. From accessing data point of view, if FMS=1 (01h), FIFO mode is enabled, otherwise, A7128 is in direct mode. If FMS=1 and FIFO Read/Write at standby mode, we call it is Normal FIFO mode. Otherwise, If FMS=1 and FIFO Read/Write at PLL mode, we called it is Quick FIFO mode due to the reduction of PLL settling time. If FMS=1 and FIFO Read/Write at IDLE mode, we called it is Power Saving FIFO mode due to the reduction of operation current. SPI chip select Data In Data Out Operation Mode Clock Recovery for Direct Mode 3-Wire SPI SCS pin = 0 SDIO pin SDIO pin FIFO (FMS=1) Direct(FMS=0) CKO pin (CKOS = 0001) 4-Wire SPI SCS pin = 0 SDIO pin GIO1 (GIO1S=0110) / GIO2 (GIO2S=0110) FIFO (FMS=1) Direct(FMS=0) CKO pin (CKOS = 0001) (1) Normal FIFO Mode (FMS=1 and FIFO Standby mode) (2) Quick FIFO Mode (FMS=1 and FIFO PLL mode) (3) Power Saving FIFO Mode (FMS=1 and FIFO IDLE mode) (4) Quick Direct Mode (FMS=0 and FIFO ignored, write TX mode, read RX mode) 11.1 Key states A7128 supports 7 key operation states. Those are, (1) Standby mode (2) Sleep mode (3) Idle mode (4) PLL mode (5) TX mode (6) RX mode (7) CAL mode (8) Deep Sleep mode After power on reset or software reset, A7128 is automatically into standby mode. Then, user has to do calibration process because all control registers are in initial values. The calibration process of A7128 is very easy, user only needs to issue Strobe commands and enable calibration registers. If so, the calibrations are automatically completed by A7128 s internal state machine. See 11.2, 11.3, 11.4 and chapter 15 for details. After calibration, A7128 is ready to do TX and RX operation. User can start wireless transmission Standby mode If Standby Strobe command is issued, A7128 enters standby mode automatically. Internal power management is listed below. Be noted that A7128 enters standby mode automatically after power on reset or software reset. On Chip Regulator Crystal Oscillator Standby mode VCO PLL RX Circuitry TX Circuitry ON ON OFF OFF OFF OFF Strobe Command (1010xxxx)b See Figure

50 Sleep mode If Sleep Strobe command is issued, A7128 enters sleep mode automatically. In sleep mode, A7128 still can accept MCU s commands via SPI interface. But, A7128 can not support Read/Write FIFO in sleep mode. Internal power management is listed below. On Chip Regulator Crystal Oscillator VCO Sleep mode PLL RX Circuitry TX Circuitry OFF OFF OFF OFF OFF OFF Strobe Command (1000xxxx)b See chapter ldle mode If Idle Strobe command is issued, A7128 enters idle mode automatically. In idle mode, A7128 can accept MCU s commands via SPI interface as well as supporting Read/Write FIFO. Internal power management is listed below. On Chip Regulator Crystal Oscillator VCO ldle mode PLL RX Circuitry TX Circuitry ON OFF OFF OFF OFF OFF Strobe Command (1001xxxx)b See chapter PLL mode If PLL Strobe command is issued, A7128 enters PLL mode automatically. In PLL mode, internal PLL and VCO are both turned on to generate LO (local oscillator) frequency before TX and RX operation. Internal power management is listed below. According to PLL Register I, II, III, IV and V, PLL circuitry is easy to control by user s definition. On Chip Regulator Crystal Oscillator VCO PLL mode PLL RX Circuitry TX Circuitry ON ON ON ON OFF OFF Strobe Command (1011xxxx)b See chapter TX mode If TX Strobe command is issued, A7128 enters TX mode automatically for data delivery. Internal power management is listed below. Be notice, (1) If A7128 is in FIFO mode, TX data packet (Preamble + ID + Payload) is delivered out through TX circuitry. Then, A7128 supports auto-back function to previous state for next delivered packet. (2) If A7128 is in direct mode, TX data packet is also delivered out through TX circuitry. Then, A7128 stays in TX mode. User has to issue Strobe command to back to previous state. On Chip Regulator Crystal Oscillator VCO TX mode PLL RX Circuitry TX Circuitry ON ON ON ON OFF ON Strobe Command (1101xxxx)b See chapter 10 50

51 RX mode If RX Strobe command is issued, A7128 enters RX mode automatically for data receiving. Internal power management is listed below. Be notice, (1) If A7128 is in FIFO mode, RX data packet is caught through RX circuitry. Then, A7128 supports auto-back function to previous state for next receiving packet. (2) If A7128 is in direct mode, RX data packet is also caught through RX circuitry. Then, A7128 stays in RX mode. User has to issue Strobe command to back to previous state. On Chip Regulator Crystal Oscillator VCO RX mode PLL RX Circuitry TX Circuitry ON ON ON ON ON OFF Strobe Command (1101xxxx)b See chapter CAL mode Calibration process shall be done after power on reset or software reset. Calibration items include VCO, IF Filter and RSSI. It is easy to implement calibration process by Strobe command and enable CALC (02h) control register. See chapter 15 for details. Be noted that VCO Calibration is executed in PLL mode only. However, IF Filter and RSSI Calibration can be executed in Standby or PLL mode Deep Sleep mode If Deep Sleep Strobe command is issued, A7128 enters sleep mode automatically. In deep sleep mode, A7128 still can accept MCU s commands via SPI interface. But, A7128 is completed switched off power supply. It can not remain registers data, therefore, once exiting this mode, restart the intitial procedure is a must. Internal power management is listed below. On Chip Regulator Crystal Oscillator VCO Sleep mode PLL RX Circuitry TX Circuitry OFF OFF OFF OFF OFF OFF Strobe Command ( )b ( )b See chapter 10 51

52 11.2 FIFO Mode This mode is suitable for requirement of general purpose applications. After calibration flow, user can issue Strobe command to enter standby mode where write TX FIFO or read RX FIFO. From standby mode to packet data transceiving, only one Strobe command is needed. Once transceiving is finished, A7128 is auto back to standby mode. When packets are finished and deeper power saving is necessary, user can issue Strobe command to ask A7128 staying in sleep mode. Figure 11.1 is the state diagram of Normal FIFO mode. CAL CMD CMD Value Calibration Section AK CALC.0=1, RSSI 15.3 CALC.1=1, IF Filter 15.2 CALC.2=1, VCO Deviation 15.6 CALC.3=1, VCO Bank 15.5 CALC.4=1, VCO Current 15.4 Strobe CMD Value Note Section ST1 1011b Enter to PLL ST2 1010b Enter to Standby ST3 1000b Enter to SLEEP ST4 1001b Enter to IDLE ST5-TX 1101b Enter to TX ST5-RX 1100b Enter to RX RST-CMD b Software Reset 10.5 Figure 11.1 State diagram of Normal FIFO Mode 52

53 From Figure 11.1, when ST5 command is issued for TX operation, see Figure 11.2 for detailed timing. A7128 status can be represented to GIO1 or GIO2 pin to MCU for timing control. Strobe CMD (SCS,SCK,SDIO) ST5 No Command Required Next Instruction RF In/Out Pin 130 us (auto delay) Preamble + ID Code + Payload GIO1 Pin - WTR (GIO1S[3:0]=0000) Transmitting Time Auto Back Standby Mode T0 T1 T2 T0-T1: Auto Delay Time T1-T2: Transmitting Time After T2 : Auto Back to Standby mode Figure 11.2 Transmitting Timing Chart of Normal FIFO Mode From Figure 11.1, when ST5 command is issued for RX operation, see Figure 11.3 for detailed timing. A7128 status can be represented to GIO1 or GIO2 pin to MCU for timing control. Strobe CMD (SCS,SCK,SDIO) RF In/Out Pin ST5 130 us Wait for Valid Packet No Command Required Preamble + ID Code + Payload Next Instruction GIO1 Pin - WTR (GIO1S[3:0]=0000) Actual Receiving Time Auto Back Standby Mode T0 T1 T2 T3 T0-T1 : Auto Delay Time T1-T2 : Waits for Valid Packet T2 : Detect the Valid Packet T2-T3 : Actual Receiving Time T3 : Auto Back to Standby mode Figure 11.3 Receiving Timing Chart of Normal FIFO Mode 53

54 11.3 Direct Mode This mode is suitable for fast transceiving. After calibration flow, for every state transition, user has to issue Strobe command to A7128.This mode is also suitable for the requirement of versatile packet format. Noted that user needs to take care the transition time by MCU s timer. When packets are finished and deeper power saving is necessary, user can issue Strobe command to ask A7128 staying in idle mode (or sleep mode). Figure 11.3 is the state diagram of Quick Direct mode. CAL CMD CMD Value Calibration Section AK CALC.0=1, RSSI 15.3 CALC.1=1, IF Filter 15.2 CALC.2=1, VCO Deviation 15.6 CALC.3=1, VCO Bank 15.5 CALC.4=1, VCO Current 15.4 Strobe CMD Value Note Section ST1 1011b Enter to PLL ST2 1010b Enter to Standby ST3 1000b Enter to SLEEP ST4 1001b Enter to IDLE ST5-TX 1101b Enter to TX ST5-RX 1100b Enter to RX RST-CMD b Software Reset 10.5 Figure 11.4 State diagram of Quick Direct Mode 54

55 From Figure 11.4, MCU s delay time and dummy preamble are important for quick direct mode. When ST5 command is issued for TX operation, see Figure 11.5 for detailed timing. A7128 status can be represented to GIO1 and GIO2 pin to MCU for timing control. Strobe CMD (SCS,SCK,SDIO) ST5 No Command ST1 GIO1 Pin - TRXD (GPIO1S[3:0]=0111) 130 us / 70 us Preamble + ID + Payload GIO2 Pin - WTR (GPIO2S[3:0]=0000) GIO2 Pin - TMEO (GPIO2S[3:0]=0010) 52 bits Preamble ID (4 bytes) + Payload CKO Pin - DCK (CKOS[3:0]=0000) T0 T1 T2 T3 T0-T1: MCU Total Delay Time, Refer to Table 11.1 T1-T2: Dummy Preamble, Refer to Table 11.2 T2-T3: Transmitting Time Figure 11.5 TX Timing Chart of Direct Mode Strobe CMD (SCS,SCK,SDIO) ST5 No Command ST1 GIO1 Pin - TRXD (GPIO1S[3:0]=0111) 130 us / 70 us Received ID + Payload GIO2 Pin - PMDO (GPIO2S[3:0]=0011) Check Preamble Check 32-bits ID Payload Output GIO2 Pin - FSYNC (GPIO2S[3:0]=0001) CKO Pin - RCK (CKOS[3:0]=0001) T0 T0-T1: MCU Total Delay Time, Refer to Table 11.1 T1-T2: Check Preamble T2-T3: Check 32-bits ID T2-T4: ID + Payload Output T1 T2 T3 When Preamble is detected (PMDO = 1), RCK will be output. T4 Figure 11.6 RX Timing Chart of Direct Mode 55

56 12 Crystal Oscillator Circuit A7128 needs external crystal or external clock, that is either 12 or 16 MHz, to generate internal wanted clock. Recommend to use 16MHz Xtal with 18pF C-load and max 80 ohm ESR. Relative Control Register Data Rate Clock Register (Address: 0Dh) R SDR1 SDR0 GRC3 GRC2 GRC1 GRC Name W SDR1 SDR0 GRC3 GRC2 GRC1 GRC0 CGS XS Reset Use External Crystal Figure 12.1 shows the connection of crystal network between XI and XO pins. C1 and C2 capacitance built inside A7128 are used to adjust different crystal loading. User can set CSXTAL[4:0] (1Bh) to meet crystal loading requirement. A7128 support low cost crystal within ± 50 ppm accuracy. Be aware that crystal accuracy requirement includes initial tolerance, temperature drift, aging and crystal loading. Note: set XS= 1 (0Dh) to select external crystal oscillator. XI C1 XO C2 Figure12.1 Crystal network connection for using external crystal 12.2 Use External Clock A7128 has built-in AC couple capacitor to support external clock input. Figure 11.2 shows how to connect. In such case, XI pin is left opened. Note: set XS = 0 (0Dh) to select external clock (AC couple capacitor active.). And the frequency accuracy of external clock shall be controlled within ± 50 ppm and the clock swing (peak-to-peak) shall be larger than 1.5V. XI External clock source XO External clock is controlled within ± 50ppm and Vpp is above 1.5V. Figure 12.2 Connect to external clock source 56

57 13. System Clock A7128 supports different external crystal frequency by programmable Data Rate Clock Register (39h). Based on this, two important internal clocks F CGR and F SYCK are generated. (1) F CGR: Clock Generation Reference = FCRYSTAL / (GRC+1) = 2MHz. where GRC is max 15. (2) F SYCK: System Clock = 64 MHz Data Rate Clock Register (Address: 39h) Name W SDR7 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 Reset PLL Register II (Address: 0Fh) R DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 IP8 Name W DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 BIP8 Reset Derive System Clock Because A7128 supports different external crystals, GRC [3:0] (0Dh) are used to get 2 MHz Clock Generation Reference (F CGR) for internal usage. F = GRC F XREF CGR. ( [ 3: 0] + 1) Below is block diagram of system clock. F XTAL is the crystal frequency. User can set registers to get F SYCK = 64MHz. F XREF is the reference clock of Clock Generator to generate F CGR = 2MHz and F SPLL = 64MHz. After delay circuitry, System clock is derived, F SYCK = 64MHz. ADC clock (F ADC = 4MHz or 8MHz) is from F SYCK = 64MHz after frequency divider. GRC CGS IFS XI XO F XTAL XS CE X DBL F XREF (GRC+1) F CGR = 2MHz PLL 64MHz Clock Generator 16MHz (500Kbps) div4 64MHz (2M / 1Mbps) CGS 0 div2 Delay div2 4MHz 8MHz 0 1 F SYCK ADC clock Figure 13.1 System Clock Block Diagram FSARS Recommend to set DBL (0Fh) = [0], then, F XREF = F XTAL Crystal Frequency (F XTAL) Internal Crystal Reference (F XREF) Clock Generation Reference (F CGR) GRC [3:0] 16 MHz 16 MHz Must be 2 MHz [0111] 1 12 MHz 12 MHz Must be 2 MHz [0101] 1 8 MHz 8 MHz Must be 2 MHz [0011] 1 CGS 57

58 13.2 Data Rate A7128 supports programmable data rate by setting SDR [7:0] (39h). Data rate = (F IFCK / (SDR [1:0] +1)). The data rate clock is from IF clock (F IFCK). F IFCK is 2MHz for 2M/1M mode and 500KHz for data rate below 500Kbps. Figure 13.2 Data Rate Block Diagram A7128 Data Rate = (F IFCK / (SDR [1:0] +1)). F SYCK F IFCK (system clock) (IF clock) SDR [7:0] (39h) Data Rate 64 MHz 2 MHz [ ] 2 Mbps 64 MHz 2 MHz [ ] 1 Mbps 64 MHz 500 KHz [ ] 500Kbps 64 MHz 500 KHz [ ] 100Kbps 58

59 14. Tranceiver Frequency A7128 is a half-duplex transceiver with embedded PA and LNA. For TX or RX frequency setting, user just needs to set up LO (Local Oscillator) frequency for two ways radio transmission. To target full range of 915MHz ISM band (902 MHz to 928 MHz), A7128 applies offset concept by LO frequency F LO = F LO_BASE + F OFFSET. Therefore, for different applications, A7128 is easy to implement frequency hopping and multi-channels by ONE register setting, PLL Register (CHN [7:0], 0Eh). Below is the LO frequency block diagram. F PFD X (DBL+1) / (RRC[1:0]+1) PFD VCO F LO F XTAL =16M BIP[8:0] + AC[14:0]/ AFC Divider VCO divider MD[1:0] VBS F MD F LO_BASE BFP[15:0]/ F LO CHN / [4*(CHR+1)] CHN[7:0] CHR[3:0] F offset + F TXRF Figure 14.1 Block Diagram of Local Oscillator PLL Register I (Address: 0Eh) Name R/W CHN7 CHN6 CHN5 CHN4 CHN3 CHN2 CHN1 CHN0 Reset PLL Register II (Address: 0Fh) R DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 IP8 Name W DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 BIP8 Reset PLL Register III (Address: 10h) R IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 Name W BIP7 BIP6 BIP5 BIP4 BIP3 BIP2 BIP1 BIP0 Reset PLL Register IV (Address: 11h) R AC15/FP15 AC14/FP14 AC13/FP13 AC12/P12 AC11/ FP11 AC10/FP10 AC9/FP9 AC8/FP8 Name W BFP15 BFP14 BFP13 BFP12 BFP11 BFP10 BFP9 BFP8 Reset PLL Register V (Address: 12h) R AC7/FP7 AC6/FP6 AC5/FP5 AC4/FP4 AC3/FP3 AC2/FP2 AC1/FP1 AC0/FP0 Name W BFP7 BFP6 BFP5 BFP4 BFP3 BFP2 BFP1 BFP0 59

60 Reset RX Register (Address: 19h) Name W MSCRC RXSM1 RXSM0 AFC RXDI DMG DMS ULS Reset LO Frequency Setting From Figure 14.1, F LO is not only for TX radio frequency but also to be RX LO frequency. To set up F LO, it is easy to implement by below 7 steps. 1. Set the base frequency (F LO_BASE) by PLL Register II, III, IV and V (0Fh, 10h, 11h and 12h). Recommend to set F LO_BASE ~ MHz. 2. Set the channel step (F CHSP) by PLL Register II (0Fh). A7128 supports channel steps by 250K. 3. Set CHN [7:0] to get offset frequency by PLL Register I (0Eh). F OFFSET = CHN [7:0] x F CHSP 4. LO frequency is equal to base frequency. F LO = F LO_BASE 5. MD frequency is equal to VCO frequency divides by VCO divider ( MD[1:0] ). F MD = F LO / (VCO Divider) 6. For TX radio frequency (F TXRF) is equal to MD frequency plus offset frequency. F TXRF = F MD + F OFFSET 7. If disable AIF function (AIF=0), RX LO frequency (F RXLO) is equal to F TXRF. F RXLO = F TXRF 8. If enable AIF function (AIF=1), RX LO frequency F RXLO = F TXRF - F IFCK ( 2M or 500K) (if ULS = 0, select up side band) RX LO frequency F RXLO = F TXRF + F IFCK ( 2M or 500K) (if ULS = 1, select low side band) F LO_BASE 1 BFP[15 : 0] = FPFD ( BIP[8: 0] + ) 16 n 2 1 F = ( DBL + 1) ( BIP[8: 0] n RRC[1: 0] + 1 XTAL + BFP[15 : 0] ) 16 2 Base on the above formula, for example, if select 16MHz crystal (F XTAL= 16 MHz.) and select channel step F CHSP = 250 KHz, To get F LO_BASE and F LO,see Table 14.1, 14.2, 14.3 and Figure 14.2 for details. How to set F LO_BASE ~ MHz STEP ITEMS VALUE NOTE 1 F XTAL 16 MHz Crystal Frequency 2 DBL 0 Disable double function 3 RRC 0 If so, F PFD= 16MHz 4 BIP 0x70 To get F LO =1792 MHz 60

61 5 BFP[15:8], PLL IV 0x80 To get F LO ~ MHz 5 BFP[7:0], PLL V 0x08 6 F LO_BASE ~ MHz LO Base frequency Table 14.1 How to set F LO_BASE How to set F TXRF ~ MHz STEP ITEMS VALUE NOTE 1 F LO_BASE ~ MHz After set up BIP and BFP 2 VBS ; MD VBS=[0] ; MD=[10b] To get F RF_BASE ~ MHz 3 F MD ~ MHz VCO divider frequency 4 CHR 7 To get F CHSP= 250 KHz 5 F CHSP 250 KHz Channel step = 250KHz 6 CHN 0x3C Set channel number = 60 7 F OFFSET 15 MHz F OFFSET= 250 KHz * (60) = 15MHz 8 F TXRF ~ MHz F TXRF = F TXRF = F MD + F OFFSET Table 14.2 How to set F TXRF How to set F RXLO Register Setting F RXLO NOTE AIF=0 USL=0 ~ MHz F RXLO = F LO AIF=0 USL=1 ~ MHz F RXLO = F LO AIF=1 USL=0 ~ MHz F RXLO = F LO - 2MHz (2M /1M mode) AIF=1 USL=1 ~ MHz F RXLO = F LO + 2MHz (2M /1M mode) Table 14.3 How to set F RXLO See below block diagram with registers setting for MHz. X (DBL+1) DBL = 0 / (RRC[1:0]+1) RRC = 0 F PFD =16M PFD VCO F LO = M F XTAL =16M BIP[8:0] + BFP[15:0]/ 2 16 (BIP = 0x70) (BFP = 0x8008) AC[14:0]/ F LO_BASE = M AFC + F LO = M Divider CHN / [4*(CHR+1)] (CHN=0x3C) (CHR = 7) Figure 14.2 Block Diagram of F LO ~ MHz F offset = 15M VCO divider MD[1:0] =10 VBS =0 F MD = M + F TXRF = M 14.2 IF Side Band Select In two ways radio, both master and slave have two roles, TX and RX. In such case, A7128 offers two methods to set up F LO while TRX exchanging. (1) Auto IF exchange (2) Fast exchange Relative Control Register Mode Control Register (Address: 01h) 61

62 R DDPC ARSSI AIF CD WORE FMT FMS ADCM Name W DDPC ARSSI AIF DFCD WORE FMT FMS ADCM Reset RX Register (Address: 19h) Name W -- RXSM1 RXSM0 AFC RXDI DMG DMS ULS Reset Auto IF Exchange A7128 has Auto IF offset function (AIF, 01h). Base on this, user has no need to change CHN [7:0] while TRX exchanging because F LO is changed automatically. See Table 14.1 for details. Item Role AIF ULS CHN[7:0] F CHSP F RF (KHz) (MHz) Master TX Enable 0 0x3C 250 F TXRF ~ NOTE RX Enable 0 0x3C 250 F RXLO ~ F RXLO is auto offset 2MHz (F IF) when 2M/1Mbps Fast Exchange Table 14.4 AIF function while TRX exchanging To reduce PLL settling time, user can disable AIF function and enable fast exchange function by ULS =1 (19h).See Table 14.2 for details Item Role AIF ULS CHN[10] F CHSP F LO (KHz) (MHz) Master TX 0 0 0x3C 250 F TXRF ~ NOTE Slave RX 0 0 0x3C 250 F RXLO ~ up side band TX 0 1 0x F TXRF ~ RX 0 1 0x F RXLO ~ low side band Table 14.5 Fast exchange function while TRX exchanging 62

63 14.4 AFC function AFC (Auto Frequency Compensation) function supports low accuracy crystal without sensitivity degradation. If AFC=1 (19h), bit error rate is optimized because AFC circuitry adjusts RX LO frequency (F RXLO) to compensate crystal drift automatically. F PFD X (DBL+1) / (RRC[1:0]+1) PFD VCO F LO F XTAL =16M AC[14:0]/ BIP[8:0] + AFC BFP[15:0]/ 2 16 F LO_BASE + F LO Divider VCO divider MD[1:0] VBS F MD CHN / [4*(CHR+1)] CHN[7:0] CHR[3:0] F offset + F TXRF Figure 14.3 Block Diagram of enabling AFC function Relative Control Register RX Register (Address: 19h) Name W -- RXSM1 RXSM0 AFC RXDI DMG DMS ULS Reset PLL Register IV (Address: 11h) R --/FP15 AC14/FP14 AC13/FP13 AC12/P12 AC11/ FP11 AC10/FP10 AC9/FP9 AC8/FP8 Name W BFP15 BFP14 BFP13 BFP12 BFP11 BFP10 BFP9 BFP8 Reset PLL Register V (Address: 12h) R AC7/FP7 AC6/FP6 AC5/FP5 AC4/FP4 AC3/FP3 AC2/FP2 AC1/FP1 AC0/FP0 Name W BFP7 BFP6 BFP5 BFP4 BFP3 BFP2 BFP1 BFP0 Reset Below is AFC function procedure: 1. Set AFC= 1 (19h). 2. When A7128 is in RX mode. AFC circuitry compensates crystal drift automatically. 3. The compensation value can be read from AC [14:0] (11h, 12h). 63

64 15. Calibration A7128 needs calibration process during initialization with 5 calibration items, they are, VCO Current, VCO Bank, VCO Deviation, IF Filter Bank and RSSI Calibration. 1. VCO Current Calibration is to find adequate VCO current. 2. VCO Bank Calibration is to select best VCO frequency bank for the calibrated frequency. 3. VCO Deviation Calibration is to calibrate 500 KHz deviation of VCO. 4. IF Filter Bank Calibration is to calibrate IF filter bandwidth and center frequency. 5. RSSI Calibration is to find the RSSI value corresponding to -70dBm RF input and RSSI curve. Be notice that VCO Current, Bank and Deviation should be calibrated in PLL mode by sequence. IF Filter Bank and RSSI could be calibrated in either standby or PLL mode. Relative Control Register Calibration Control Register (Address: 02h) Name R/W VCC VBC VDC FBC RSSC Reset Calibration Procedure 1. Initialize all control registers (refer to A7128 reference code). 2. Select auto value mode (set MFBS, MVCS, MVBS, MVDS= 0). 3. Set A7128 in PLL mode. 4. Enable IF Filter Bank and RSSI Calibration (set VCC = FBC = RSSC= 1) 5. Wait until VCC=FBC=RSSC = 0 (calibration done) 6. Enable channel group calibration and set VBC = VDC =1. 7. Wait until VBC=VDC=RSSC = 0 (calibration done) 8. Check calibration flags (FBCF) and (VCCF, VBCF) Channel Group Function Channel group function is used for VCO calibration that supports to increase the accuracy of VCO Current, Bank and Deviation. By this function, user can easily set Channel Group Register I and II (13h, 14h) to get 915M ISM band into 3 groups as shown below. Then, choose middle frequency (905MHz / 915MHz / 925MHz) of 3 groups to do the VCO Current, Bank and Deviation Calibration. Below is an example of channel group distribution. 905 MHz 915 MHz 925 MHz ISM band 902MHz (CHGL=0x28) 910MHz (CHGH=0x50) 920MHz 928 MHz Figure 15.1 Channel Group setting of VCO calibration 64

65 15.3 Ring Oscillator Calibration A7128 has built-in a ring oscillator to support WOR function. To get good accurancy of WOR period (sleep-rx-sleep-rx ), it is necessary to calibrate ring oscillator. Below is an example of calibration flow. 1. Initialize all control registers (refer to A7128 reference code). 2. Set A7128 in Standby mode. 3. Set RCOSC_E=CALWC=1. 4. Wait until CALWR = 0 (calibration done) 5. Read RCOC [5:0] 6. Ring Osc is calibration success if RCOC [5:0] is in between 0x0B ~ 0x3E. 65

66 16. FIFO (First In First Out) A7128 has the separated physical 64-bytes TX and RX FIFO inside the device. To use A7128 s FIFO mode, user just needs to enable FMS =1. For FIFO accessing, TX FIFO (write-only) and RX FIFO (read-only) share the same register address 05h. TX FIFO represents transmitted payload. On the other hand, RX circuitry synchronizes ID Code and stores received payload into RX FIFO TX Packet Format in FIFO mode Basic FIFO mode If FCL[1:0] = 00 and ENRL = 0, A7128 is formed a Basic FIFO mode which can also support Auto-ack/ Auto-resend function. There is no MAC header in TX packet format. ID code is a PHY header used to be the frame sync to enable RX FIFO receiving. Data whitening(optional) FEC encoded/decoded(optional) CRC -16 calculation(optional) Preamble ID code Payload (CRC) 4 bytes 4 bytes Phy. 64 bytes 2 bytes ID code ID Byte 0 ID Byte 1 ID Byte 2 ID Byte 3 Figure 16.1 TX packet format of basic FIFO mode Preamble: The packet is led by a self-generated preamble which is composed of alternate 0 and 1. If the first bit of ID code is 0, preamble shall be In the contrast, if the first bit of ID code is 1, preamble shall be Preamble length is recommended to set 4 bytes by PML [1:0] (20h). ID code: ID code is recommended to set 4 bytes by IDL[1:0] = [01] and ID Code is stored into ID Data register by sequence ID Byte 0, 1, 2 and 3. If RX circuitry check ID code is correct, payload will be written into RX FIFO. In addition, user can set ID code error tolerance (0~ 7bit error) by setting ETH [2:0] during ID synchronization check. Payload: Payload length is programmable by FEP [11:0]. The physical FIFO depth is 64 bytes. A7128 also supports logical FIFO extension up to 4K bytes. CRC: In FIFO mode, if CRC is enabled (CRCS=1), 2-bytes of CRC value is self-generated and attached at the footer of the packet. In the same way, RX circuitry will check CRC value and show the result to CRC Flag Advanced FIFO mode A7128 supports to self generated MAC header to form an advanced FIFO mode by enabling FCL[1:0] and ENRL. Therefore, A7128 can support ACK FIFO (FCB1~FCB3) and dynamic FIFO length depending on configurations. 66

67 auto ack/resend dynamic FIFO Preamble ID code FCB FEP Payload (CRC) 4 bytes 4 bytes 1~4 bytes 1 2 bits Phy. 64 bytes 2 bytes PHY H eader (self-generated) M AC H eader (self-generated) Figure 16.2 TX packet format of advanced FIFO mode. FCB: If FCL[1:0] 00, FCB header is enabled to support ACK FIFO by (FCB1~FCB3). The FCB is frame control byte. FCB0 is NOT allowed to program but carry a dedicated header (00111b) and SID [2:0] (Serial ID of packet number). FCB1~3 are used for customized information in FCB field. FCB FCB 0 FCB 1 FCB 2 FCB 3 Figure 16.3 FCB (Frame Control Field) FEP: If ENRL = 1, A7128 supports dynamic FIFO. FEP [11:0] is self-generated to add into TX packet. In RX side, FEP[11:0] of the coming TX packet will be detected and stored into LENF [11:0] register. HEC: If HECS = 1, A7128 supports to self-generated a HEC byte which is a local CRC-8 of the MAC header. This HEC byte is an optional feature to calculate CRC result of MAC Header. HEC is located at the end of the MAC header. MAC header Header CRC Preamble ID code FCB FEP HEC Payload (CRC) 4 bytes 4 bytes 1~4 bytes 12 b its 1 byte Phy. 64 bytes 2 bytes PHY H eader (self-generated) M A C H eader (self-generated) 16.2 Bit Stream Process in FIFO mode A7128 supports 3 optional bit stream process for payload in FIFO mode, they are, (1) CCITT-16 CRC (2) (7, 4) Hamming FEC (3) Data Whitening by XOR PN7 (7-bits Pseudo Random Sequence). The initial seed of PN7 is set by WS [6:0] CRC (Cyclic Redundancy Check): 1. CRC is enabled by CRCS= 1. TX circuitry calculates the CRC value of payload (preamble and ID code are excluded) and transmits 2-bytes CRC value after payload. 2. RX circuitry checks CRC value and shows the result to CRCF. If CRCF=0, received payload is correct, else error occurred. FEC (Forward Error Correction): 1. FEC is enabled by FECS= 1. Payload and CRC value (if CRCS=1) are encoded by (7, 4) Hamming code. 2. Each 4-bits (nibble) of payload is encoded into 7-bits code word and delivered out automatically. (ex., 64 bytes payload will be encoded to 128 code words, each code word is 7 bits.) 67

68 3. RX circuitry decodes received code words automatically. Each code word can correct 1-bit error. Once 1-bit error occurred, FECF=1 (00h). Data Whitening: 1. Data whitening is enabled by WHTS= 1. Payload and CRC value (if CRCS=1) or their encoded code words (if FECS=1) are encrypted by bit XOR operation with PN7. The initial seed of PN7 is set by WS [6:0]. 2. RX circuitry decrypts received payload and 2-bytes CRC (if CRCS=1) automatically. Please noted that user shall set the same WS [6:0] (22h) to TX and RX Transmission Time Based on CRC and FEC options, the transmission time are different. See table 16.1 for details. Data Rate = 2 Mbps Data Rate (Mbps) Preamble (bits) ID Code (bits) Payload (bits) CRC (bits) FEC Transmission Time / Packet Disable Disable 576 bit X 0.5 us = 288 us bits Disable 592 bit X 0.5 us = 296 us Disable 512 x 7 / bit X 0.5 us = 480 us x 7 / x 7 / bit X 0.5 us = 494 us Table 16.1 Transmission time of 2 Mbps data rate Data Rate = 1 Mbps Data Rate (Mbps) Preamble (bits) ID Code (bits) Payload (bits) CRC (bits) FEC Transmission Time / Packet Disable Disable 576 bit X 1.0 us = 576 us bits Disable 592 bit X 1.0 us = 592 us Disable 512 x 7 / bit X 1.0 us = 960 us x 7 / x 7 / bit X 1.0 us = 988 us Table 16.2 Transmission time of 1 Mbps data rate 16.4 Usage of TX and RX FIFO In application points of view, A7128 supports 3 options of FIFO arrangement. (1) Easy FIFO (2) Segment FIFO (3) FIFO Extension For FIFO operation, A7128 supports Strobe command to reset TX and RX FIFO pointer as shown below. User can refer to section 10.5 for FIFO write pointer reset and FIFO read pointer reset. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description x x X x FIFO write pointer reset (for TX FIFO) x x X x FIFO read pointer reset (for RX FIFO) FIFO Register I (Address: 03h) Name W FEP7 FEP6 FEP5 FEP4 FEP3 FEP2 FEP1 FEP0 Reset

69 FIFO Register II (Address: 04h) Name W FPM1 FPM0 PSA5 PSA4 PSA3 PSA2 PSA1 PSA0 Reset FIFO DATA Register (Address: 05h) Name R/W FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0 Reset Easy FIFO In Easy FIFO, max FIFO length is 64 bytes. FIFO length is equal to ( FEP [7:0] +1 ). User just needs to control FEP [7:0] (03h) and disable PSA and FPM as shown below. Register setting TX RX Control Registers FIFO Length (byte) FIFO Length (byte) FEP[7:0] (03h) PSA[5:0] (04h) FPM[1:0] (04h) 1 1 0x x x0F x1F x3F 0 0 Table 16.3 Control registers of Easy FIFO Procedures of TX FIFO Transmitting 1. Initialize all control registers (refer A7128 reference code). 2. Set FEP [7:0] = 0x3F for 64-bytes FIFO. 3. Refer to Figure 11.2 and Figure Send Strobe command TX FIFO write pointer reset. 5. MCU writes 64-bytes data to TX FIFO. 6. Send TX Strobe Command. 7. Done. Procedures of RX FIFO Reading 1. When RX FIFO is full, WTR (or FSYNC) can be used to trigger MCU for RX FIFO reading. 2. Send Strobe command RX FIFO read pointer reset. 3. MCU read 64-bytes from RX FIFO. 4. Done. 69

70 Figure 16.3 Easy FIFO Segment FIFO In Segment FIFO, TX FIFO length is equal to (FEP [7:0] - PSA [5:0]+1). FPM [1:0] should be zero. This function is very useful for button applications. In such case, each button is used to transmit fixed code (data) every time. During initialization, each fixed code is written into corresponding segment FIFO once and for all. Then, if button is triggered, MCU just assigns corresponding segment FIFO (PSA [5:0] and FEP [7:0]) and issues TX strobe command. If TX FIFO is arranged into 8 segments, each TX segment and RX FIFO length are 8 bytes TX Segment PSA FEP FIFO Length (byte) PSA[5:0] (04h) Control Registers FEP[7:0] (03h) FPM[1:0] (04h) 1 PSA1 FEP1 8 0x00 0x PSA2 FEP2 8 0x08 0x0F 0 3 PSA3 FEP3 8 0x10 0x PSA4 FEP4 8 0x18 0x1F 0 5 PSA5 FEP5 8 0x20 0x PSA6 FEP6 8 0x28 0x2F 0 7 PSA7 FEP7 8 0x30 0x PSA8 FEP8 8 0x38 0x3F 0 RX FIFO Length (byte) PSA[5:0] (04h) Control Registers FEP[7:0] (03h) FPM[1:0] (04h) 8 0 0x07 0 Table 16.4 Segment FIFO is arranged into 8 segments Procedures of TX FIFO Transmitting 1. Initialize all control registers (refer A7128 reference code). 2. Refer to Figure 11.2 and Figure 11.3 (in chapter 11). 3. Send Strobe command TX FIFO write pointer reset. 4. MCU writes fixed code into corresponding segment FIFO once and for all. 5. To consign Segment 1, set PSA = 0x00 and FEP= 0x07 To consign Segment 2, set PSA = 0x08 and FEP= 0x0F 70

71 To consign Segment 3, set PSA = 0x10 and FEP= 0x17 To consign Segment 4, set PSA = 0x18 and FEP= 0x1F To consign Segment 5, set PSA = 0x20 and FEP= 0x27 To consign Segment 6, set PSA = 0x28 and FEP= 0x2F To consign Segment 7, set PSA = 0x30 and FEP= 0x37 To consign Segment 8, set PSA = 0x38 and FEP= 0x3F 6. Send TX Strobe Command. 7. Done. Procedures of RX FIFO Reading 1. When RX FIFO is full, WTR (or FSYNC) is used to trigger MCU for RX FIFO reading. 2. Send Strobe command RX FIFO read pointer reset. 3. MCU read 8-bytes from RX FIFO. 4. Done. Figure 16.4 Segment FIFO Mode 71

72 FIFO Extension In FIFO Extension, FIFO length is equal to (FEP [7:0] +1). PSA [5:0] shall be zero, and FPM [1:0] is used to set FIFO Pointer Flag (FPF) to MCU. FIFO extension could be set up to 256 bytes by FEP [7:0] with different FPF trigger conditions. Be notice, setting of SPI data rate is important to prevent error operation of FIFO extension. The min. SPI data rate shall be equal or greater than (A7128 data rate + 500Kbps) and refer Table 16.4 and 16.5 for max. SPI Data Rate. If A7128 data rate = 2Mbps and FIFO extension = 256 bytes. TX RX Control Registers FIFO Length (byte) 256 FPF Trigger Condition Max. SPI Data Rate FIFO Length (byte) FPF Trigger Condition Max. SPI Data Rate FEP[7:0] FPM[1:0] PSA[5:0] Delta = Mbps Delta = Mbps 00 0 Delta = Mbps Delta = Mbps 01 0 Delta = Mbps 256 Delta = Mbps 0xFF 10 0 Delta = 16 8 Mbps Delta = 48 8 Mbps 11 0 Table 16.5 How to set FIFO extension when A7128 is at 2Mbps data rate If A7128 data rate = 1Mbps and FIFO extension = 256 bytes. TX RX Control Registers FIFO Length (byte) 256 FPF Trigger Condition Max SPI Data Rate FIFO Length (byte) FPF Trigger Condition Max SPI Data Rate FEP[7:0] FPM[1:0] PSA[5:0] Delta = Mbps Delta = Mbps 00 0 Delta = 08 8 Mbps Delta = 56 8 Mbps 01 0 Delta = 12 5 Mbps 256 Delta = 52 5 Mbps 0xFF 10 0 Delta = 16 4 Mbps Delta = 48 4 Mbps 11 0 Table 16.6 How to set FIFO extension when A7128 is at 1Mbps data rate Please refer to AMICCOM s reference code (FIFO extension) for details. Procedures of TX FIFO Extension 1. Initialize all control registers (refer A7128 reference code). 2. Set FEP [7:0] = 0xFF for 256-bytes FIFO extension. 3. Set FPM [1:0] = 11 for FPF trigger condition. 4. Set CKO Register = 0x12 5. Send Strobe command TX FIFO write pointer reset. 6. MCU writes 1 st 64-bytes TX FIFO. 7. Send TX Strobe command. 8. MCU monitors FPF from A7128 s CKO pin. 9. FPF triggers MCU to write 2 nd 48-bytes TX FIFO. 10. Monitor FPF. 11. FPF triggers MCU to write 3 rd 48-bytes TX FIFO. 12. Monitor FPF. 13. FPF triggers MCU to write 4 th 48-bytes TX FIFO. 14. Monitor FPF. 15. FPF triggers MCU to write 5 th 48-bytes TX FIFO. 16. Done. 72

73 Figure 16.5 TX FIFO Extension Procedures of RX FIFO Reading 1. Initialize all control registers (refer A7128 reference code). 2. Set FEP [7:0] = 0xFF for 256-bytes FIFO extension. 73

74 3. Set FPM [1:0] = 11b for FPF trigger condition. 4. Set CKO Register = 0x12 5. Send Strobe command RX FIFO read pointer reset. 6. Send RX Strobe command. 7. MCU monitors FPF from A7128 s CKO pin. 8. FPF triggers MCU to read 1 st 48-bytes RX FIFO. 9. Monitor FPF. 10. FPF triggers MCU to read 2 nd 48-bytes RX FIFO. 11. Monitor FPF. 12. FPF triggers MCU to read 3 rd 48-bytes RX FIFO. 13. Monitor FPF. 14. FPF triggers MCU to read 4 th 48-bytes RX FIFO. 15. Monitor FPF. 16. FPF triggers MCU to read 5 th 48-bytes RX FIFO. 17. Monitor WTR falling edge or WTR = low, read the rest 16-bytes RX FIFO 18. Done. 74

75 Figure 16.6 RX FIFO Extension Mode 75

76 17. ADC (Analog to Digital Converter) A7128 has built-in 8-bits ADC that supports multi-functions to do temperature measurement, RSSI, carrier detection and convert external analog voltage (BP_RSSI pin) into 8-bits digital value. User can set FSARS (1Fh) to select 4MHz or 8MHz ADC clock (F ADC). The converting time is 20 x ADC clock periods. FSARS = 0 is recommended to result less power comsumption. Bit Description XADS (1Fh) RSS (1Fh) Standby mode RX mode 0 0 Temperature None 0 1 None RSSI / Carrier detect 1 x External voltage via BP_RSSI pin None Table 17.1 Setting of ADC external voltage measurement. Relative Control Register Mode Control Register (Address: 01h) R DDPC ARSSI AIF CD WORE FMT FMS ADCM Name W DDPC ARSSI AIF DFCD WORE FMT FMS ADCM Reset RX Gain Register IV (Address: 1Dh) Name W ERSSM AVSEL1 AVSEL0 MVSEL1 MVSEL0 MHC LHC NS1 Reset RSSI Threshold Register (Address: 1Eh) R ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Name W RTH7 RTH6 RTH5 RTH4 RTH3 RTH2 RTH1 RTH0 Reset ADC Control Register (Address: 1Fh) Name W RSM1 RSM0 -- RADC FSARS XADS RSS CDM Reset Temperature Measurement A7128 has built-in thermal sensor. Combined with 8-bits ADC, it can be used to monitor the relative environment temperature. Below is the measurement procedure: 1. Set RSS= 0 (1Fh), FSARS= 0 (1Fh). 2. Enter Standby mode. 3. Set ADCM= 1 (01h). A7128 will enable relative temperature measurement automatically. 4. After measurement done, ADCM is auto clear. 5. User can read digital temperature value from ADC [7:0] (1Eh). 76

77 17.2 RSSI Measurement A7128 has built-in 8-bits digital RSSI to detect RF signal strength. After measurement done, RSSI is stored in ADC [7:0] (1Eh). The more signal power, the larger RSSI value.below is the measurement procedure: Auto RSSI measurement for TX Power 1. Set wanted F RXLO (Refer to chapter 14). 2. Set RSS= 1 (1Fh), FSARS= 0 (1Fh). 3. Enable MVSEL = [01] (1Dh) and RADC = [1] (1Fh) to do 16-times average RSSI measurement. 4. Set ARSSI= 1 (01h). 5. Send RX Strobe command. 6. Once entering into RX mode, A7128 executes 16-times average measurement repeatedly. 7. Once A7128 leaves RX mode, user can read digital RSSI value from ADC [7:0] (1Eh) for TX power. Be notice, in step 7, if A7128 is set in direct mode, once the received packet is completed, MCU shall ask A7128 to leave RX mode within 40 us to prevent RSSI inaccuracy. Strobe CMD (SCS,SCK,SDIO) RX-Strobe RX Mode MCU Read ADC[7:0] (1Eh) RF-IN 130 us Received Packet Read 8-bits RSSI value GIO1 Pin - WTR (GPIO1S[3:0]=0000) GIO2 Pin - FSYNC (GPIO2S[3:0]=0001) T0 T1 T2 T3 T4 T5 T0-T1: Settling Time from PLL to RX mode T2-T3: Receiving Packet (at least 20 bytes) T3-T4: Leave RX mode T3-T4: MCU read RSSI ADC [7:0](1Eh) Figure 17.1 Timing chart of Auto RSSI measurement for TX Power: Auto RSSI measurement for Background Power 1. Set wanted F RXLO (Refer to chapter 14). 2. Set RSS= 1 (1Fh), FSARS= 0 (1Fh). 3. Enable MVSEL = [01] (1Dh) and RADC = [1] (1Fh) to do 16-times average RSSI measurement. 4. Set ARSSI= 1 (01h). 5. Send RX Strobe command. 6. MCU delays min. 300us. 7. MCU disable ARSSI = 0 (01h). 8. Read digital RSSI value from ADC [7:0] (1Eh) to get background power. 9. Send Strobe command to ask A7128 to leave RX mode. 77

78 Strobe CMD (SCS,SCK,SDIO) RX-Strobe MCU Read ADC[7:0] (1Eh) RF-IN No Packet GIO1 Pin - WTR (GPIO1S[3:0]=0000) GIO2 Pin - FSYNC (GPIO2S[3:0]=0001) Min. 300 us Read 8-bits RSSI value T0 T1 T2 T3 T0-T1: MCU Delay Loop from PLL to RX mode for RSSI measurment T1-T2: MCU reads RSSI ADC [7:0](1Eh) T3 : Leave RX mode Figure 17.2 Timing chart of Auto RSSI measurement for Background Power. ADC (decade) 140 TX power VS ADC R Input TX power (dbm) Figure 17.3 Typical RSSI curve at 915MHz band. 78

79 17.3 Carrier Detect Base on RSSI measurement, user can extend its application to do carrier detect (CD). If CD is triggered, its output can be programmed to GIO1 or GIO2 pin to inform MCU occupied channel or coming TX packet. Below is the detection procedure: 1. Set RTH (1Eh) for RSSI higher threshold by user s definition. 2. Recommend to set RSM = [11] (1Fh) to get RSSI lower threshold, RTL = RTH RSM. 3. Set GIO1S = [0010] (0Bh) for GIO1 pin to output CD signal. 4. Follow procedure of auto RSSI measurement for Background Power. (4-1) Set wanted F RXLO (Refer to chapter 14). (4-2) Set RSS= 1 (1Fh), FSARS= 0 (1Fh). (4-3) Enable MVSEL = [01] (1Dh) and RADC = [1] (1Fh) to do 16-times average RSSI measurement. (4-4) Set ARSSI= 1 (01h). (4-5) Send RX Strobe command. (4-6) MCU enables time out timer (min. 300 us). 5. MCU checks GIO1 pin for carrier detect (CD) signal until time out. 6. Send Strobe command to ask A7128 to leave RX mode. Be notice, In step 5, In step 1, CD=1 if measured RSSI RTH. That means this channel is occupied (or coming packet). CD=0 if measured RSSI RTL. That means this channel is clear (or no packet detected). User can define occupied channel power by set RTH. User can refer below table to set threshold point (RTH) in different applications. RSSI Range (db) Max -50 db Min -100 db RH [7:0] RL [7:0] Input Power (dbm) Read address 1Bh Read address 1Ch Digital RSSI Value -58 ~ (3RH- RL) / 2-64 ~ RH -70 ~ (RH + RL) / 2-76 ~ RL -82 ~ (3RL - RH) / 2 Note Formula of digital RSSI values is just approximate for reference External Voltage Measurement BP_RSSI pin can be programmed to be input pin for external voltage measurement which range is 0.3V ~ 1.5V. Below is the measurement procedure: 1. Connect external voltage input to BP_RSSI pin. 2. Set XADS= 1 (1Fh). 3. Enter standby mode. 4. Set ADCM= 1 (01h) to enable external voltage measurement. 5. After measurement done, ADCM is auto clear. 6. User can read digital external voltage value from ADC [7:0] (1Eh). 79

80 18. WOR Function A7128 has an internal RC oscillator to supports WOR (Wake On RX) and TWOR (Timer Wake On RX) function. RCOSC_E (09h) is used to enable RC oscillator. WORE (01h) is used to enable WOR function and TWOR_E (09h) is used to enable TWOR function. After done calibrations of RC oscillator, WOR and TWOR function can be operated from -40 to 85. Parameter Min Typ Max Unit Note Calibrated Freq. 3.8K 4.2K Hz Sleep period ms [( WOR_SL [9:0] ) +1] x 7.8 ms RX period ms [( WOR_AC [5:0] ) +1] x 244 us Operation temperature After calibration WOR Function When WOR is enabled (WORE = 1 and RCOSC_E =1), A7128 periodically wakes up from sleep and listen (auto-enter RX mode) for incoming packets without MCU interaction. Therefore, A7128 will stay in sleep mode based on WOR_SL timer and RX mode based on WOR_AC timer unless a packet is received. The internal RC oscillator used for the WOR function varies with temperature and CMOS process deviation. In order to keep the frequency as accurate as possible, the RC oscillator shall be calibrated (CALWC=1) whenever possible. After done calibrations, MCU shall set WORE=1 and issue sleep strobe command to start WOR function. After a period (WOR_SL) in sleep mode, the device goes to RX mode to check coming packets. And then, A7128 is back to sleep mode for the next WOR cycle. To end up WOR function, MCU just needs to set WORE = 0. Strobe CMD (SCS,SCK,SDIO) sleep No Command Required Strobe cmd RF In Pin Coming packet GIO1 -- WTR GIO1S[3:0]=0000 Sleep WOR_SL[9:0] RX Sleep WOT_SL[9:0] RX Start WOT (sleep strobe) End WOT (set WOTE = 0) 80

81 20.2 TWOR Function The RC oscillator inside A7128 can also be used to supports programmable TWOR (Timer Wake-On, TWOR_E=1) function which enables A7128 to output a periodic square wave from GIO1 (or GIO2). The duty cycle of this square wave is set by WOR_AC (08h) or WOR_SL (08h and 07h) regarding to TSEL (09h). User can use this square wave to wake up MCU or other purposes. 19. Battery Detect A7128 has built-in battery detector to check supply voltage (REGI pin). The detect range is 2.1V ~ 2.8V into 8 levels. Battery Detect Register (Address: 2Ch) R -- RGV1 RGV0 BDF BVT2 BVT1 BVT0 BD_E Name W ECKS RGV1 RGV0 QDS BVT2 BVT1 BVT0 BD_E Reset BVT [2:0]: Battery Voltage Threshold Select. [000]: 2.1V, [001]: 2.2V. [010]: 2.3V. [011]: 2.4V. [100]: 2.5V. [101]: 2.6V. [110]: 2.7V. [111]: 2.8V. ( Typical +-0.1V detection inaccuracy.) Below is the procedure of battery detect for low voltage detection (ex., below 2.1V): 1. Set A7128 in idle, standby or PLL mode. 2. Set BVT (2Ch) = [000] and enable BD_E (2Ch) = After 5 us, BD_E is auto clear. 4. Check BDF (2Ch). If REGI pin > 2.1V, BDF = 1. Else, BDF = 0. 81

82 20. Auto-act and Auto-resend A7128 supports Auto-resend and Auto-ack (set EAK = 1 to enable Auto-ack and set EAR = 1 to enable Auto-resend) for easy two-way communication. In application points of view, comibed with Basic FIFO, Dynamic FIFO, FCB, there are several operation options below Basic FIFO plus auto-ack auto-resend Set EAF = 0, EAK = 1 and EAR = 1 to enable auto-ack and auto-resend. Please refer to the below TX and ACK packet format of the sender and the receiver site respectively Advanced FIFO plus auto-ack and auto-resend In addition to set EAF = 0, EAK = 1 and EAR = 1 to enable auto-ack and auto-resend. User can also enable an optional MAC header (FCB field) in the TX packet together with auto-ack and auto resend scheme. Please refer to the below TX and ACK packet format of the sender and the receiver site. 82

83 83

84 20.3 WTR Behavior during Auto-ack and Auot-resend If Auto-ack and Auto-resend are enabled (EAR = EAK = 1), WTR represents different meanings when it is output to GIO1 and GIO2. See below timing diagrams for details. Master site and enable Auto-resend. Slave site and enable Auto-ack. Refer to 3Bh for ARD[7:0] setting. Refer to 3Ah for EAK (enable Auto-ack). Refer to 3Ah for EAR (enable Auto-resend). Refer to 3Ah for EAK (enable Auto-ack). Refer to 0Bh for VPM and VPW. 84

85 20.4 Examples of Auto-ack and Auto-resend Once EAK and EAR (0x3A) are enabled, below are 3 common cases (assume to ARD (3Bh) = 800 us) in two-way radio communications. <Case1> Always success <Case2> Success in second packet 85

86 <Case3> always resend failure 86

87 21. Application Circuit (Reference Only) 21.1 MD7128-A90 (915MHz Band) 1. A7128 schematic for RF layouts with single ended 50Ω RF output. 2. Y1 is a 16MHz crystal with 18 pf Cload. (Xtal C-load compensated capacitor is built in A7128 by CSXTAL[4:0], 1Bh) 87

88 21.2 MD7128-A80 (868MHz Band) Use Lump Elements for Matching Circuit C15 2.2uF J3 1 2 CON/2P 2.0 J2 1 2 CON/2P 2.0 C1 120pF C5 NC C8 2.2uF REGOA VIN CKO GIO2 GIO1 J4 RFIN C17 2pF C16 2pF L6 8.2nH L5 8.2nH C18 3.9pF L4 9.1nH C19 5pF C21 1pF C10 27pF C11 0.1uF L3 33nH C6 100pF C2 L2 12nH R1 10 REGOA 1.5nF C4 C12 0.1uF 100pF BPBG C7 100pF RSSI 1 VDA2 5 C3 560pF C14 10nF RSSI BPBG RFI RFO VDA2 R2 1K 20 VDA1 VT 6 19 REGI GND 7 18 CKO VDDPLL 8 17 GIO2 A7128PKG XI 9 16 GIO1 XO 10 GND SDIO DVDD SCK SCS Y1 U MHz SDIO VDD_D SCK SCS C9 2.2uF R3 NC X_CLK VIN GND CKO GIO2 GIO1 SDIO SCK SCS GND X_CLK J CON/10P VDPLL REGOA C13 0.1uF 1. A7128 schematic for RF layouts with single ended 50Ω RF output. 2. Y1 is a 16MHz crystal with 18 pf Cload. (Xtal C-load compensated capacitor is built in A7128 by CSXTAL[4:0], 1Bh) 88

89 21.3 MD7128-A40 (433MHz Band) Use Lump Elements for Matching Circuit J3 1 2 J2 1 2 CON/2P 2.0 CON/2P 2.0 C1 120pF C5 NC C8 2.2uF REGOA VIN C15 2.2uF CKO GIO2 GIO1 J4 RFIN C17 10pF C16 10pF L6 27nH L5 18nH C18 12pF L4 18nH C19 12pF C21 1.5pF C10 27pF C11 0.1uF L3 100nH C6 100pF C2 1.5nF RSSI1 L2 47nH BPBG 2 C4 100pF R1 10 C12 C7 0.1uF 100pF REGOA VDA2 5 C3 560pF C14 10nF 3 4 RSSI BPBG RFI RFO VDA2 R2 1K 20 VDA1 VT 6 19 REGI GND 7 18 CKO VDDPLL 8 17 GIO2 XI 9 16 A7128PKG GIO1 XO 10 GND SDIO DVDD SCK SCS U Y1 16MHz SDIO VDD_D SCK SCS C9 2.2uF R3 NC X_CLK VIN GND CKO GIO2 GIO1 SDIO SCK SCS GND X_CLK J CON/10P 2.0 VDPLL REGOA C13 0.1uF 1. A7128 schematic for RF layouts with single ended 50Ω RF output. 2. Y1 is a 16MHz crystal with 18 pf Cload. (Xtal C-load compensated capacitor is built in A7128 by CSXTAL[4:0], 1Bh) 89

90 22. Abbreviations ADC AIF AFC BER BW CD CHSP CRC DC FEC FIFO FSK ID IF ISM LO MCU PFD PLL POR RX RXLO RSSI SPI SYCK TWOR TX TXRF VCO XOSC XREF XTAL Analog to Digital Converter Auto IF Automatic Frequency Compensation Bit Error Rate Bandwidth Carrier Detect Channel Step Cyclic Redundancy Check Direct Current Forward Error Correction First in First out Frequency Shift Keying Identifier Intermediate Frequency Industrial, Scientific and Medical Local Oscillator Micro Controller Unit Phase Frequency Detector for PLL Phase Lock Loop Power on Reset Receiver Receiver Local Oscillator Received Signal Strength Indicator Serial to Parallel Interface System Clock for digital circuit Timer Wireless Wakeup System Transmitter Transmitter Radio Frequency Voltage Controlled Oscillator Crystal Oscillator Crystal Reference frequency Crystal 23. Ordering Information Part No. Package Units Per Reel / Tray A71C28AQFI/Q QFN20L, Pb Free, Tape & Reel, K A71C28AQFI QFN20L, Pb Free, Tray, EA A71C28AH Die form, EA 90

91 24. Package Information QFN 20L (4 X 4 X 0.8mm) Outline Dimensions unit: inches/mm TOP VIEW BOTTOM VIEW D 0.25 C D e E E2 L C e b 0.10 M C A B // 0.10 C A1 A Seating Plane C A3 y C Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A REF REF B D D E E e BSC 0.50 BSC L Y

92 25. Top Marking Information A71C28AQFI Part No. :A71C28AQFI Pin Count :20 Package Type : QFN Dimension :4*4 mm Mark Method : Laser Mark Character Type :Arial J F K Y Y W W X D B I C17128 N N N N N N N N N A L C2 G C3 v CHARACTER SIZE : (Unit in mm) A : 0.55 B : 0.36 C1 : 0.25 C2 : 0.3 C3 : 0.2 D : 0.03 A1 : 0.75 B2 : 0.7 Y Y W W X N N N N N N N N N : DATECODE :PKG HOUSE ID : LOT NO. (max.9 characters) F=G I=J K=L

93 26. Reflow Profile 93

94 27. Tape Reel Information Cover / Carrier Tape Dimension Unit: mm TYPE P A0 B0 P0 P1 D0 D1 E F W 20 QFN 4* QFN 4* QFN 5* QFN3*3 / DFN SSOP SSOP TYPE K0 t COVER TAPE WIDTH 20 QFN (4X4) QFN (4X4) QFN (5X5) QFN3*3 / DFN SSOP SSOP

95 REEL DIMENSIONS Unit: mm TYPE G N T M D K L R 20 QFN(4X4) 24 QFN(4X4) 32 QFN(5X5) QFN(3X3) / DFN / REF 18.2(MAX) 1.75± / ± SSOP 24 SSOP / REF 22.4(MAX) 1.75± / ± / /

96 28. Product Status Data Sheet Identification Product Status Definition Objective Planned or Under Development This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary Engineering Samples and First Production This data sheet contains preliminary data, and supplementary data will be published at a later date. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. No Identification Noted Full Production This data sheet contains the final specifications. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Obsolete Not In Production This data sheet contains specifications on a product that has been discontinued by AMICCOM. The data sheet is printed for reference information only. Headquarter A3, 1F, No.1, Li-Hsin Rd. 1, Hsinchu Science Park, Taiwan Tel: RF ICs AMICCOM Shenzhen Office Rm., 2003, DongFeng Building, No. 2010, Shennan Zhonglu Rd., Futian Dist., Shenzhen, China Post code: Web Site 96