Title - ZU111 Validation Plan/Procedure/Analysis
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1 Title - ZU111 Validation Plan/Procedure/Analysis Customer Xilinx Program ZU111 Lead Engineer Brian Forsse - Brian.Forsse@xilinx.com Phone - (408) Infineon Technologies Jay Radhakrishnan Sr. Field Applications Engineer Infineon Technologies 640 N. McCarthy Blvd Milpitas CA Tony Ochoa Sr. Product Marketing Manager Tony.ochoa@infineon.com
2 Table of Contents Title - ZU111 Validation Plan/Procedure/Analysis... 1 Introduction... 7 Documents... 7 Test Equipment... 7 DC/DC Converter Overview... 8 Programming... 8 Power Sequencing... Error! Bookmark not defined. DCDC Converter Validation Results... 9 Acceptance test parameters are as follows:... 9 VCCINT_IO_BRAM_PS_SDFEC VCC1V VCCINT_AMS UTIL_3V UTIL_2V MGT1V MGTRAVCC VCC1V DAC_AVTT FMC_VADJ MGT1V VCCINT MGTAVCC DAC_AVCCAUX ADC_AVCCAUX UTIL_1V UTIL_5V ADC_AVCC DAC_AVCC PL_DDR4_VTT PS_DDR4_VTT UTIL_3V
3 AMS_CLK_VCC3V
4 Table 1 Document and File Description... 7 Table 2 Test Equipment... 7 Table 3 - Ref Des Description... 8 Table 4 VCCINT_IO_BRAM_PS_SDFEC Results Table 5 VCC1V8 Results Table 6 VCCINT_AMS Results Table 7 UTIL_3V3 Results Table 8 UTIL_2V5 Results Table 9 MGT1V2 Results Table 10 MGTRAVCC Results Table 11 VCC1V2 Results Table 12 DAC_AVTT Results Table 13 FMC_VADJ Results Table 14 MGT1V8 Results Table 15 VCCINT Results Table 16 MGTAVCC Results Table 17 DAC_AVCC_AUX Results Table 18 ADC_AVCC_AUX Results Table 19 UTIL_1V13 Results Table 20 UTIL_5V0 Results Table 21 ADC_AVCC Results Table 22 DAC_AVCC Results Table 23 PL_DDR4_VTT Results Table 24 PS_DDR4_VTT Results Table 25 UTIL_3V5 Results Table 26 AMS_CLK_VCC3V3 Results
5 Figure 1 - VCCINT_IO_BRAM_PS_SDFEC DC Ripple, 15A Figure 2 - VCCINT_IO_BRAM_PS_SDFEC ac ripple load Figure 3 - VCCINT_IO_BRAM_PS_SDFEC ac ripple release Figure 4 - VCCINT_IO_BRAM_PS_SDFEC Jitter, 10A... Error! Bookmark not defined. Figure 5 - VCC1V8 DC Ripple, 2A Figure 6 - VCC1V8 ac ripple load Figure 7 - VCC1V8 ac ripple release Figure 8 - VCC1V8 Jitter, 2A Figure 9 - VCCINT_AMS DC Ripple, 7A Figure 10 - VCCINT_AMS ac ripple load Figure 11 - VCCINT_AMS ac ripple release Figure 12 VCCINT_AMS Jitter, 7A Figure 13 - UTIL_3V3 DC Ripple, 10A Figure 14 - UTIL_3V3 ac ripple load Figure 15 - UTIL_3V3 ac ripple unload Figure 16 - UTIL_3V3 Jitter, 10A Figure 17 - UTIL_2V5 DC Ripple, 2A Figure 18 - UTIL_2V5 ac ripple load Figure 19 - UTIL_2V5 ac ripple release Figure 20 - UTIL_2V5 Jitter... Error! Bookmark not defined. Figure 21 - MGT1V2 DC Ripple Figure 22 - MGT1V2 ac ripple load Figure 23 - MGT1V2 ac ripple release Figure 24 - MGT1V2 Jitter, 6A Figure 25 - MGTRAVCC DC Ripple, 0.5A Figure 26 - MGTRAVCC ac ripple load Figure 27 - MGTRAVCC ac ripple release Figure 28 - VCC1V2 DC Ripple, 5A Figure 29 - VCC1V2 ac ripple load Figure 30 - VCC1V2 ac ripple release Figure 31 - VCC1V2 Jitter, 5A Figure 32 - DAC_AVTT DC Ripple, 0.5A Figure 33 - DAC_AVTT ac ripple load Figure 34 - DAC_AVTT ac ripple release Figure 35 - DAC_AVTT Jitter, 0.5A Figure 36 - FMC_VADJ DC Ripple, 3A Figure 37 - FMC_VADJ ac ripple load Figure 38 - FMC_VADJ ac ripple release Figure 39 - FMC_VADJ Jitter, 3A Figure 40 - MGT1V8 DC Ripple, 0.5A Figure 41 - MGT1V8 ac ripple load Figure 42 - MGT1V8 ac ripple release
6 Figure 43 - VCCINT Ripple, 20A Figure 44 - VCCINT ac ripple load Figure 45 - VCCINT ac ripple release Figure 46 - VCCINT Jitter, 0A... Error! Bookmark not defined. Figure 47 - MGTAVCC DC Ripple, 0.5A Figure 48 - MGTAVCC ac ripple load Figure 49 - MGTAVCC ac ripple release Figure 50 - MGTAVCC Jitter, 3A Figure 51 - DAC_AVCC_AUX DC Ripple, 0.5A Figure 52 DAC_AVCC_AUX ac ripple load Figure 53 DAC_AVCC_AUX ac ripple unload Figure 54 - ADC_AVCCAUX DC Ripple, 0.5A Figure 55 ADC_AVCCAUX ac ripple load Figure 56 ADC_AVCCAUX ac ripple unload Figure 57 ADC_AVCAUX Jitter, 2A Figure 58 - UTIL_1V13 DC Ripple, 1A Figure 59 - UTIL_1V13 ac ripple load Figure 60 - UTIL_1V13 ac ripple release Figure 61 - UTIL_1V13 Jitter, 1A Figure 62 - UTIL_5V0 DC Ripple, 2.1A Figure 63 - UTIL_5V0 ac ripple load Figure 64 - UTIL_5V0 ac ripple unload Figure 65 - UTIL_5V0 Jitter, 2.1A Figure 66 DAC_AVCC ac ripple Figure 67 - PL_DDR4_VTT DC Ripple, 3A Figure 68 - PL_DDR4_VTT ac ripple load Figure 69 - PL_DDR4_VTT ac ripple release Figure 70 - PL_DDR4_VTT Jitter, 3A Figure 71 - PS_DDR4_VTT DC Ripple, 3A Figure 72 - PS_DDR4_VTT ac ripple load Figure 73 - PS_DDR4_VTT ac ripple release Figure 74 - PS_DDR4_VTT Jitter, 3A Figure 75 - UTIL_3V5 DC Ripple, 3A Figure 76 - UTIL_3V5 ac ripple load Figure 77 - UTIL_3V5 ac ripple unload Figure 78 - AMS_CLK_VCC3V3 DC Ripple, 3A Figure 79 - AMS_CLK_VCC3V3 ac ripple load Figure 80 - AMS_CLK_VCC3V3 ac ripple unload
7 Introduction This document is used to record the power supply programming, bringup, and validation for Xilinx ZU111 platform. This document applies to Rev A hardware only. Documents The following documents are used for this validation plan. Table 1 Document and File Description Originato Title Description r Xilinx HW-Z1-ZCU111_ _PM Schematic Xilinx ZCU111_REVA_Patches Rev A PCB Rework Xilinx 70_ZCU111.brd Layout Infineon IRPS5401MXI04TRP_MTPplus5_0.85V_1.8V_0.85V_800k_Rev2_2.txt U53 Configuratio n Infineon IRPS5401MXI04TRP_MTPplus6_3.3V_2.5V_1.2V 0.85V_800k_Rev2_2.tx t U55 Configuratio n Infineon IRPS5401MXI04TRP_MTPplus7_1.2V_2.5V_1.8V_1.8V_800k_Rev2_2.txt U57 Configuratio n Xilinx ZCU111_REVA_Powerup Power Up Instructions Test Equipment The following is the test equipment used for validation purposes. Table 2 Test Equipment Item Manufacturer Function Model/Description 1 LTE Power Supply 2 Fluke DMM Agilent DMM 34401A 4 Tek Oscilloscope TDS5104B 5 Tek Differential Probe P Tek Passive Probe P6139A 7 N/A Coax Probe 8 Infineon Comms USB005 9 Infineon GUI Power Center 10 Chroma Electronic Load 7
8 DC/DC Converter Overview The below reference designators are the voltage regulators designed onto the ZU111 hardware and tested as part of the validation plan/procedure. The voltage rails associated with each are listed. Note there are multiple ref des associated with a few voltage rails due to the use of power stages. Table 3 - Ref Des Description Ref Des Manufacturer Schematic Page Voltage Rail U53 Infineon 47 VCCINT_IO_BRAM_PS_SDFEC VCC1V8 VCCINT_AMS U54 Infineon 48 *VCCINT_IO_BRAM_PS_SDFEC (power stage) U55 Infineon 49 UTIL_3V3 UTIL_2V5 MGT1V2 MGTRAVCC U56 Infineon 50 *UTIL_3V3 (power stage) U57 Infineon 51 VCC1V2 DAC_AVTT VADJ_FMC MGT1V8 U58 52 * VCC1V2 (power stage) U68 Infineon 54 VCCINT U70 Infineon 55 MGTAVCC U72 Infineon 56 DAC_AVCCAUX U74 Infineon 57 ADC_AVCCAUX U75 Infineon 58 UTIL_1V13 U76 Infineon 59 UTIL_5V0 U101 Intersil 60 ADC_AVCC U78 Intersil 60 DAC_AVCC U81 Infineon 61 PL_DDR_VTT U82 Infineon 61 PS_DDR_VTT U62 Infineon 71 UTIL_3V5 U100 Intersil 71 AMS_CLK_VCC3V3 Programming The programming procedure assumes a board populated with an IRPS5401, U53, U55, and U57, has parts pre-programmed. All others have no pre-programmed configuration in the NVM where applicable. Please confirm all REVA_PATCHES are complete. 8
9 DCDC Converter Validation Results The following sections document the DCDC converters with respect to the following test conditions and measurements. 1. DC Voltage a. All DC measurements are recorded by use of a true RMS DMM to ensure accuracy and validation with the GUI reported results. 2. DC Ripple (Steady-State) a. DC ripple is measured with a differential active probe or an analog coax probe (ac coupled) where precision noise floor measurements are required. Note o-scope offsets are in effect and absolute DC reference point must be measured by the DMM and are recorded as the DC voltage. Noise floor for active differential probes typically limit to 10mVpp. Noise floor for coax probes typically limit to just under 5mVpp. 3. ac transient response (Large Signal Analysis) a. All ac transient measurements are measured with respect to the valley/valley or peak/peak for loading and releasing events respectively. Note 0-scope offsets are in effect and absolute DC reference point must be measured by the DMM and are recorded as the DC voltage. 4. Current Sense Accuracy a. Where telemetry is available, the calibrated E-load is used to verify the telemetry reporting accuracy. 5. Protection (OCP) a. Where the programmability occurs, magnetic ratings on Isat allow, and test access allows, OCP protections are checked for accurate triggering. In some instances, the OCP rating may be artificially adjusted to check the operation of OCP but may not be the final programmed rating due to other HW limitations. 6. Sequence Timing Acceptance test parameters are as follows: 1. DC Ripple (updated per inputs 1/26/18) a. ADC_AVCC [STE required] i. 0.25mV,pp (0.12mV,pp original spec) b. DAC_AVCC [STE required] i. 0.40mV,pp (0.2mV,pp original spec) c. ADC_AVCCAUX i mV,pp (5.51mV,pp original spec) d. DAC_AVCCAUX [STE required] i. 2.00mV,pp (1.0mV,pp original spec) e. DAC_AVTT i. 8.94mV,pp (4.47mV,pp original spec) f. VCCINT_AMS i. 20mV,pp (10mV,pp original spec) g. MGTAVCC, MGTRAVCC, MGT1V2, MGT1V8 9
10 i. 12mV,pp 10mV,pp h. VCCINT_IO_BRAM_PS_SDFEC (VCCPSINT) i. 2%, 17mV,pp i. VCC1V8 i. 2%, 36mV,pp j. Others i. Combined within overall specification 2. Vac Transient a. ADC_AVCC (23.13mV), DAC_AVCC (23.13mV), DAC_AVCCAUX i. 25% step, 1A/us b. VCCINT_AMS (21.25mV), VCCINT (21.25mV) i. 25% step (6A given in last for AMS), 2A/us c. UTIL3V5 (87.5mV), AMS_CLK_VCC3V3 (82.5mV) i. 50% step, 1A/us d. DAC_AVTT (62.5mV), ADC_AVCCAUX (45mV), VCC1V8 (45mV), UTIL1V13 (28.25mV), MGT1V8 (45mV) i. 100% step, 1A/us e. MGTRAVCC (21.25mV) i. 50% step, 1A/us f. MGT1V2 (30mV) i. 2.5A step, 1A/us g. VCC1V2 (30mV) i. 3.0A step, 1A/us h. MGTAVCC (22.5mV) i. 1.5A step, 1A/us i. FMC_VADJ (45mV) i. 0.7A step (test to 2A), 1A/us 1. Connector requires 4A load ability on VADJ_FMC_BUS (before shunt) j. VCCINT_IO_BRAM_PS_SDFEC (VCCPSINT) i. ±2.5% 8A step (2A to 10A), 2.5A/us k. UTIL1V13 (56.5mV) i. 100% step (step size unknown), 1A/us l. UTIL3V3 (165mV), UTIL2V5 (125mV) i. 50% step, 1A/us m. UTIL5V0 (250mV) i. 900mA step (1.8A to 2.7A), 1A/us n. PL_DDR4_VTT (30mV), PS_DDR4_VTT (30mV) i. 40% step, 1A/us 3. OCP a. Where circuit allows, ensure OCP meets design b. Else, ensure ample margin to prevent for false OCP 4. Sequencing 10
11 a. POR (power on reset) guidelines met Design Change Recommendations Any design change recommendations are embedded within the subsections to follow and are denoted in RED. 11
12 VCCINT_IO_BRAM_PS_SDFEC Vin, 12V Vout, 0.85V Iout(pk), 15A Istep, 8A (2A to 10A) Iramp, 2.5A/us Vout Measurement Location, J46, C946 Load Test Location, J46 SW Node Measurement Location, L22 Jitter = 47ns (10A load) Bode Analysis At 0A load, Crossover Frequency is 72kHz with Phase Margin = 78deg and Gain Margin ~ -10dB 12
13 With 15A load, the crossover frequency is 59.5kHz with Phase Margin = 72 deg and Gain Margin = -10dB Config: IRPS5401MXI04TRP_MTPplus5_0.85V_1.8V_0.85V_800k_Rev2_2.txt Table 4 VCCINT_IO_BRAM_PS_SDFEC Results Measurement Result Pass/Fail Test Condition Notes Vout 0.846V Pass 0A DMM 15A DC Ripple 15.6mV 14.4mV Pass 0A 15A active probe across SP-Cap. Lower ripple at Isense 0.38A 5.50A 10.38A 15.00A Pass 0A 5A 10A 15A Vac(droop) 5.4mV Pass 2A to 10A Vac(overshoot) 9.4mV Pass 10A to 2A BGA pads. Telemetry/E-load 13
14 Figure 1 - VCCINT_IO_BRAM_PS_SDFEC DC Ripple, 0A Figure - VCCINT_IO_BRAM_PS_SDFEC DC Ripple, 15A 14
15 Figure 2 - VCCINT_IO_BRAM_PS_SDFEC Transient Load : 2-10A 15
16 Figure During 2-10A load step, the Vout excursion is around 5.4mV 16
17 Figure 3 - VCCINT_IO_BRAM_PS_SDFEC during the 10A 2A load release, Vout overshoot is around 9.4mV 17
18 VCC1V8 Vin, 12V Vout, 1.8V Iout(pk), 2A Istep, 2A Iramp, 1A/us Vout Measurement Location, J61, L38, C110 Load Test Location, J61 SW Node Measurement Location, L19 Jitter = 28.8ns (2A load) Config: IRPS5401MXI04TRP_MTPplus5_0.85V_1.8V_0.85V_800k_Rev2_2.txt Bode Analysis At 0 A Load, crossover frequency is 21.86kHz with Phase Margin at 60deg and Gain Margin of -23dB 18
19 At 2A load, crossover frequency of 22.13kHz with Phase Margin of 54 deg and Gain Margin of -23dB Table 5 VCC1V8 Results Measurement Result Pass/Fail Test Condition Notes Vout 1.8V Pass 0A DMM 2A DC Ripple 13.0mV Pass 0A Active probe 13.2mV 2A Isense 0.38A Pass 0A Telemetry/E-load 2.34A 2A Vac(droop) 36.0mV Pass 0A to 2A Vac(overshoot) 32.8mV Pass 2A to 0A 19
20 Figure 4 - VCC1V8 DC Ripple, 2A 20
21 Figure 5 - VCC1V8 ac ripple load 21
22 Figure 6 - VCC1V8 ac ripple release 22
23 Figure 7 - VCC1V8 Jitter, 2A 23
24 VCCINT_AMS Vin, 12V Vout, 0.85V Iout(pk), 7A Istep, 1.75A Iramp, 2A/uS Vout Measurement Location, C789, C119 Load Test Location, J62 SW Node Measurement Location, L20, L21 Jitter = 18.4ns (no load) Config: IRPS5401MXI04TRP_MTPplus5_0.85V_1.8V_0.85V_800k_Rev2_2.txt Bode Plot With 0A load, the crossover frequency is around 50kHz where Phase Margin is 62.4 deg and Gain Margin is around -14dB With 7A Load, the crossover frequency is around 56.6kHz with Phase Margin around 53.5 deg and Gain Margin is around -13dB 24
25 Table 6 VCCINT_AMS Results Measurement Result Pass/Fail Test Condition Notes Vout 0.848V Pass 0A DMM 7A DC Ripple 8.0mV Pass 0A Coax 8.0mV 7A Isense 0A Pass 0.0A Telemetry/E-load 3.33A 6.75A 3.5A 7.0A Vac(droop) 18.0mV Pass 5.25A to 7.0A Vac(overshoot) 21.2mV Pass 7.0A to 5.25A 25
26 Figure 8 - VCCINT_AMS DC Ripple, 7A Figure 9 - VCCINT_AMS ac ripple load 26
27 Figure 10 - VCCINT_AMS ac ripple release 27
28 Figure 11 VCCINT_AMS Jitter, 7A 28
29 UTIL_3V3 Vin, 12V Vout, 3.3V Iout(pk), 15A (new from ) Istep, 5A Iramp, 1A/us Vout Measurement Location, J69, U40, C183, J20 Load Test Location, J69 SW Node Measurement Location, L26 Jitter = 68ns (10A load) Bode Analysis 29
30 With 0A Load the crossover frequency is around 69kHz with 52 deg of Phase Margin and Gain Margin of -10dB With 10A Load, the crossover frequency is around 70kHz with 50 deg of Phase Margin and Gain Margin of -11dB Config: IRPS5401MXI04TRP_MTPplus6_3.3V_2.5V_1.2V 0.85V_800k_Rev2_2.txt Table 7 UTIL_3V3 Results 30
31 Measurement Result Pass/Fail Test Condition Notes Vout 3.313V Pass 0A DMM 10A DC Ripple 10.4mV 12.4mV 12.4mV Pass 0A 10A 15A Active probe Isense 0.63A 5.25A 9.88A 14.88A Vac(droop) Vac(overshoot) 29.6mV 31.2mV 25.2mV 30.0mV Pass Pass Pass 0A 5A 10A 15A 5A to 10A 10A to 15A 10A to 5A 15A to 10A Telemetry/E-load 31
32 Figure 12 - UTIL_3V3 DC Ripple, 10A 32
33 Figure 13 - UTIL_3V3 ac ripple load 33
34 Figure 14 - UTIL_3V3 ac ripple unload 34
35 Figure 15 - UTIL_3V3 Jitter, 10A 35
36 UTIL_2V5 Vin, 12V Vout, 2.5V Iout(pk), 2A Istep, 1A Iramp, 1A/us Vout Measurement Location, J66, L74 Load Test Location, J66 SW Node Measurement Location, L23 Jitter = 65ns (1A load) Bode Analysis With 0A load, the crossover frequency is around 35.3kHz and 52 deg of Phase Margin and Gain Margin of -20dB 36
37 With 2A load, the crossover frequency was around 48.62kHz with 51 deg of Phase Margin and Gain Margin of -17dB. Config: IRPS5401MXI04TRP_MTPplus6_3.3V_2.5V_1.2V 0.85V_800k_Rev2_2.txt Table 8 UTIL_2V5 Results Measurement Result Pass/Fail Test Condition Notes Vout 2.500V Pass 0A DMM 2A DC Ripple 26.8mV Pass 0A Active probe 26.8mV 2A Isense 0.03A Pass 0A Telemetry/E-load 2.00A 2A Vac(droop) 22.8mV Pass 1A to 2A At Ethernet At LDO input Vac(overshoot) 26.8mV Pass 2A to 1A At Ethernet At LDO input 37
38 Figure 16 - UTIL_2V5 DC Ripple, 0A 38
39 Figure - UTIL_2V5 DC Ripple, 2A 39
40 Figure 17 - UTIL_2V5 Transient Load: 1-2A load step 40
41 Figure 18 - UTIL_2V5 Vout excursion during a transient load is around 22.8mV 41
42 Figure UTIL_2V5 Transient load release: Vout overshoot is around 26.8mV 42
43 MGT1V2 Vin, 12V Vout, 1.2V Iout(pk), 6A Istep, 2.5A Iramp, 1A/us Vout Measurement Location, J67, C942, C124, C943 Load Test Location, J67 SW Node Measurement Location, L81 Jitter = 43ns (6A) Bode Analysis With 0A load, the crossover frequency is 28.8kHz with 66deg phase margin and -43dB of Gain Margin 43
44 With 6A load, the crossover frequency is around 32.2kHz with 47 deg of phase margin and Gain Margin is around -30dB Config: IRPS5401MXI04TRP_MTPplus6_3.3V_2.5V_1.2V 0.85V_800k_Rev2_2.txt Table 9 MGT1V2 Results Measurement Result Pass/Fail Test Condition Notes Vout 1.207V Pass 0A DMM 6A DC Ripple 14.3mV Pass 0A Diff Probe 14.2mV 6A Isense 0.00A Pass 0A Telemetry/Eload 5.89A 6A Vac(droop) 57mV Pass 3.5A to 6.0A Vac(overshoot) 57mV Pass 6.0A to 3.5A 44
45 Figure 19 - MGT1V2 DC Ripple with 0A load 45
46 Figure: DC ripple with 6A load 46
47 Figure 20 - MGT1V2 ac ripple load with 3.5A 6A Figure: Vout excursion during a 3.5-6A load step is around 57mV 47
48 Figure: Vout overshoot during a 6A-3.5A load release is around 57mV 48
49 Figure 21 - MGT1V2 ac ripple release 49
50 Figure 22 - MGT1V2 Jitter, 6A 50
51 MGTRAVCC Vin, 2.5V Vout, 0.85V Iout(pk), 0.5A Istep, 0.25A Iramp, 1A/us Vout Measurement Location, J68, C129 Load Test Location, J68 Config: IRPS5401MXI04TRP_MTPplus6_3.3V_2.5V_1.2V 0.85V_800k_Rev2_2.txt Table 10 MGTRAVCC Results Measurement Result Pass/Fail Test Condition Notes Vout 0.842V Pass 0.0A DMM 0.844V 0.5A DC Ripple 5.8mV Pass 0.0A Coax 5.8mV 0.5A Isense 0.0A Pass 0A Telemetry/E-load 0.5A 0.5A Vac(droop) 3.6mV Pass 0.25A to 0.5A Vac(overshoot) 3.8mV Pass 0.5A to 0.25A 51
52 Figure 23 - MGTRAVCC DC Ripple, 0.5A 52
53 Figure 24 - MGTRAVCC ac ripple load 53
54 Figure 25 - MGTRAVCC ac ripple release 54
55 VCC1V2 Vin, 12V Vout, 1.2V Iout(pk), 6.0A Istep, 3.0A Iramp, 1A/uS Vout Measurement Location, J74, C101, C107, C108 Load Test Location, J74 SW Node Measurement Location, L30 Jitter = 26ns (6A load) Bode Analysis 55
56 With 0A load, the crossover frequency is around 63.26kHz and phase margin of 53.5 deg with Gain Margin of -12dB With 6A Load, the crossover frequency is around 69 khz and Phase Margin is 46.5 deg with Gain Margin of -12.5dB Config: IRPS5401MXI04TRP_MTPplus7_1.2V_2.5V_1.8V_1.8V_800k_Rev2_2.txt Table 11 VCC1V2 Results 56
57 Measurement Result Pass/Fail Test Condition Notes Vout 1.197V Pass 0A DMM 6A DC Ripple 10.4mV Pass 0A Active probe 10.4mV 6A Isense 0.0A Pass 0.0A Telemetry/E-load 3.0A 5.9A 3.0A 6.0A Vac(droop) 16.4mV Pass 3.0A to 6.0A Vac(overshoot) 19.0mV Pass 6.0A to 3.0A 57
58 Figure 26 - VCC1V2 DC Ripple, 5A 58
59 Figure 27 - VCC1V2 ac ripple load 59
60 Figure 28 - VCC1V2 ac ripple release 60
61 Figure 29 - VCC1V2 Jitter, 5A 61
62 DAC_AVTT Vin, 12V Vout, 3.0V/2.5V Iout(pk), 0.5A Istep, 0.5A Iramp, 1A/uS Vout Measurement Location, J71, C145, C146, C143, C144 Load Test Location, J71 SW Node Measurement Location, L27 Jitter = 31.2ns (6A load) Bode Analysis With 0A load, the crossover frequency is around 29.36kHz with deg Phase Margin and Gain Margin of -18.3dB 62
63 With 500mA of load current, the crossover frequency is around 29.38kHz with 48.5deg Phase Margin and Gain Margin of -17dB Config: IRPS5401MXI04TRP_MTPplus7_1.2V_2.5V_1.8V_1.8V_800k_Rev2_2.txt Table 12 DAC_AVTT Results Measurement Result Pass/Fail Test Condition Notes Vout 2.508V Pass 0A DMM 0.5A DC Ripple 4.8mV Pass 0A Coax 7.4mV 0.5A Isense 0A Pass 0.0A Telemetry/E-load 0.52A 0.5A Vac(droop) 17.2mV Pass 0A to 0.5A Vac(overshoot) 24.0mV Pass 0.5A to 0A 63
64 Figure 30 - DAC_AVTT DC Ripple, 0.5A 64
65 Figure 31 - DAC_AVTT ac ripple load 65
66 Figure 32 - DAC_AVTT ac ripple release 66
67 Figure 33 - DAC_AVTT Jitter, 0.5A 67
68 FMC_VADJ Vin, 12V Vout, 1.8V Iout(pk), 5A Istep, 2A Iramp, 1A/us Vout Measurement Location, J72, C96, C97, C98, C287 (BUS side) Load Test Location, J72 SW Node Measurement Location, L28, L29 Jitter = 32.8ns (5A load) Bode Analysis 68
69 With 0A load, the crossover frequency is 26.6kHz and phase margin is 63.9 deg with Gain Margin around -34dB With 5A load, the crossover frequency is 30.33kHz and phase margin is around 47deg and Gain Margin is around 31.3dB. Config: IRPS5401MXI04TRP_MTPplus7_1.2V_2.5V_1.8V_1.8V_800k_Rev2_2.txt Table 13 FMC_VADJ Results Measurement Result Pass/Fail Test Condition Notes Vout 1.81V Pass 0A DMM 69
70 5A DC Ripple 56mV 80mV Pass 0A 5A Isense 0A Pass 0A 4.98A 5A Vac(droop) 108mV Pass 3A to 5A Vac(overshoot) 68mV Pass 5A to 3A Active probe Telemetry/E-load 70
71 Figure 34 - FMC_VADJ DC Ripple, 0A: The ripple voltage is around 56mV 71
72 Figure FMC_VADJ: Vout ripple with 5A load is around 80mV 72
73 Figure 35 - FMC_VADJ Transient load response during 3-5A load step is around 192mV 73
74 Figure 36 - FMC_VADJ transient load step: Vout excursion is around 108mV 74
75 Figure 37 - FMC_VADJ Transient load release Vout overshoot is around 68mV 75
76 MGT1V8 Vin, 2.5V Vout, 1.8V Iout(pk), 0.5A Istep, 0.5A Iramp, 1A/us Vout Measurement Location, J41, C944 Load Test Location, J41 Config: IRPS5401MXI04TRP_MTPplus7_1.2V_2.5V_1.8V_1.8V_800k_Rev2_2.txt Table 14 MGT1V8 Results Measurement Result Pass/Fail Test Condition Notes Vout 1.797V Pass 0A DMM 1.794V 0.5A DC Ripple 4.8mV Pass 0A Coax 4.8mV 0.5A Isense 0.0A Pass 0A Telemetry/Eload 0.5A 0.5A Vac(droop) 18.8mV Pass 0A to 0.5A Vac(overshoot) 12.8mV Pass 0.5A to 0A 76
77 Figure 38 - MGT1V8 DC Ripple, 0.5A 77
78 Figure 39 - MGT1V8 ac ripple load 78
79 Figure 40 - MGT1V8 ac ripple release 79
80 VCCINT Vin, 12V Vout, 0.85V Iout(pk), 30A Istep, 7.5A (12.5A to 20A) Iramp, 2A/us Vout Measurement Location, J76, C51, C52, (or BGA pad where FPGA not populated) Load Test Location, J76 SW Node Measurement Location, L31 Test Needs VOUT_OV_WARN is persistent. This is being investigated. Table 15 VCCINT Results Measurement Result Pass/Fail Test Condition Notes Vout V V V Pass 0A 15A 30A DMM At load DC Ripple 14.4mV 12.82mV 13.6mV 12.4mV Isense 0.0A 4.00A 9.00A A Pass Pass 0A 10A 15A 30A 0A 5A 10A 15A 20A 30A Active Probe Telemetry/E-load Vac(droop) 20.8mV Pass 12.5A to 20A Active Probe/ E- Load Vac(overshoot) 18.8mV Pass 20A to 12.5A Active Probe/ E- Load 80
81 Figure VCCINT Ripple, 0A Jitter is around 16ns Figure VCCINT Ripple, 10A Jitter is around 12ns 81
82 Figure 41 - VCCINT Ripple, 15A Jitter is around 16ns Figure 44 VCCINT Ripple, 30A Jitter is around 16ns 82
83 Figure 42 - VCCINT excursion during a 12.5A to 20A load step, 20.8mV Figure 43 - VCCINT deviation during a 20A to 12.5A load release. 83
84 Figure With 0A load, crossover frequency is 31.13kHz with 70 deg of Phase Margin and Gain Margin of -18dB Figure With 30A Load, crossover frequency is 31.13kHz with 60.4 deg of Phase Margin and Gain Margin of -19dB 84
85 MGTAVCC Vin, 2.5V Vout, 0.9V Iout(pk), 3.0A Istep, 1.5A Iramp, 1A/us Vout Measurement Location, J77, C131 Load Test Location, J77 Jitter = 26.8ns (3A load) * note - large pigtail loop present due to load equip location Design Recommendations: Add BODE resistor Test Needs BODE Table 16 MGTAVCC Results Measurement Result Pass/Fail Test Condition Notes Vout 0.903V Pass 0A DMM 3.0A DC Ripple 10mV Pass 0A Active Probe 10mV 3.0A Isense 0.0A Pass 0A Telemetry/E-load 3.2A 3.1A Vac(droop) 12.8mV Pass 1.5A to 3.0A Vac(overshoot) 11.2mV Pass 3.0A to 1.5A 85
86 Figure 44 - MGTAVCC DC Ripple, 0.5A 86
87 Figure 45 - MGTAVCC ac ripple load 87
88 Figure 46 - MGTAVCC ac ripple release 88
89 Figure 47 - MGTAVCC Jitter, 3A 89
90 DAC_AVCCAUX Vin, 2.5V Vout, 1.8V Iout(pk), 0.5A Istep, 0.125A Iramp, 1A/us Vout Measurement Location, J77, C326 Load Test Location, J77 Design Recommendations: Test Needs DC Ripple special test equip required Table 17 DAC_AVCC_AUX Results Measurement Result Pass/Fail Test Condition Notes Vout 1.802V Pass 0A DMM 1.800V 0.5A DC Ripple 0A 0.5A Vac(droop) 7.2mV Pass 0.375A to 0.5A Vac(overshoot) 8.0mV Pass 0.5A to 0.375A Require STE for target spec Reached coax noise floor 90
91 Figure 48 - DAC_AVCC_AUX DC Ripple, 0.5A 91
92 Figure 49 DAC_AVCC_AUX ac ripple load 92
93 Figure 50 DAC_AVCC_AUX ac ripple unload 93
94 ADC_AVCCAUX Vin, 12V Vout, 1.8V Iout(pk), 2.0A Istep, 2.0A Iramp, 1A/us Vout Measurement Location, J79, C135 Load Test Location, J79 Jitter = 50ns (no load) * note - large pigtail loop present due to load equip location Design Recommendations: Add BODE resistor Test Needs BODE Table 18 ADC_AVCC_AUX Results Measurement Result Pass/Fail Test Condition Notes Vout 1.804V Pass 0A DMM 0.5A DC Ripple 8.4mV Pass 0A Coax 8.0mV 0.5A Isense 0.0A Pass 0A Telemetry/E-load 2.19A 2A Vac(droop) 11.2mV Pass 0.0A to 2.0A Vac(overshoot) 12.0mV Pass 2.0A to 0.0A 94
95 Figure 51 - ADC_AVCCAUX DC Ripple, 0.5A 95
96 Figure 52 ADC_AVCCAUX ac ripple load 96
97 Figure 53 ADC_AVCCAUX ac ripple unload 97
98 Figure 54 ADC_AVCAUX Jitter, 2A 98
99 UTIL_1V13 Vin, 12V Vout, 1.13V Iout(pk), 4A Istep, 4A Iramp, 0.5A/us Vout Measurement Location, J80, load cap Load Test Location, J80 SW Node Measurement Location, L34 Jitter = 23.6ns (4A load) Design Recommendations: Add BODE resistor Test Needs BODE Waveforms at load bypass caps for lower ripple Table 19 UTIL_1V13 Results Measurement Result Pass/Fail Test Condition Notes Vout 1.136V Pass 0A DMM 4A DC Ripple 14.4mV 34.0mV Pass 0A 4A Active probe at VR. Confirmed tighter specs at load. Isense 0.0A Pass 0A Telemetry/E-load 4.25A 4A Vac(droop) 33.2mV Pass 0A to 4A Vac(overshoot) 18.4mV Pass 4A to 0A 99
100 Figure 55 - UTIL_1V13 DC Ripple, 1A 100
101 Figure 56 - UTIL_1V13 ac ripple load 101
102 Figure 57 - UTIL_1V13 ac ripple release 102
103 Figure 58 - UTIL_1V13 Jitter, 1A 103
104 UTIL_5V0 Vin = 12V Vout = 5.0V Iout(pk) = 2.7A Istep, 1A Iramp, 1A/us Vout Measurement Location, J81, Cout Load Test Location, J81 SW Node Measurement Location, L35 Design Recommendations: Test Needs Table 20 UTIL_5V0 Results Measurement Result Pass/Fail Test Condition Notes Vout 5.V Pass 0A DMM DC Ripple 41.6mV Pass 0A Active probe 19.6mV 2.7A Vac(droop) 23.6mV Pass 1.7A to 2.7A Vac(overshoot) 35.6mV Pass 2.7A to 1.7A 104
105 Figure 59 - UTIL_5V0 DC Ripple, 2.1A 105
106 Figure 60 - UTIL_5V0 ac ripple load 106
107 Figure 61 - UTIL_5V0 ac ripple unload 107
108 Figure 62 - UTIL_5V0 Jitter, 2.1A 108
109 ADC_AVCC Vin, 1.13V Vout, 0.925V Iout(pk), 2.0A Istep, 0.5A Iramp, 1A/us Vout Measurement Location, J82, Load Test Location, J82 Design Recommendations: Test Needs DC Ripple special test equip required Table 21 ADC_AVCC Results Measurement Result Pass/Fail Test Condition Notes Vout 0.927V Pass 0A DMM 2.0A DC Ripple 0A 2A Vac(droop) Vac(overshoot) None measurable to 2A step (<2.0mV) None measurable to 2A step (<2.0mV) Pass Pass 1.5A to 2A 1.5A to 2A Require STE for target spec Reached coax noise floor 109
110 DAC_AVCC Vin, 1.13V Vout, 0.925V Iout(pk), 1.0A Istep, 0.25A Iramp, 1A/us Vout Measurement Location, J82, C131 Load Test Location, J82 Design Recommendations: Test Needs DC Ripple special test equip required Table 22 DAC_AVCC Results Measurement Result Pass/Fail Test Condition Notes Vout 0.93V Pass 0A DMM 1.0A DC Ripple 0A 1A Vac(droop) No discernable droop Pass 0.75A to 1A Require STE for target spec Reached coax noise floor Vac(overshoot) 2mV No discernable overshoot 2.4mV 0.5A to 1A Pass 1.0A to 0.75A 1A to 0.5A 110
111 Figure 63 DAC_AVCC ac ripple 111
112 PL_DDR4_VTT Vin, 12V Vout, 0.6V Iout(pk), 3A Istep, 1.5A Iramp, 0.5A/us Vout Measurement Location, J84 Load Test Location, J84 SW Node Measurement Location, L36 Jitter = 7.4ns (3A load) Design Recommendations: Add BODE resistor Test Needs BODE Waveforms from load bypass cap Table 23 PL_DDR4_VTT Results Measurement Result Pass/Fail Test Condition Notes Vout 0.6V Pass 0A DMM 0.6V 3A DC Ripple 30.0mV Pass 0A Active Probe 26.8mV 3A Vac(droop) 14.0mV Pass 1.5A to 3.0A Vac(overshoot) 10.4mV Pass 3.0A to 1.5A 112
113 Figure 64 - PL_DDR4_VTT DC Ripple, 3A 113
114 Figure 65 - PL_DDR4_VTT ac ripple load 114
115 Figure 66 - PL_DDR4_VTT ac ripple release 115
116 Figure 67 - PL_DDR4_VTT Jitter, 3A 116
117 PS_DDR4_VTT Vin, 12V Vout, 0.6V Iout(pk), 3A Istep, 1.5A Iramp, 0.5A/us Vout Measurement Location, J85 Load Test Location, J85 SW Node Measurement Location, L37 Design Recommendations: Add BODE resistor Test Needs BODE Jitter Table 24 PS_DDR4_VTT Results Measurement Result Pass/Fail Test Condition Notes Vout 0.6V Pass 0A DMM 0.599V 3A DC Ripple 12.0mV Pass 0A Active Probe 12.4mV 3A Vac(droop) 8.8mV Pass 1.5A to 3.0A Vac(overshoot) 9.2mV Pass 3.0A to 1.5A 117
118 Figure 68 - PS_DDR4_VTT DC Ripple, 3A 118
119 Figure 69 - PS_DDR4_VTT ac ripple load 119
120 Figure 70 - PS_DDR4_VTT ac ripple release Figure 71 - PS_DDR4_VTT Jitter, 3A 120
121 UTIL_3V5 Vin, 12V Vout, 3.5V Iout(pk), 3A Istep, 1.5A Iramp, 1A/us Vout Measurement Location, J93, C832 Load Test Location, J93 SW Node Measurement Location, L71 Design Recommendations: Evaluate DC drop from VR to load Test Needs Table 25 UTIL_3V5 Results Measurement Result Pass/Fail Test Condition Notes Vout 3.518V Pass 0A DMM 3A DC Ripple 14.0mV Pass 0A Active probe 11.6mV 3A Vac(droop) 26.4mV Pass 1.5A to 3.0A Vac(overshoot) 29.6mV Pass 3.0A to 1.5A 121
122 Figure 72 - UTIL_3V5 DC Ripple, 3A 122
123 Figure 73 - UTIL_3V5 ac ripple load 123
124 Figure 74 - UTIL_3V5 ac ripple unload 124
125 AMS_CLK_VCC3V3 Vin, 12V Vout, 3.3V Iout(pk), 3A Istep, 1.5A Iramp, 1A/us Vout Measurement Location, J63, C827, L73, C953, L58 Load Test Location, J63 Design Recommendations: Test Needs Evaluate Cu and impedance from VR to load to alleviate DC drop Table 26 AMS_CLK_VCC3V3 Results Measurement Result Pass/Fail Test Condition Notes Vout 3.33V Pass 0A DMM 3A DC Ripple 10.0mV Pass 0A Active probe 11.2mV 3A Vac(droop) ***46.4mV Pass 1.5A to 3.0A See slew rate There is no undershoot Vac(overshoot) ***46.0mV Pass 3.0A to 1.5A See slew rate There is minimal VOS, 20mV 125
126 Figure 75 - AMS_CLK_VCC3V3 DC Ripple, 3A 126
127 Figure 76 - AMS_CLK_VCC3V3 ac ripple load 127
128 Figure 77 - AMS_CLK_VCC3V3 ac ripple unload 128
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