NJU7381A LOW VOLTAGE OPERATION DUAL H BRIDGE DRIVER FEATURES BLOCK DIAGRAM

Transcription

1 LOW VOLTAGE OPEATI DUAL H BIDGE DIVE GENEAL DESCIPTI The is a dual H-bridge driver IC that features low voltage operation and low quiescent current. The control method is 2 logic Inputs (2-IN) that includes standby mode. The independent comparator circuit can be used for position sensing signal processing and the others. Small package makes the suitable for small stepper motor and DC motor, such as portable applications. PACKAGE OUTLINE MJE (EQFN16-JE) V (SSOP16) FEATUES Supply Voltage : V DD =1.8V to 5.5V Output Current : I O =200mA (Continuous) I O =400mA (Peak) Output esistance : O(H+L) =5Ω typ. at V DD =3.3V O(H+L) =1.95Ω typ. at V DD =1.8V Low Quiescent Current : 60µA typ. at V DD =3.3V 2 Logic Inputs Control (2-IN) Stand-by Function (At no-input signal) Built-in Comparator Circuit Protection Circuit : Thermal Shutdown Circuit (TSD) Package Outline : EQFN16-JE, SSOP16 BLOCK DIAGAM INA1 OUTA1 Stepper Motor INA2 Control Logic OUTA2 M INB1 INB2 TSD OUTB1 GND OUTB2 COMP + COMP - COMP OUT - 1 -

2 PIN CFIGUATI EQFN16-JE SSOP Top View Top View SUB Bottom View PIN DESCIPTI PIN No. EQFN16 SSOP16 PIN NAME FUNCTI NOTES 1 2 INB1 Bch Logic Input Pin INB2 Bch Logic Input Pin 2-3,11 4,12 Power Supply Pin Both pins must be connected together externally. 4 5 INA2 Ach Logic Input Pin INA1 Ach Logic Input Pin OUTA2 Ach Output Pin 2-7,15 8,16 GND Ground Pin Both pins must be connected together externally. 8 9 OUTA1 Ach Output Pin COMP OUT Comparator Output Pin When not using, it should be set to open NC No Connection Not Internally Connected COMP+ Comparator Non-inverted Input Pin When not using, it should be connected to COMP- Comparator Inverted Input Pin When not using, it should be connected to GND OUTB1 Bch Output Pin OUTB2 Bch Output Pin 2 - SUB - SUB Back Side Thermal PAD The PAD is connected with the internal. (SUB) It must be set to open or connected to

3 ABSOLUTE MAXIMUM ATINGS (Ta=25ºC) PAAMETE SYMBOL ATINGS UNIT NOTES Supply Voltage V DD 7 V - Logic Input Voltage V ID -0.3 to V DD +0.3 V - Motor Output Current (Peak) I OPEAK 400 ma Per channel 800 ma Ach & Bch parallel connection Comparator Output Current I CO 10 ma - Comparator Output Voltage V CO 7 V - Operating Ambient Temperature Topr -40 to + 85 ºC - Junction Temperature Tj -40 to +150 ºC - Storage Temperature Tstg -50 to +150 ºC - Power Dissipation Layers on PCB (*1) P (EQFN16-JE) D mw Layers on PCB (*2) Power Dissipation (SSOP16) P D 300 Device itself 610 mw 2 Layers on PCB (*3) Layers on PCB (*4) *1: Mounted on glass epoxy board based on EIA/JEDEC. ( mm, F-4, 2Layers, connected exposed PAD) *2: Mounted on glass epoxy board on EIA/JEDEC. ( mm, F-4, 4Layers, Inner Cu area : mm, In addition thermal via holes, connected exposed PAD) *3: Mounted on glass epoxy board based on EIA/JEDEC. ( mm, F-4, 2Layers) *4: Mounted on glass epoxy board based on EIA/JEDEC. ( mm, F-4, 4Layers, Inner Cu area : mm) ECOMMENDED OPEATING CDITIS (V DD =3.3V, Ta=25ºC) PAAMETE SYMBOL TEST CDITIS MIN. TYP. MAX. UNIT Supply Voltage 1 V DD1 Not using comparator block (*5) V Supply Voltage 2 V DD1 Using comparator block (*5) V Motor Output Current (Continuous) I O Per channel ma Ach & Bch parallel connection ma *5: Output voltage may not be provided enough depending on output current level, please review output resistance spec

4 ELECTICAL CHAACTEISTICS (V DD =3.3V, Ta=25ºC) PAAMETE SYMBOL TEST CDITIS MIN. TYP. MAX. UNIT GENEAL Quiescent Current 1 I DD µa Quiescent Current 2 I DD2 V DD =1.8V µa Quiescent Current at Stand-by I STB µa Thermal Shutdown Temperature T TSD ºC Thermal Shutdown Hysteresis T HYS ºC LOGIC BLOCK H Level Input Voltage 1 V IH V DD V H Level Input Voltage 2 V IH2 V DD =1.8V V DD V L Level Input Voltage 1 V IL1 0 - V L Level Input Voltage 2 V IL2 V DD =1.8V 0 - V Input Hysteresis Width V IHYS - - V H Level Input Current I IH Per 1 Input µa L Level Input Current I IL Per 1 Input na Input Pull Down esistance IN kω Input Pulse Width tp µs DIVE BLOCK High Side Output esistance 1 H1 I O =200mA Ω High Side Output esistance 2 H2 V DD =2.1V, I O =200mA Ω High Side Output esistance 3 H3 V DD =1.8V, I O =200mA Ω Low Side Output esistance 1 L1 I O =200mA Ω Low Side Output esistance 2 L2 V DD =2.1V, I O =200mA Ω Low Side Output esistance 3 L3 V DD =1.8V, I O =200mA Ω Parallel Connection High Side Output esistance 1 PH1 I O =400mA Ω Parallel Connection High Side Output esistance 2 PH2 V DD =2.1V, I O =400mA Ω Parallel Connection High Side Output esistance 3 PH3 V DD =1.8V, I O =400mA - Ω Parallel Connection Low Side Output esistance 1 PL1 I O =400mA Ω Parallel Connection Low Side Output esistance 2 PL2 V DD =2.1V, I O =400mA Ω Parallel Connection Low Side Output esistance 3 PL3 V DD =1.8V, I O =400mA Ω H Temperature Coefficient Δ H/ΔTj Tj=40~125ºC, I O =200mA mω/ºc L Temperature Coefficient Δ L/ΔTj Tj=40~125ºC, I O =200mA mω/ºc High Side everse Voltage V OH I O =-200mA - 5 V Low Side everse Voltage V OL I O =-200mA V High Side Leak Current I OLEAKH V DD =7.0V µa Low Side Leak Current I OLEAKL V DD =7.0V µa Output Turn Time t ns Output Turn OFF Time t OFF ns Dead Time td ns COMPAATO BLOCK Input Offset Voltage V IO mv Input Bias Current I IB pa Common Mode Input Voltage ange V ICM 0 - V DD -0.5 V Output Voltage Vsat L=10kΩ V Output Leak Current I COLEAK V CO =5.5V µa - 4 -

5 THEMAL ESISTANCE EQFN16-JE PAAMETE SYMBOL TEST CDITIS MIN. TYP. MAX. UNIT Junction - Ambient Mounted on glass epoxy board based on ja_1 Thermal esistance 1 EIA/JEDEC ºC/W Junction Case Surface ( mm, F-4, 2Layers, jt_1 Thermal esistance 1 connected exposed PAD) ºC/W Junction - Ambient Mounted on glass epoxy board based on ja_2 Thermal esistance 2 EIA/JEDEC ºC/W Junction Case Surface Thermal esistance 2 SSOP16 ( mm, F-4, 4Layers, jt_2 Inner Cu area : mm, In addition ºC/W thermal via holes, connected exposed PAD) PAAMETE SYMBOL TEST CDITIS MIN. TYP. MAX. UNIT Junction - Ambient ja_1 Mounted on glass epoxy board based on ºC/W Thermal esistance 1 EIA/JEDEC. Junction Case Surface jt_1 ( mm, F-4, 2Layers) ºC/W Thermal esistance 1 Junction - Ambient Mounted on glass epoxy board based on ja_2 Thermal esistance 2 EIA/JEDEC ºC/W Junction Case Surface ( mm, F-4, 4Layers, jt_2 Thermal esistance 2 Inner Cu area : mm) ºC/W POWE DISSIPATI vs. AMBIENT TEMPEATUE MJE P D vs. Ta (Topr=-40 to +85ºC, Tj=150ºC) 2500 Power Dissipation P D (mw) Mounted on 4-Layer Board (F mm, Inner Cu area: mm, In addition thermal via holes, connected exposed PAD) Mounted on 2-Layer Board (F mm, connected exposed PAD) 936mW 374mW Ambient Temperature Ta(ºC) V P D vs. Ta (Topr=-40 to 85ºC, Tj=150ºC) Power Dissipation P D (mw) Mounted on 4-Layer Board (F mm, Inner Cu area: mm) Mounted on 2-Layer Board (F mm) Device itself 405mW 317mW 156mW Ambient Temperature Ta(ºC) - 5 -

6 INPUT - OUTPUT TUTH TABLE INPUT OUTPUT Comparator NOTES INA1 INA2 INB1 INB2 OUTA1 OUTA2 OUTB1 OUTB2 Circuit STOP ALL L OFF OFF OFF OFF Standby (Output OFF) L L OFF OFF OFF(Fast Decay) H L H L CW - - Ach L H L H CCW H H H H Brake(Slow Decay) Normal L L OFF OFF OFF(Fast Decay) Operation H L H L CW - - Bch L H L H CCW H H H H Brake(Slow Decay) Don't Care OFF OFF OFF OFF TSD *OFF=Hi-Z COMPAATO TUTH TABLE (Normal Operation) INPUT OUTPUT COMP+ COMP- COMPOUT NOTES H L OFF FET: OFF Operation L H L FET: Operation *OFF=Hi-Z BASIC OPEATI TIMING CHAT INA1(B1) INA2(B2) OUTA1(B1) OFF(Hi-Z) OUTA2(B2) OFF(Hi-Z) Output OFF STATE CCW CW Brake BASIC OUTPUT OPEATI PATTEN Stop CCW (Charge) CW (Charge) Output OFF (Fast Decay) Brake (Slow Decay) OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1 OUT2-6 -

7 TYPICAL APPLICATIS STANDAD Connect suitable capacitors to reduce transient noise generated by the switching. + 10µF 0.1µF + DC Motor 2 POTx POTx INA1 INA2 OUTA1 OUTA2 Ach DC MOTO M POTx POTx INB1 INB2 OUTB1 OUTB2 Bch DC MOTO M COMP+ COMP- Stepper Motor 1 POTx COMP OUT GND STEPPE MOTO When not using comparator part, these should be set as follows. COMP+ : COMP- : GND COMP OUT : OPEN M PAALLEL CNECTI (Boost Output Current) Connect suitable capacitors to reduce transient noise generated by the switching. + 10µF 0.1µF + DC Motor 1 POTx INA1 OUTA1 POTx INA2 INB1 INB2 The wiring distance should be connected equally or in the IC neighborhood to prevent the delay time from occurring between each signal input. OUTA2 OUTB1 OUTB2 DC MOTO M POTx COMP+ COMP- COMP OUT When not using comparator part, these should be set as follows. COMP+ : COMP- : GND COMP OUT : OPEN GND The wiring distance should be connected equally to prevent the delay time or wiring resistance difference from occurring between each motor output

8 STEPPE MOTO DIVE APPLICATI TIMIG CHAT INA1 INA2 INB1 INB2 Io(Ach) Io(Bch) STEP No FULL STEP ( 2 Phase Excitation ) HALF STEP ( 1-2 Phase Excitation ) OTE POSITI (STEP No.) - 8 -

9 TYPICAL CHAACTEISTICS 120 V DD vs. I DD Ta=25ºC I DD [µa] V DD [V] 1.6 V DD vs. H Io=200mA, Ta=25ºC 1.6 V DD vs. L Io=200mA, Ta=25ºC H [Ω] L [Ω] V DD [V] V DD [V] Io vs. V OH V DD =3.3V, Ta=25ºC Io vs. V OL V DD =3.3V, Ta=25ºC V OH [V] V OL [V] Io [ma] Io [ma] - 9 -

10 TYPICAL CHAACTEISTICS 80 Tj vs. I DD V DD =3.3V 14 Tj vs. I STB V DD =3.3V I DD [µa] I STB [µa] Tj [ºC] Tj [ºC] Tj vs. H V DD =3.3V, Io=200mA Tj vs. L V DD =3.3V, Io=200mA H [Ω] L [Ω] Tj [ºC] Tj [ºC]

11 [CAUTI] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights