This is a repository copy of PWM Harmonic Signature Based Islanding Detection for a Single-Phase Inverter with PWM Frequency Hopping.

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1 Tis is a repository copy of PWM Harmonic Signature Based Islanding Detection for a Single-Pase Inverter wit PWM Frequency Hopping. Wite Rose Researc Online URL for tis paper: ttp://eprints.witerose.ac.uk/110053/ Version: Accepted Version Article: Colombage, K., Wang, J. orcid.org/ , Gould, C. et al. (1 more autor) (2017) PWM Harmonic Signature Based Islanding Detection for a Single-Pase Inverter wit PWM Frequency Hopping. IEEE Transactions on Industry Applications, 53 (1). pp ISSN ttps://doi.org/ /tia Reuse Unless indicated oterwise, fulltext items are protected by copyrigt wit all rigts reserved. Te copyrigt exception in section 29 of te Copyrigt, Designs and Patents Act 1988 allows te making of a single copy solely for te purpose of non-commercial researc or private study witin te limits of fair dealing. Te publiser or oter rigts-older may allow furter reproduction and re-use of tis version - refer to te Wite Rose Researc Online record for tis item. Were records identify te publiser as te copyrigt older, users can verify any specific terms of use on te publiser s website. Takedown If you consider content in Wite Rose Researc Online to be in breac of UK law, please notify us by ing eprints@witerose.ac.uk including te URL of te record and te reason for te witdrawal request. eprints@witerose.ac.uk ttps://eprints.witerose.ac.uk/

2 PWM Harmonic Signature Based Islanding Detection for a Single-Pase Inverter wit PWM Frequency Hopping Kalana Colombage (Student Member, IEEE), Jiabin Wang (Senior Member, IEEE), Cris Gould (Member, IEEE), Caoui Liu (Student Member, IEEE) Department of Electronic and Electrical Engineering Te University of Seffield Seffield, S1 3JD, UK kalana.colombage@icloud.com Abstract -- Distributed generation (DG) as gained popularity in recent years due to te increasing requirement for renewable power sources. A problem tat exists wit DG systems is te islanding of DG units tat creates safety issues for personnel as well as te potential for damage to utility infrastructure. Terefore, islanding detection metods are utilized to mitigate te risk of islanded operation of DG units. A new passive metod of islanding detection based on te signature of te PWM voltage armonics is proposed. Te viability of te algoritm is investigated wit te use of an analytical and time domain model of te inverter and furter validated wit experimental results. Furtermore, an extension of te detection sceme is proposed for use in multiinverter scenarios composed of adaptive frequency opping to eliminate unwanted tripping. Keywords passive islanding detection, PWM armonic signature, frequency opping I.! INTRODUCTION Islanding is defined as te condition were te distributed generator (DG) continues to operate wit local loads after te utility grid as been disconnected [1]. Unintentional islanding is undesired since it is a azard to utility workers and causes possible damage to equipment as a result of asyncronous re-closure. Asyncronous reclosure occurs wen te utility recloses wit an energized DG wic is out of pase wit te utility and can terefore cause large currents to flow, ence possibly damaging te DG converter infrastructure [2]. Islanding also as te potential to interfere wit te power restoration service of te utility [3]. According to te IEEE1547 standard for interconnecting distributed resources wit electric power systems, it is a requirement for grid connected DG systems to be able to detect islanding witin 2 seconds and cease to energize te area electrical power system (EPS) tat is coupled troug te point of common coupling (PCC) [4]. As a consequence, a diverse range of islanding detection metods ave been developed and reported in literature eac wit teir merits and limitations. Te two main categories of islanding detection are passive and active metods. Passive metods consist of te detection of islanding troug non-invasive means wereas active metods introduce a small perturbation to te grid current and tereby as some impact on power quality. Te advantage of te active metods is te reduction/elimination of te non-detection zone (NDZ). In addition to te two main groups, tere are also detection metods tat rely on communication wit te grid and inverter. A variety of passive metods ave been reported in literature suc as over/under voltage protection (OVP/UVP) and over/under frequency protection (OFP/UFP) metods [3]. Tese basic types of detection metods ave a large NDZ and terefore are not sufficient in most applications of DG systems. Oter types of passive detection metods include voltage pase jump [5], armonic voltage or current detection metods [6] as well as te passive metod proposed in [7] wic monitors te oscillations in rate of cange of frequency at te PCC. Te armonics based metods consist of eiter detecting cange in te total armonic distortion [6], detecting canges in te individual low order armonics [8], or monitoring te canges in te switcing armonics due to te PWM operation of te inverter [10]. A few examples of active metods of detection are, slidemode frequency sift (SMS) [11], active frequency drift and Sandia frequency sift (SFS) [11-14], Sandia voltage sift (SVS) [11], metods based on impedance measurement by armonic injection [15-18], impedance measurement by output power sift [8] and impedance measurement by active frequency drift [9]. Oter types of active metods include DQ-frame based feedback metods [19]; metods based on te perturbation of te reactive power [20, 21, 22] and second order generalized integrator (SOGI) PLL based metods [23] tat introduce a small disturbance in te pase of te inverter current. A more recent metod involves a multi principle local area measurement and communication based sceme were te islanding metod is applied to a refinery power system [24].

3 Altoug active metods significantly decrease te NDZ, tey sare te disadvantage of degrading te power quality to some degree and some of te active metods ave te disadvantage of causing instability to te grid in multiinverter scenarios [25]. Furtermore, wit te common prevalence of potovoltaic (PV) inverter systems, tere may be situations were te islanding detection mecanisms of multiple inverter systems wic are connected to te same utility, fail to detect islanding due to te interaction between tese systems [2]. II.! PROPOSED METHOD Tis paper presents a new detection tecnique tat as been developed to overcome te drawbacks of islanding detection scemes reported in literature. Te proposed islanding detection metod consists of monitoring te frequency spectrum of te voltage at te PCC (V PCC ). Wen islanding occurs, te sunt impedance at te PCC for ig frequencies increases and tis results in te increase of PWM voltage armonics. A fast Fourier transform (FFT) is performed on te V PCC signal for eac cycle of te fundamental frequency after wic te switcing armonic sidebands are compared wit te noise floor to obtain a relative magnitude. A look up table (LUT) is utilized to compare te obtained magnitude to te trip value for te given modulation index. Te decision logic ten determines weter islanding as taken place and if so, te inverter is sut down. Two sideband armonic components are used as te signature of te inverter s armonics for te detection of islanding wic provides a degree of immunity from false tripping due to external noise sources. Wilst PWM armonic voltage based anti-islanding as been reported in [10], no experimental demonstration as been performed. Te proposed metod differs from te metod reported in [10] troug utilisation of multiple armonic components, tereby detecting te unique signature of te inverter under consideration for te purposes of noise immunity. Furter extension of te algoritm wereby te PWM frequency is varied upon encountering multi-inverter interference is also investigated. Furtermore, te limitations common to bot te proposed metod and te metod reported in [10] due to large capacitive loads, as well as te positive effect of series impedance of te capacitive load on te ease of detection are investigated. correction. However, te series impedance (Z grid ) of te power lines must be considered in te model. Te circuit breaker (SW 1 ) represents te breaking point wen islanding occurs. H-Bridge VSC L 1 Fig. 1.! Equivalent model of inverter, RLC load and grid Te ig frequency voltage armonics are generated in te inverter due to te voltage source converter s (VSC) PWM operation and te individual armonic components can be quantified as given in (1) [26]. For te H-bridge inverter under investigation, unipolar PWM modulation sceme is utilized and terefore te armonics appear centred around integer multiples of te switcing frequency (10 khz), starting from double te switcing frequency onwards as illustrated in Fig. 2, were te armonic orders are normalized to te 50 Hz fundamental. As can be seen, te two side bands at 20 khz ±50 Hz ave te igest magnitude. V inv ( t) = V dc Mcos( ω o t) + (1) 4V dc 1 2m J 2n 1( mπ M )cos( m + n 1 π ) π m=1 n= L 2 ( ) cos 2mω sw t + 2n 1 ω o t R L PCC According to IEEE standard , current armonics over te 35 t order generated by te inverter must be lower tan 0.3% of te maximum load current for sort circuit current ratios lower tan 20. Terefore te inverter LCL filter can be designed to meet tese regulations. For te purposes of analysis and experiment, te following inverter specifications given in Table I are used. C SW 1 Z grid III.! MODELLING OF INVERTER LCL FILTER AND UTILITY GRID In order to analyze te beaviour of te grid-connected inverter upon islanding, it is necessary to establis a model of te system at te ig frequency level. Te scematic given in Fig. 1 represents te inverter s LCL filter, te RLC load and te grid. Te RL represents a combination of te most common resistive and inductive loads wile C represents capacitance for any power factor correction or armonic filtering. Te grid can be considered a sort circuit at te ig frequencies of interest due to te large capacitor banks tat are common for power factor Fig. 2.! Harmonics of unipolar PWM VSC switcing at 10 khz

4 TABLE I.! INVERTER SPECIFICATIONS Inverter active power L 1 L kw 5 mh 145 µh 6.8 µf 1.2 Ω For te ease of analysis, te inverter consisting of te VSC and LCL filter can be simplified by a Tévenin equivalent circuit as sown in Fig. 3 were e t () and Z t () are given by (2) and (3) respectively. Te impedance seen by te inverter before and after islanding for te parallel RLC load is defined by (4) and (5). Terefore te voltage armonics present at te PCC before and after islanding can be evaluated as given in (6) and (7). PCC between te igest level of non-islanded state voltage ripple and islanded state voltage ripple reduce to levels tat are not detectable for iger values of load capacitance. IEEE standard 929 states tat te islanding detection metod must be able to detect islanding for an RLC load tat is resonant at te grid frequency and aving a quality factor under 2.5. In order to quantify te detectable zone as a function of load capacitance C, te following Fig. 4 is presented wereby te grid impedance, Z grid, at ig PWM frequencies is assumed to be zero for a 2.2 kw power level. Te figure sows te variation of armonic voltage difference ΔV() before and after islanding for an RLC load resonant at 50 Hz. Z t SW 1 Z grid e t () R L C Fig. 3.! Tévenin equivalent circuit of inverter wit RLC load e t Z t 1+ jω ( ) =.V 1+ jω ω 2 inv L 1 ( ) = ( ) + L 1 1+ jω jω L 2 ( 1+ jω ω 2 L 1 C 1 ) 1+ jω ω 2 L 1 Z pre islanding V PCC pre islanding Z post islanding ( ) (2) (3) ( ) = R! L! C! Z (4) grid ( ) = ( ) = R! L! C (5) Z t e t ( ) ( ) + Z pre islanding ( ). Z pre islanding ( ) (6) Fig. 4.! Difference in voltage ripple (20.05 khz) for an RLC resonant load wit varying load capacitance Altoug te ideal grid condition of 0 Ω for ig frequencies as been assumed for analysis of te detection zone, in practice te series grid inductance at te switcing frequency will be a finite value, wic sets te baseline value of te voltage armonics above wic te trip tresold lies. Furtermore, in reality te parallel RLC load will ave a series impedance component wic represents cable effect at te switcing frequency as well as ESR of te load capacitance and load inductance as sown in Fig. 5. Z t Z rlc Z grid V PCC post islanding ( ) = Z t e t ( ) ( ) + Z post islanding ( ). Z post islanding ( ) (7) R L R esr R L C It is clear tat during islanding, te impedance at te PCC for switcing frequencies increases due to te absence of te low impedance sunt component of te grid. It is tis increase tat also causes an increase in te voltage armonics tat appear at te PCC, wic is te basis of te detection metod. However, as te capacitance of te RLC load increases, te post-islanding impedance for te switcing frequencies decreases. Terefore te difference Fig. 5.! RLC load wit parasitic impedance elements TABLE II.! CONDITIONS FOR THE RIPPLE VOLTAGE ANALYSIS Symbol Description Value P Inverter active power 2.2 kw R Load resistance 26 Ω

5 Symbol Description Value C Load capacitance 0 to 350 µf sweep R L Inductor series resistance 10 mω R esr Capacitor ES0 mω Z rlc (20 khz) RLC series impedance 0 to 5 Ω Z grid (20 khz) Grid impedance 2.5 Ω M Modulation index 0.62 initiates te FFT transform. Te iger sampling frequency and ence te 8k size for te FFT is used to increase te FFT process gain, tereby increasing te signal-to-noise ratio (SNR) as te design is a proof of concept. For actual implementation, te sampling rate and resulting FFT size may be reduced dramatically. After te data is processed troug te FFT logic, data points except te armonic sideband components are averaged to obtain te noise floor. Te level of te noise floor is subsequently cecked for any interference as a form of sanity ceck. Te final part of te algoritm is te comparator logic, wic compares te 2 armonic components (19.95 khz and khz) to te detection tresold in te LUT (predefined as worst-case ripple +5% for te operating power range). If bot components are above te trip limit, te logic asserts te islanding detected signal. Tis process repeats itself every ~20 ms (20 ms capture window + FFT process time wic depends on te FPGA speed and actual FFT size used in final implementation) and terefore te typical detection time is also ~20 ms. Fig. 6.! Voltage ripple after islanding as a function of load capacitance (C) and series impedance at 20 khz ( Z rlc (20 khz) ) V g Attenuation ( db) BPF ADC ksps Buffer Fig. 6 sows te variation in post-islanded switcing voltage ripple (20.05 khz) present at te PCC for te conditions given in Table II for an RLC load resonant at 50 Hz (Te value for L is cosen for resonance at 50 Hz). In Fig. 6, islanding is detectable if te magnitude of te post islanding voltage ripple lies above te detection tresold plane. Te detection tresold plane is defined as a value tat is 5% larger tan te worst-case value of voltage ripple present under normal operation (i.e. wen no RLC load is connected to te inverter and te inverter is not islanded). It is found tat islanding is detectable for all values of series impedance, Z rlc (20 khz) for load capacitances tat are under 3.65 µf. For series impedances iger tan 2.75 Ω, islanding is detectable for all values of load capacitance. Te effect of spurious noise tat can be present in te sensed voltage is minimized by comparing bot armonic components (19.95 khz and khz) to te tresold values. A.! Detection Algoritm IV.! ISLANDING DETECTION Te block diagram of te islanding detection algoritm is illustrated in Fig. 7 and te detailed flow cart is given in Fig. 8 (a). Voltage at te PCC (V g ) is first attenuated after wic it is band-pass filtered. Tis stage removes te fundamental (50 Hz) signal tereby maximising te ADC s dynamic range as well as removing out-of-band signals tat are not of interest. Te ADC digitises te filtered signal after wic te signal is processed in te FPGA. Te data processing is overseen by te control logic, wic first takes 8192 data samples (20 ms of data = 1 cycle of te fundamental) from te ADC to te FIFO memory and Control Fig. 7.! Block diagram of islanding detection algoritm Start Inverter Capture 20 ms of samples FFT Average noise floor Is noise floor below tresold? Compare armonics Are te armonics above tresold? (a) Islanded Scan frequency spectrum Start inverter Capture 20 ms of samples FFT Average noise floor Is noise floor below tresold? Compare armonics Are te armonics above tresold? Scan spectrum & cange PWM frequency LUT FFT Compare Islanded? Fig. 8.! (a) Islanding detection algoritm. (b) Islanding detection algoritm for multi-inverter operation (b) Capture 20 ms of samples Islanded Are te armonics above tresold? Compare armonics Is noise floor below tresold? Average noise floor FFT

6 B.! ise immunity from oter switcing converters It is possible tat oter power converter systems operating nearby to te inverter could cause a false trip if te external systems operate at te same switcing frequency, tereby causing te magnitude of te voltage armonics to exceed te tresold value. If noise immunity from oter switcing converters is a design criterion, te detection logic can be configured to dynamically cange te inverter PWM frequency for te subsequent cycle of fundamental frequency upon detection of te first trip condition. Te 2 nd PWM modulation frequency to be opped to is determined by scanning te adjacent spectrum (20 khz ±4 khz), and selecting a frequency tat as a low level of noise present, and is an integer multiple of te grid frequency. If te spectrum of te subsequent cycle also matces te sideband caracteristics for islanding condition, it can be determined tat actual islanding as taken place and inverter operation ceased. Te detailed flow cart of te islanding detection algoritm for multi-inverter operation is illustrated in Fig. 8 (b). It must be noted tat te amount of inverters tat can be supported by te islanding detection algoritm is limited to te spectral bandwidt (20 khz ± 4 khz in tis instance) and terefore optimum utilization may be obtained by interleaving te spectrum. For instance, if ±3 sideband armonics around 20 khz are considered (19.75 to khz), it is observed tat te armonics are separated by 100 Hz and ence occupies a bandwidt of 500 Hz. Terefore, it is possible to interleave anoter inverter between te armonic spurs tat are separated by 100 Hz, yielding a total bandwidt of 600 Hz for 2 inverters. Terefore, te 16 khz - 24 khz band can support 13 pairs of inverters, or 26 in total. As an example, in a residential application, eac utility pase in a neigbourood may contain 26 separate inverters. Eac inverter must terefore scan te available band and self-allocate a suitable switcing frequency before initiating power switcing. V.! SIMULATION OF ISLANDING ALGORITHM Te algoritm as been simulated in MATLAB using te SimPowerSystems toolbox to validate its performance. Te first simulation test case consists of islanding under an RLC load tat is resonant at 50 Hz were te RLC parameters are listed in Table III. Furtermore, te PWM frequency opping multi-inverter (2 inverters simulated) islanding detection algoritm as been validated in Simulink for wic te conditions are also sown in Table III. TABLE III.! SIMULATION TEST CONDITIONS Parameter RLC Load (Resonant) Test Multi Inverter Test R Ω Ω L mh t Used C 300 µf t Used R L 10 mω N/A R esr 10 mω N/A Parameter RLC Load (Resonant) Test Multi Inverter Test Z rlc (20 khz) 2.75 Ω N/A Z grid (20 khz) 2.5 Ω 2.5 Ω A.! Simulation case 1 RLC resonant load Since te RLC load is resonant at 50 Hz, te islanding condition lies in te NDZ of te OVP/UVP and OFP/UFP metods. Fig. 9 and Fig. 10 sow te V PCC, inverter current and V PCC spectral content variation over time. It can be observed tat te islanding is successfully detected after 20 ms (1 electrical cycle) after islanding occurs. After islanding, te magnitude and te frequency of V PCC s fundamental component continue to be unaffected, but te voltage ripple of te khz component (and khz) increases to 77 mv from 49 mv after islanding. Terefore islanding is successfully detected, as te detection tresold is 76 mv. Fig. 9.! V PCC, inverter current and V PCC frequency (RLC Load) Fig. 10.!Time domain plot of te V PCC spectral content (RLC Load) B.! Simulation case 2 detection of islanding under multiple inverter operation In te situation were immunity from false tripping due to oter converters operating wit te same PWM frequency is required, te adaptive PWM opping metod can be used at te cost of increasing te detection time from ~20 ms to ~40 ms (2 electrical cycles). Te simulation can be summarized as follows, were te device under test in wic te islanding detection algoritm

7 is applied is referred to as Inverter 1 and te external system tat causes interference is referred to as Inverter 2. Initially Inverter 2 is non-operational and Inverter 1 feeds power to te utility grid. At t = 0.6 s, Inverter 2 starts operating at te same 10 khz device switcing frequency (20 khz armonics generated), wic causes te armonics seen at te PCC to increase as sown in Fig. 11. and te low voltage controller is introduced after te ADC stage wit te use of ADUM1400 digital isolators. Te resistor divider attenuates te grid voltage by a factor of 52 (34.32 db) in order to reduce te peak value of te signal to under ±7 V so as to be compatible wit te analogue signal conditioning circuit. In order to maximize te dynamic range of te ADC, te fundamental grid frequency component is removed by filtering and te remaining ig frequency signal is amplified prior to digitisation. An active band-pass filter was designed for tis purpose, wic also serves as te anti-aliasing filter for te ADC. Fig. 12 sows te frequency response of te 4 t order multiple feedback Cebysev band pass filter tat was designed for te filtering. Since te dominant switcing armonics appear at 20 khz, te pass-band of te filter was cosen to be between 16 khz-24 khz wit a gain of 34 db and attenuation at te fundamental frequency (50 Hz) of -87 db. Fig. 11.!Time domain variation of te V PCC spectral content (2 inverter case) At t = 0.62 s, upon detection tat te armonic voltage limits ave been exceeded, te islanding prevention algoritm of Inverter 1 scans te adjacent spectrum for a suitable frequency wit low interference, and canges its PWM frequency to 10.5 khz (armonics at 21 khz). After te subsequent electrical cycle (at t = 0.64 s), te FFT of V PCC reveals tat te armonic spectrum for Inverter 1 is below te limits tat would be identified as being islanded. Terefore Inverter 1 continues to operate at 21 khz. At t = 0.68 s, actual islanding occurs were te breaker opens and terefore te 2 inverters (bot operating at 2.2 kw) continue to power te local resistive load. At t = 0.7, te islanding detection algoritm detects te increased voltage armonics and terefore canges te PWM frequency to 9.5 khz (causing voltage armonics to appear at 19 khz). In te following electrical cycle (t = 0.72), it can be seen in Fig. 11 tat despite te frequency jump, te armonics are still at te increased level (234 mv). Terefore, at t = 0.72 s, islanding is detected since te algoritm detected increased armonics in 2 consecutive cycles of te grid voltage. Te proposed algoritm for islanding detection as terefore been sown to provide immunity from false tripping due to external power converters operating at te same PWM frequency. VI.! DESIGN OF ISLANDING DETECTION HARDWARE A.! Voltage detection ardware design Te detection of te small signal ig frequency components present at te PCC can be acieved by sampling te grid voltage troug an ADC converter. However, since most commercially available voltage transducers are not able to detect signals wit bandwidt exceeding 20 khz, a resistor divider based circuit is designed were te isolation between te ig voltage side V in Gain (db) Frequency (Hz) Fig. 12.!Voltage sensing circuit band pass filter frequency response R1 R3 C C2 - + R2 Fig. 13.!Band pass filter scematic Tis configuration allows te full dynamic range of te ADC to be utilized wilst preventing saturation of te ADC at te igest value of ripple voltage (i.e. wen islanding takes place wit a purely resistive load). Te scematic of te op-amp based filter circuit is sown in Fig. 13. A 16-bit SAR ADC converter (ADS8422) tereafter digitises te signal wit a sampling frequency of ksps. Te ADC output is carried in an 8-bit data bus and terefore te data bus is clocked at twice te sampling frequency. Te ADC is interfaced troug tree ADUM1400 digital isolator cips, wic provide te galvanic isolation required for safety. An NI crio-9082 controller is used for processing te data for te experimental demonstration. R4 R6 C3 C4 - + R5 V out

8 B.! Inverter current detection circuit ardware design A current sensing circuit as been designed wit similar band pass caracteristics as te voltage sensing circuit wit an independent ADC. Altoug te current sensing circuit is not used in te detection of islanding, it serves te purpose of measuring te grid impedance at 20 khz frequency for analysis purposes. Te current sensing element consists of a 10 mω sunt resistor troug wic te inverter current passes. Te voltage signal tat appears across te resistor due to te PWM ripple current is small in magnitude and terefore te succeeding filter stage is designed wit a ig gain at te pass band frequency. For instance, if te ripple current magnitude is assumed to be 0.3% of te fundamental current, te rms value of voltage present across te sunt resistor due to te ripple current is only 275 µv. Te filter circuit consists of a 6t order multiple feedback Cebysev band pass filter wit a pass band of 16 khz-24 khz, pass band gain of 60 db and attenuation of db at 50 Hz. Since te filter contains 6 poles, it is implemented wit 3 op-amps. VII.!EXPERIMENTAL RESULTS Te experimental setup used for te islanding tests is sown in Fig. 14. Te inverter is connected to te grid and te load via a low frequency (50 Hz) isolation transformer. A dedicated isolation and data acquisition board is designed and constructed. Te inverter control and island detetion algoritms are implemented on NI CRIO (a) (b) Lg C Transformer (c) Inverter (d) Fig. 14.!Experimental setup tat was used for islanding test. (a) Low frequency transformer based inverter. (b) Inductor (318 mh) used for RLC test. (c) Islanding detection data acquisition circuit (d) NI crio-9082 used for data processing and detection algoritm A.! Estimation of grid impedance Te magnitude of te grid impedance at 20 khz ( Zgrid(20 khz) ) can be estimated by measuring te magnitude of te ig frequency components of VPCC and Ig during operation of te inverter wen te RLC load is not connected. Te results tat were obtained for te utility grid of te laboratory wen te inverter was operating at 2.2 kw are given in Table IV. TABLE IV.! ESTIMATED GRID IMPEDANCE FROM MEASURED VALUES OF VOLTAGE AND CURRENT RIPPLE Parameter Value Parameter Value VPCC(19.95 khz) 73.4 mv VPCC(20.05 khz) 72.2 mv Ig(19.95 khz) 30.0 ma Ig(20.05 khz) 30.1 ma Zgrid(19.95 khz) 2.44 Ω Zgrid(20.05 khz) 2.39 Ω Te experimentally derived ig frequency grid impedance value as been utilized as a starting point for determining te worst-case ripple magnitude. It must be noted tat in practical realization of te system, te maximum acceptable grid impedance for ig frequencies must be determined on a case-by-case basis dependant on te grid configuration (for wic te detailed analysis is beyond te scope of tis paper). B.! Resistive load islanding test Experimental validation as been carried out for an islanding condition wit a purely resistive load (26.2 Ω) at 2.2 kw, and te results are depicted in Fig. 15 and Fig. 16. In Fig. 15, te band pass filtered ADC captured data is sown togeter wit te magnitude of te khz voltage armonic component (from te FFT of te band pass filtered signal). Te islanding takes place at t = 0.011s, and te system detects te islanding at 0.02 s (9 ms detection time). Since te FFT is performed for eac cycle (20 ms), te first FFT magnitude value is lower tan te steady-state islanded magnitude since te FFT time window contains bot islanded and non-islanded data in te first cycle. It must be noted tat te system is allowed to operate after te islanding is detected to observe te beaviour under islanding condition. Since te resistive load is not resonant at 50 Hz and due to te difficulty in aving an exactly matced active load in te experiment, te dynamic beaviour of te system is suc tat te inverter output frequency increases after te islanding and te inverter is subsequently sut down after a few cycles for protection. Of course, it is possible to implement droop control after te islanding for stable islanded operation, but tis is beyond te current scope. Neverteless, it is evident tat te resistive load islanding is detectable.

9 Fig. 15.!Islanding test waveforms for resistive load test (top: voltage and inverter current at PCC, middle: te band pass filtered signal from te ADC, bottom: te FFT magnitude of te khz component) Fig. 16 sows te pre and post islanding (steady state) voltage ripple. Te pre-islanding voltage ripple of te khz component is mv and under post islanding, it reaces mv. Te values obtained experimentally compare to te analytical prediction of 70.5 mv and mv, and to te numerical simulation results of mv and mv for pre- and post-islanding cases, respectively. It can be seen tat te predicted and measured pre-islanding ripple matces. Te iger value of post islanding voltage ripple can be attributed to te series inductance of te load resistor bank, wic is neglected in analytical prediction and in numerical simulation X: Y: Before Islanding After Islanding measured voltage for 7 ms, te experiment outcome is not affected. It can be seen tat islanding is successfully detected for te RLC load under consideration. Te preislanding voltage ripple of te khz component is 55.1 mv and after islanding, it reaces mv. Te values obtained experimentally compare to te analytical prediction of 57.6 mv and mv for pre- and postislanding cases, respectively. It is observed tat te predicted and measured post-islanding ripples matc better tan te purely resistive test case. Tis is because te load resistor bank s series inductance is te reason for te large difference between te prediction and measurement tat appears during te resistive load test. However, it can be seen tat in te RLC load test, te capacitance is te dominant sunt component for ig frequencies and terefore te series inductance of te load resistor as a negligible affect on te post-islanding ripple. In simulations, te system wen islanded wit a RLC load tat is resonant at 50 Hz is capable of continuous operation. However, during te experimental tests wit an RLC load, it was observed tat te system becomes unstable after ~0.5 s of te islanded operation. Tis is attributed to te noise and oter disturbances tat occur in te experiment because te PLL and te current control loop is igly sensitive to tese disturbances and terefore causes te voltage/frequency to drift beyond te safe limits. R (Ω) TABLE V.! RLC TEST CONDITIONS L (mh) C (µf) R L (Ω) R esr (mω) Z rlc (20 khz) (Ω) V PCC (mv) X: Y: Frequency (khz) Fig. 16.!Islanding test frequency spectrum for resistive load test C.! RLC load islanding test Te RLC load-based islanding detection test as been carried out wit te conditions depicted in Table V for an inverter power output of 2.2 kw. Te resulting waveforms are presented in Fig. 17 and te spectrum of te switcing frequency armonics in Fig. 18. Islanding takes place at t = s and is detected at t = 0.06 s (9 ms detection time). Similar to te resistive case, te first FFT output after te islanding contains bot pre and post islanding data, and terefore te magnitude is initially lower tan te steadystate islanded armonic magnitude. Furtermore, at t = s, contact bounce due to arcing occurs on te relay tat emulates te islanding andextinguises at t = s. Altoug tis contact bounce causes a transient in te Fig. 17.!Islanding test waveforms for RLC load test (top: voltage and inverter current at PCC, middle: te band pass filtered signal from te ADC, bottom: te FFT magnitude of te khz component)

10 V PCC (mv) X: Y: X: Y: Frequency (khz) Fig. 18.!Islanding test frequency spectrum for RLC load test VIII.!CONCLUSION A new islanding detection algoritm as been presented wic as te advantage of multi-inverter compatibility compared to similar voltage armonic monitoring metods. Furtermore, te difficulty in detection for PWM armonic based metods wen capacitive loads are present as been analyzed and te detectable conditions as a function of te load s caracteristics establised. Te algoritm as been simulated and two test cases demonstrated experimentally in ardware. Te detection ardware designed and demonstrated erein as been over-engineered since te exercise was purely as a proof-of-concept. It follows from analysis of te measured signal-to-noise ratio (SNR: 124 db relative to 340 V peak grid voltage) and spurious free dynamic range (SFDR: 71 dbfs) of te prototype detector, tat te ardware may be optimized in terms of ADC resolution and sample rate to acieve a trade-off between performance and cost. In particular, it is feasible to use te integrated 12- bit ADCs tat are common in many low cost DSP/microcontrollers tat are used in te control of grid converters. Te requirement for computing power can be minimized by eiter optimising te FFT lengt or by utilising an optimized version of an FFT algoritm tat caters only for te frequency range of interest. Te proposed frequency opping metod may also be suitable for oter active islanding detection scemes were low order armonics are injected. Furter investigations are required for its applicability in tese scemes. REFERENCES Before Islanding After Islanding [1]! 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