TODAY S wireless communication standards, including

Transcription

1 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 1 A Quasi-Doherty SOI CMOS Power Amplifier With Folded Combining Transformer Kichul Kim, Student Member, IEEE, Dong-Ho Lee, and Songcheol Hong, Member, IEEE Abstract A fully integrated transformer-based quasi-doherty power amplifier (DPA) with an adaptive power divider (APD) is presented in this paper. A novel folded combining transformer is designed for power combining, which has smaller insertion loss than a conventional one. An APD adaptively controls the power delivered to carrier and peaking amplifiers by altering the input impedance of the peaking amplifier, which has a variable resonance frequency that changes according to the input power. Most of the power is delivered to the carrier amplifier at low incoming power, and it is divided between the carrier and the peaking amplifiers at high incoming power. With continuous wave signal at 1850 MHz, the quasi-dpa implemented with an SOI CMOS process achieves 39.8% and 44.4% power-added efficiencies (PAEs) at the first and the second peak, respectively. With wideband code division multiple access signal, it has 29.2-dBm average linear output power and a 40.47% PAE with a 33-dBc adjacent channel leakage ratio 1. With long-term evolution (LTE) signal, it delivers 27.2-dBm average linear output power and a 37.7% PAE, satisfying linearity requirements for the LTE. Index Terms Adaptive bias circuit (ADB), adaptive power cell (APC), adaptive power divider (APD), folded combining transformer (CT), power amplifier (PA), quasi-doherty, SOI CMOS. I. INTRODUCTION TODAY S wireless communication standards, including wideband code division multiple access (WCDMA), long-term evolution (LTE), time division-synchronous code division multiple access, LTE advanced, and wireless local area network (WLAN), use complicated modulation schemes to utilize limited frequency bands effectively. The high peakto-average-power ratio (PAPR) in these complex modulation schemes makes it difficult to design power amplifiers (PAs), since these usually have to operate with large back-off power (BOP) for high linearity. This large BOP causes not only reduced linear output power but also decreased efficiency at the output power. This eventually reduces the battery lifetime of mobile phones. Manuscript received September 16, 2015; revised February 29, 2016, April 26, 2016, and May 30, 2016; accepted June 01, This work was supported by the Korean Government (MEST) under the National Research Foundation of Korea (NRF) Grant 2014R1A2A1A and the Samsung Electro-Mechanics Company, Ltd. K. Kim and S. Hong are with the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon , South Korea ( kimkc@kaist.ac.kr; schong@ee.kaist.ac.kr). D.-H. Lee is with the Department of information and communication Engineering, Hanbat National University, Daejeon , South Korea ( dhlee@hanbat.ac.kr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TMTT Many groups have studied techniques to improve the efficiency of linear PAs with large BOP. For example, envelope tracking techniques [1], [2], polar modulation techniques [3], [4], and Doherty architectures [5] [8] have been proposed. A Doherty PA (DPA), which consists of main and auxiliary amplifiers, uses load modulation to improve efficiency at BOP. From low output power to BOP, the main amplifier only turns ON with its optimized load impedance to achieve high efficiency. The auxiliary amplifier starts to operate near BOP, changing load impedance. Finally, two amplifiers operate simultaneously in the range from BOP up to saturation output power with their optimized loads with the help of load modulation. Therefore, the improved efficiencies at both BOP and high output power can be achieved with the Doherty architecture. On the other hand, the conventional Doherty architecture needs λ/4 transmission lines at the input and output networks [5], [6]. This leads to a size issue due to their bulky sizes, so previous works have studied off-chip equivalent components for mobile handset applications [7], [8]. However, this is not the best solution, because off-chip matching networks increase the form factors of front-end modules. Therefore, the most appropriate Doherty architecture for mobile phones may be a fully integrated quasi-doherty architecture, which does not use λ/4 transmission lines or their equivalents. This paper proposes a fully integrated quasi-dpa with a novel folded combining transformer (CT), which has reduced insertion loss, smaller size, and wider bandwidth characteristics than a conventional CT. In addition, an adaptive power divider (APD) distributes the driving power to the main and auxiliary amplifiers properly according to the incoming power. In this paper, a quasi-doherty architecture with a novel folded CT is discussed in Section II. The APD is proposed and analyzed in Section III. In Section IV, the implemented SOI CMOS chip and its measured results are presented. The conclusions and performance comparisons with other reported PAs are given in Section V. II. QUASI-DOHERTY PA WITH A FOLDED CT A conventional DPA, as shown in Fig. 1(a), comprises two amplifiers (main and auxiliary PAs) and λ/4 transmission lines. The main and auxiliary PAs are typically biased in class-ab and class-c modes, respectively. In the low power region, only the main PA turns ON with 2 Z opt load impedance for high efficiency at BOP. When the main PA is close to its saturation power, the auxiliary PA starts to operate. At the same time, the load impedances for the two PAs start to change from 2 Z opt to Z opt for the main PA and from infinity IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 2 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES Fig. 2. Proposed CT. (a) Increased self-inductance of secondary transformer from the folded structure. (b) Z-parameter model of the proposed CT when the auxiliary amplifier turns ON or OFF. as in [5] and [6]. They also generate significant losses. The transformer-based quasi-dpa, which obviates the λ/4 transmission lines and related issues, is shown in Fig. 1(b). It can be fully integrated into a chip for mobile phones. It has similar load modulation for DPA with the CT instead of large transmission lines. However, the conventional series CT (SCT), as shown in Fig. 1(c), still occupies a large area (almost double that of a single transformer) on a chip [9] [12]. In addition, it has significant insertion loss and poor bandwidth characteristics. Therefore, we propose a novel folded CT, as shown in Fig. 1(d), which has reduced chip area and insertion loss. Moreover, it provides wider bandwidth characteristics than the conventional SCT. Fig. 1. Structures of DPAs and CTs. (a) Conventional DPA. (b) Transformerbased quasi-dpa. (c) Conventional SCT. (d) Proposed folded CT. to Z opt for the auxiliary PA [5] [8]. This load modulation is achieved with the help of λ/4 transmission lines in the output of the main PA. The λ/4 transmission line in front of the auxiliary PA adjusts its signal phase to reduce combining losses due to the phase difference between the main and the auxiliary PAs output signals. As a result, the output power of a DPA can be typically increased 6 db with the help of the load modulation of the PAs. However, λ/4 transmission lines in the conventional Doherty architecture cause bulky size, A. Structure of the Proposed Folded CT The SCT is folded in the proposed CT. The secondary part of the transformer for the auxiliary amplifier is loosely coupled with the primary part for the main amplifier, as shown in Fig. 1(d). The shared secondary part allows parallel power combining with the SCT structure. With the help of the proposed folded structure, the secondary part has additional self-inductance (positive mutual inductance) of β L S,where β is a variable number according to the figure of the transformer, and L S denotes the secondary transformers for the main and auxiliary amplifiers, as shown in Fig. 2(a), which increases the total inductance of the secondary part and changes the turn ratio (n) of the transformer by the following

3 KIM et al.: QUASI-DOHERTY SOI CMOS PA WITH FOLDED CT 3 equation [13]: L S n = (1) L P TABLE I SIMULATED PARAMETERS FOR LOAD MODULATION where L P and L S are the self-inductances of the primary and secondary transformers, respectively. The increased turn ratio of the transformer from the increased secondary inductance finally increases the mutual inductance between the primary and secondary transformers [13]. The schematic of the folded CT is shown in Fig. 2(b). As mentioned earlier, the secondary part for the auxiliary amplifier is loosely coupled with the primary part of the main amplifier. When only the main amplifier operates at a low power level, all of the secondary parts are used to get the coupled power from the primary transformer part of the main amplifier. However, with the conventional SCT, some of the secondary transformer part for the auxiliary amplifier is not used, and this causes losses. Therefore, the proposed folded CT improves the coefficient of magnetic coupling (k-factor) of the transformers with the help of k1, as shown in Fig. 2(b), where k1 isthek-factor between the primary part of the main amplifier and the secondary part for the main amplifier, and k1 is the k-factor between the primary part of the main amplifier and the secondary part for the auxiliary amplifier. This finally improves the overall efficiency of the DPA. B. Load Modulation With the Proposed Folded CT The Z-parameter model for the proposed CT is shown in Fig. 2(b). L P1, L P2,andL S represent the inductances and R P1, R P2,andR S are the series resistances in the primary and secondary transformers, respectively. M 1 and M 2 are mutual inductances between two primary transformers and the secondary transformer. This Z-parameter model can be denoted as follows: V MAIN V AUX = V OUT R P1 + jωl P1 0 jωm 1 0 R P2 + jωl P2 jωm 2 jωm 1 jωm 2 R S + jωl S I MAIN I AUX I OUT M 1 = k 1 L P1 L S α M 2 = k 2 L P2 L S (1 α) (2) where V MAIN, V AUX, V OUT, I MAIN, I AUX,andI OUT represent the voltages and the currents in the primary and secondary transformers, respectively. k1 and k2 are coupling factors between the primary transformers and the secondary transformer, and α is the ratio of the secondary transformer for the main amplifier to all secondary transformers. The load impedances for the main and auxiliary amplifiers can be calculated as the following two Fig. 3. Load-pull results of (a) main and (b) auxiliary amplifiers and simulated load impedance modulations when auxiliary amplifier turns OFF and ON. equations [9]: Z main = R P1 + jωl P1 + (ωm 1) 2 (1 + I AUX /I MAIN ) α (R S + jωl S ) + Z Load1 Z Load1 = Z Load α + 2 (Z Load (1 α)) (3) Z aux = R P2 + jωl P2 + (ωm 2) 2 (1 + I MAIN /I AUX ) (1 α) (R S + jωl S ) + Z Load2 Z Load2 = 2 (Z Load (1 α)) (4) where Z Load, Z Load1, and Z Load2 are the load impedance (normally 50 ), the load impedance for the main amplifier, and the load impedance for the auxiliary amplifier. The number 2 for Z Load1 and Z Load2 in (3) and (4) is from the folded structure, because the secondary transformer part only for auxiliary amplifier in a conventional CT is also used for the main amplifier in the folded one. When the auxiliary amplifier turns OFF, with parameters in Table I, the calculated load impedance for the main amplifier at the center frequency (1.85 GHz), considering shunt capacitors (3.7 pf for the main amplifier and 2 pf for the auxiliary amplifier), is j When the two amplifiers operate simultaneously, the calculated load impedances for the main and auxiliary amplifiers are j7.22 and j13.45, respectively. In Fig. 3, the simulated load modulations are plotted. The some discrepancy between the calculated and simulated load impedances is due to the parasitic components, which are not considered in the calculation. The main amplifier maintains its output power and efficiency when the auxiliary amplifier turns ON, as shown in Fig. 3(a), and the auxiliary amplifier changes from infinite to its optimum impedance, as shown in Fig. 3(b). With

4 4 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES TABLE II TRANSFORMER T-MODEL PARAMETERS the auxiliary amplifier is open. In addition, the MAG through the auxiliary path is reduced from 1.28 to 0.9 db, assuming that the impedance looking into the main amplifier is open. Fig. 4(a) and (b) shows the simulated insertion losses on the main and auxiliary paths with the conventional SCT and the proposed CT. As seen in Fig. 4(a) and (b), all insertion losses are reduced with the proposed CT structure. This reduced insertion loss finally helps improve the overall efficiency of the quasi-dpa. The drain efficiencies with the proposed CT could be improved 2.04% and 3.68% at the BOP and the peak output power, respectively. The size of the proposed folded CT on the chip is significantly decreased compared with the conventional SCT. The conventional SCT occupies 1950 μm 750 μm onthechip, but the CT with the proposed structure has the dimensions of 1050 μm 750 μm, as shown in Fig. 1(c) and (d), respectively. The folded CT is almost half the size of the conventional SCT structure. The CT with the folded structure has an increased k-factor between the primary and secondary parts, as shown in Table II. The improved k-factor increases the shunt inductance L a in the transformer T-Model [13], as shown in Fig. 4(c). This shunt inductance is inversely proportional to the node Q-factor (Q n ). The reduced Q-factor in the proposed CT improves the bandwidth characteristics of the transformer itself. Finally, as shown in Fig. 4(a) and (b), the simulated 0.1-dB bandwidths are improved from 170 to 390 MHz on the main path and from 160 to 260 MHz on the auxiliary path. Fig. 4. Characteristics of the proposed CT. (a) Insertion loss on main path. (b) Insertion loss on auxiliary path. (c) Bandwidth characteristic using transformer T-Model. this load modulation, the proposed quasi-dpa enables efficient operation of the main amplifier and additional output power from the auxiliary amplifier. C. Advantages of the Proposed Folded CT By employing the folded structure, the insertion loss without reflectionlosses[maximumgain(mag)],whichwassimulated through the main path, is reduced from 0.72 to 0.59 db with an improved k-factor between the primary and secondary transformer parts, assuming that the impedance looking into III. DESIGN OF A QUASI-DOHERTY PA WITH AN ADAPTIVE POWER DIVIDER The architecture of the proposed quasi-dpa is shown in Fig. 5. The main amplifier comprises a common source transistor of 3456/0.32 μm and a common gate transistor of 2048/0.32 μm. The auxiliary amplifier has a common source transistor of 4096/0.32 μm and a common gate transistor of 5120/0.32 μm. The proposed quasi-dpa has a folded CT in the output matching network, and this provides several advantages, namely, reduced insertion loss, small size, and wideband characteristics. In addition, the quasi-dpa uses the adaptive power cell (APC) technique, which was already studied regarding the linearity of the main amplifier [14]. An adaptive bias circuit (ADB) [15] was designed for the auxiliary amplifier, and it is biased in class-c. It increases the small gain of the auxiliary amplifier; the increased gain not only complements the AM AM distortion of the quasi-

5 KIM et al.: QUASI-DOHERTY SOI CMOS PA WITH FOLDED CT 5 Fig. 5. Overall schematic of the quasi-doherty SOI CMOS PA with the folded CT. Fig. 7. Simulated powers delivered to main and auxiliary amplifiers in DPA with the APD. levels. The APD circuit located in front of the auxiliary amplifier is considered as a variable capacitor between the gate nodes of M3 andm4, and it controls the incoming power to the auxiliary amplifier. A detailed analysis of the APD is presented in Section III-A. Fig. 6. Operation principle of the APD. (a) Schematic of the APD. (b) Simulated M1 resistance according to the output power. DPA [8], but also makes load modulation perfect for Doherty operation. Imperfect load modulation occurs due to the insufficient drain current of the auxiliary amplifier because of its small gain, as in [16]. An APD is designed for proper power dividing between the main and auxiliary amplifiers according to delivered power A. Adaptive Power Divider Fig. 6(a) shows the structure of the APD, which comprises two capacitors (C1 andc2), a transistor (M1), and a resistor (R1). With a low incoming power, M1 is mostly in the triode region. However, with a high incoming power, M1 is in the saturation and cutoff regions as well as the triode region, as shown in Fig. 6(a). The resistance r ds of M1 is increased with high incoming power, because it is in the saturation and cutoff regions, as shown in Fig. 6(b). The increased resistance of M1 controls the total capacitance of the APD, which is written as Imag(Y eq ) of the equivalent

6 6 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES Fig. 9. Photograph of a quasi-dpa chip. The capacitance of the APD resonates with the inductance L1 of the input transformer shown in Fig. 6(a). This parallel LC resonating circuit at the input of the auxiliary amplifier operates as a variable bandpass filter. The power delivered to the main and auxiliary amplifiers is adaptively controlled by the power-dependent characteristics of the bandpass filter. As shown in Fig. 7, the power delivered to the two amplifier inputs was simulated for the cases of low and high incoming power. With a low incoming power, the levels of delivered power delivered to the main and auxiliary amplifiers were 2.34 and db, respectively. In this case, the power delivered to the auxiliary amplifier was very low in comparison with that delivered to the main amplifier. This is because the resonating frequency of the APD was close to 0.9 GHz and quite far from the operation frequency. On the other hand, the resonating frequency changed to the operation frequency of 1.85 GHz when the incoming power increased. Therefore, with high incoming power, the levels of power delivered to the main and auxiliary amplifiers were 4.67 and 4.15 db, respectively. The APD controlled most power delivered to the main amplifier at low incoming power, and it divided power almost equally into the two amplifiers at high incoming power. Fig. 8. IMD3 canceling mechanism in DPA. (a) Principle of IMD3 canceling. (b) Simulated phase differences of fundamental and IMD3 signals at the two amplifier outputs. (c) Two-tone simulations (gain and PAE) of the proposed quasi-dpa. (d) Two-tone simulations (IMD3) of the proposed quasi-dpa. Y -parameter in Fig. 6(a). Therefore, the total capacitance is determined by both C1 andc2 at low incoming power, and it approaches C1 at high incoming power. B. Linearity of a Quasi-Doherty PA The linearity of a PA is one of the most important issues for mobile applications. Previously, designed DPAs [5], [6] are optimized for their efficiency. Their linearity is not guaranteed without digital predistortion for mobile communications, such as WCDMA, LTE, WLAN, and so on. However, the linearity of a DPA can be improved by using a third-order intermodulation distortion (IMD3) canceling technique, because the main and auxiliary amplifiers of a DPA are biased differently in class-ab for a main amplifier and class-c for an auxiliary one. The third-order nonlinear components have different phases according to their classes of amplifiers [17]. As shown in Fig. 8(a), the quasi-dpa can be designed to have opposite phases in the IMD3 output signals of the main and auxiliary amplifiers. Therefore, the linearity of the quasi-dpa is improved through the IMD3 canceling technique. In addi-

7 KIM et al.: QUASI-DOHERTY SOI CMOS PA WITH FOLDED CT 7 Fig. 11. Measurement results with LTE signal. Fig. 10. Measurement results and simulation results with (a) CW signal and (b) WCDMA signal. Fig. 12. Measured 16-QAM constellations (with 4.78% EVM) for 1.85-GHz LTE signal with 16-QAM, 10-MHz bandwidth, and 7.5-dB PAPR at 27.2-dBm average output power and 37.7% PAE. tion, the fundamental components in the two amplifiers must be in-phase for proper power combining. Fig. 8(b) shows the simulated phase differences of fundamentals and IMD3 components at the two amplifier outputs. The IMD3 phase difference points are varied with the control voltages for the APD. With the optimum control voltage (0.6 V), the IMD3 canceling for the quasi-dpa can be achieved. Fig. 8(c) shows the performance [gain and power-added efficiency (PAE)] of the quasi- DPA, which was simulated with two-tone signals. The gains at low output power are varied with the control voltages, which causes from the delivered power difference to main and auxiliary amplifiers. As shown in Fig. 8(d), the IMD3 simula- tion results with the optimum control voltage meet the linearity specifications (under a 30 dbc of IMD3). IV. MEASUREMENT RESULTS A. Implementation The transformer-based quasi-dpa with the proposed folded CT and APD was implemented with an IBM 0.18-μm SOI CMOS process. The overall size of the chip was 1370 μm 1926 μm, and its photograph is shown in Fig. 9. The size of the proposed folded CT is 1050 μm 750 μm, and the drain voltages for the main and auxiliary amplifiers

8 8 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES TABLE III PERFORMANCE COMPARISONS WITH REPORTED CMOS LINEAR PAS AND CMOS DPAS are supplied through the center tap of the transformer. The main amplifier with the APC technique and the auxiliary amplifier with the ADB [15] are connected to combine the fundamental signals. The novel APD circuit is located in front of the auxiliary amplifier to provide the proper power to the auxiliary amplifier. The ADB is adopted to compensate for the small gain of the auxiliary amplifier, which is biased in class-c. The layout sizes of the APD and ADB circuits are 214 μm 52 μm and 134 μm 104 μm, respectively. B. Measurement Results The chip was attached on an FR-4 printed circuit board (PCB) and was connected to the PCB using bonding wires. The performance of the quasi-dpa was measured with an RF signal generator E4438C and a driver amplifier ZVE-8G. The output power of the DPA was measured with an E4418B power meter and an E9301B average power sensor, and an N9030A Agilent signal analyzer with an 89601B VSA was used to test the adjacent channel leakage ratio (ACLR) with the WCDMA signal. The supplied voltage was 3.3 V and the total quiescent current of the quasi-dpa was 46 ma. Fig. 10 shows the performance of the quasi-dpa measured with continuous wave (CW) and WCDMA signals. From 1710 to 1980 MHz, the PA delivered the gains of db. The first peak PAEs of 38.27% 40.8% and the second peak PAEs of 42.4% 45% were measured with CW signal. The PA has a gain variation of 1.7 db from 1710 to 1980 MHz due to the input impedance variation. Using the WCDMA signal, the maximum linear output power levels (Pouts) and the efficiency at the Pout were in ranges of dbm and 38.4% 40.5%, satisfying a linearity requirement of the WCDMA standard (under 33 dbc of ACLR1). Fig. 11 shows the performance of the quasi-dpa measured with LTE signal, which is modulated with 16-quadrature amplitude modulation (QAM), 10-MHz bandwidth, and 7.5-dB PAPR. From 1710 to 1980 MHz, the maximum linear Pouts and the efficiency at the Pout were in ranges of dbm and 36% 37.7%, satisfying linearity requirements for LTE standard (under 30 dbc of ACLR E UTRA ) under the evolved universal terrestrial radio

9 KIM et al.: QUASI-DOHERTY SOI CMOS PA WITH FOLDED CT 9 access (E-UTRA) specification. Fig. 12 shows the modulation test with 1.85-GHz LTE signal at 27.2-dBm average output power. The measured results are compared with those obtained for other recently published CMOS linear PAs and CMOS DPAs in Table III. In comparison with several linear CMOS Pas, which have their own linearized techniques, the proposed quasi-dpa with the novel folded CT and the APD has good average output power and average efficiency with 3.3 V supply voltage. It has better PAE than any other CMOS DPAs at both maximum and 3.5-dB back-off output powers. V. CONCLUSION A transformer-based quasi-doherty SOI CMOS PA was presented, which has a folded CT and an APD circuit. The folded CT occupies a small chip area and shows reduced insertion loss and wide bandwidth characteristics. The APD controls the power delivered to the main and auxiliary amplifiers by adaptively altering its resonating frequency. Most of the power is transferred to the main amplifier at low incoming power, but the power is divided almost equally to the two amplifiers at high incoming power. With CW signal, the quasi-dpa achieves 39.8% and 44.4% PAEs at the first and the second peaks, respectively. At 1850 MHz, it has an average linear output power of 29.2 dbm and a PAE of 40.47%, satisfying a linearity requirement for WCDMA standard (under 33 dbc of WCDMA ACLR1). It delivers an average linear output power of 27.2 dbm and a PAE of 37.7%, satisfying linearity requirements for LTE standard (under 30 dbc of ACLR E UTRA and 5.6% of EVM). ACKNOWLEDGMENT The authors would like to thank H. Choi and S. Kang with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, for their helpful advice and discussions. They would also like to thank the Integrated Circuit Design Education Center, Daejeon, for their support in computer-aided design tools. REFERENCES [1] J. Kim, D. Kim, Y. Cho, D. Kang, B. Park, and B. Kim, Envelopetracking two-stage power amplifier with dual-mode supply modulator for LTE applications, IEEE Trans. Microw. Theory Techn., vol. 61, no. 1, pp , Jan [2] R. Wu, Y.-T. Liu, J. Lopez, C. Schecht, Y. Li, and D. Y. C. Lie, High-efficiency silicon-based envelope-tracking power amplifier design with envelope shaping for broadband wireless applications, IEEE J. Solid-State Circuits, vol. 48, no. 9, pp , Sep [3] T. Nakatani, J. Rode, D. F. Kimball, L. E. Larson, and P. M. Asbeck, Digitally-controlled polar transmitter using a watt-class current-mode class-d CMOS power amplifier and Guanella reverse balun for handset applications, IEEE J. Solid-State Circuits, vol. 47, no. 5, pp , May [4] H. Lee, S. Jang, and S. Hong, A hybrid polar-linc CMOS power amplifier with transmission line transformer combiner, IEEE Trans. Microw. Theory Techn., vol. 61, no. 3, pp , Mar [5] J. Lee, D.-H. Lee, and S. Hong, A Doherty power amplifier with a GaN MMIC for femtocell base stations, IEEE Microw. Wireless Compon. Lett., vol. 24, no. 3, pp , Mar [6] P. Saad, P. Colantonio, L. Piazzon, F. Giannini, K. Andersson, and C. Fager, Design of a concurrent dual-band GHz GaN-HEMT Doherty power amplifier, IEEE Trans. Microw. Theory Techn., vol. 60, no. 6, pp , Jun [7] D. Kang, D. Kim, Y. Cho, B. Park, J. Kim, and B. Kim, Design of bandwidth-enhanced Doherty power amplifiers for handset applications, IEEE Trans. Microw. Theory Techn., vol. 59, no. 12, pp , Dec [8] Y. Cho, D. Kang, J. Kim, K. Moon, B. Park, and B. Kim, Linear Doherty power amplifier with an enhanced back-off efficiency mode for handset applications, IEEE Trans. Microw. Theory Techn., vol. 62, no. 3, pp , Mar [9] E. Kaymaksut and P. Reynaert, Transformer-based uneven Doherty power amplifier in 90 nm CMOS for WLAN applications, IEEE J. Solid-State Circuits, vol. 47, no. 7, pp , Jul [10] A. D. Pye and M. M. Hella, Analysis and optimization of transformerbased series power combining for reconfigurable power amplifiers, IEEETrans.CircuitsSyst.I,Reg.Papers, vol. 58, no. 1, pp , Jan [11] D. Chowdhury, C. D. Hull, O. B. Degani, Y. Wang, and A. M. Niknejad, A fully integrated dual-mode highly linear 2.4 GHz CMOS power amplifier for 4G WiMax applications, IEEE J. Solid-State Circuits, vol. 44, no. 12, pp , Dec [12] E. Kaymaksut and P. Reynaert, A dual-mode transformer-based Doherty LTE power amplifier in 40 nm CMOS, in Int. Solid State Circuits Conf. Dig. Tech. Papers, Feb. 2014, pp [13] J. R. Long, Monolithic transformers for silicon RF IC design, IEEE J. Solid-State Circuits, vol. 35, no. 9, pp , Sep [14] T. Joo, B. Koo, and S. Hong, A WLAN RF CMOS PA with adaptive power cells, in IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2013, pp [15] B. Koo, Y. Na, and S. Hong, Integrated bias circuits of RF CMOS cascode power amplifier for linearity enhancement, IEEE Trans. Microw. Theory Techn., vol. 60, no. 2, pp , Feb [16] J. Kim, J. Cha, I. Kim, and B. Kim, Optimum operation of asymmetrical-cells-based linear Doherty power amplifiers-uneven power drive and power matching, IEEE Trans. Microw. Theory Techn., vol. 53, no. 5, pp , May [17] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd ed. Norwood, MA, USA: Artech House, [18] B. François et al., A fully integrated watt-level linear 900-MHz CMOS RF power amplifier for LTE-applications, IEEE Trans. Microw. Theory Techn., vol. 60, no. 6, pp , Jun [19] S. Jin, B. Park, K. Moon, M. Kwon, and B. Kim, Linearization of CMOS cascode power amplifiers through adaptive bias control, IEEE Trans. Microw. Theory Techn., vol. 61, no. 12, pp , Dec [20] S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M. Asbeck, A watt-level stacked-fet linear power amplifier in silicon-on-insulator CMOS, IEEE Trans. Microw. Theory Techn., vol. 58, no. 1, pp , Jan [21] B. Koo, T. Joo, Y. Na, and S. Hong, A fully integrated dual-mode CMOS power amplifier for WCDMA applications, in IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, Feb. 2012, pp [22] B. François and P. Reynaert, Highly linear fully integrated wideband RF PA for LTE-advanced in 180-nm SOI, IEEE Trans. Microw. Theory Techn., vol. 63, no. 2, pp , Feb [23] K. Onizuka, K. Ikeuchi, S. Saigusa, and S. Otaka, A 2.4 GHz CMOS Doherty power amplifier with dynamic biasing scheme, in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2012, pp [24] E. Kaymaksut and P. Reynaert, Dual-mode CMOS Doherty LTE power amplifier with symmetric hybrid transformer, IEEE J. Solid-State Circuits, vol. 50, no. 9, pp , Sep Kichul Kim (S 13) received the M.S. degree in electrical engineering from the Gwangju Institute of Science and Technology, Gwangju, South Korea, in He is currently pursuing the Ph.D. degree in electrical engineering with the Korean Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. He was a Research Engineer with Samsung Thales, Yongin, South Korea, from 2007 to 2008, where he was involved with the development of multi-function radar system. His current research interests include CMOS RF power amplifier design for mobile applications, linearization and efficiency enhancement techniques for power amplifiers, SOI CMOS RF switches, and antenna tuners.

10 10 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES Dong-Ho Lee received the B.S., M.S., and Ph.D. degrees from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2000, 2002, and 2007, respectively, all in electrical engineering. He was with the Microwaves Applications Group, Georgia Institute of Technology, Atlanta, GA, USA, from 2007 to 2009, where he developed CMOS power amplifiers for mobile communications. In 2009, he joined Skyworks Solutions, Inc., Cedar Rapids, IA, USA, where he was involved in the design of power amplifiers and front end modules for cellular handsets. In 2010, he joined the Hanbat National University, Daejeon, South Korea, as a Faculty Member. His current research interests include RF power amplifiers, microwave modules, and ground penetrating radar systems. Songcheol Hong (S 87 M 88) received the B.S. and M.S. degrees in electronics from Seoul National University, Seoul, South Korea, in 1982 and 1984, respectively, and the Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in In 1989, he joined the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, as a Faculty Member. In 1997, he held short visiting professorships with Stanford University, Palo Alto, CA, USA, and with Samsung Microwave Semiconductor, Suwon, South Korea. His current research interests include microwave integrated circuits and systems including power amplifiers for mobile communications, miniaturized radar, millimeter-wave frequency synthesizers, and novel semiconductor devices.